SS8021

SS8021 SSC | Alldatasheet

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Technical content

www.SiliconStandard.com 1 of 8 SS8021 8/21/2004 Rev.2.01 Stereo Headphone Power Amplifier

FEATURES

High performance Class AB amplifier High signal-to-noise ratio Low distortion Low power consumption Large output voltage swing Excellent power supply ripple rejection Supply voltage range of 3.0V to 6.5V Surface-mount package - SO-8

APPLICATIONS

DESCRIPTION

The SS8021 is an output-rail-to-rail stereo audio power amplifier housed in an 8-pin SOP package capable of delivering 125mW of continuous power into 16Ω loads and 75mW into 32 Ω loads with THD <0.1% per channel. The gain of the amplifiers can be easily set with two external resistors - R I (input resistor) and RF (feedback resistor). The SS8021 is a dual channel, low voltage, low power, high performance amplifier. The quiescent current is typically 3mA at 5V. With excellent AC performance (small THD), it can be designed into a wide range of headphone driving applications. PIN CONFIGURATION SYMBOL PIN DESCRIPTION OUTA 1 output A INA(neg) 2 inverting input A INA(pos) 3 non-inverting input A VSS 4 negative supply INB(pos) 5 non-inverting input B INB(neg) 6 inverting input B OUTB 7 output B VDD 8 positive supply INA(neg) INA(pos) OUTA VSS VDD OUTB INB(neg) INB(pos) 1 8 INA(neg) INA(pos) OUTA VSS VDD OUTB INB(neg) INB(pos) 1 8 SS8021

ORDERING INFORMATION

SS8021(G)XX Packing: TR Tape and reel : TB Tubes This device is normally supplied with Pb-free lead finish (second-level interconnect) as SS8021G, but can be supplied with a traditional lead finish (SS8021) upon request.

www.SiliconStandard.com 2 of 8 SS8021 8/21/2004 Rev.2.01 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS (Note1) SYMBOL PARAMETER CONDITION MIN MAX UNIT VDD Supply voltage 0 7.0 V Tstg Storage temperature -65 +150 °C Tamb Operating ambient temperature -40 +85 °C ESD ESD voltage HBM - 2 KV Notes: 1. Absolute Maximum Ratings are limits beyond which damage to the device may occur. THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT Rth j-a Thermal resistance from junction to ambient in free air SO8 240 °C/W TEST AND APPLICATION INFORMATION Fig.1 Measurement circuit for inverting application 4 5 8OUTA INA(neg) INA(pos) VSS VDD OUTB INB(neg) INB(pos) SS8021 4 5 8OUTA INA(neg) INA(pos) VSS VDD OUTB INB(neg) INB(pos) VDD VINA VINB 220µF VOUTA RL + C6 100µF 220µF RL VOUTB 2.2µF 2.2µF 1µF VDD VINA 3.9kΩ 3.9kΩVINB 3.9kΩ SS8021 3.9kΩ + 220µF VOUTA RL + C6 100µF 220µF RL VOUTB 2.2µF 2.2µF 100kΩ 100kΩ1µF

www.SiliconStandard.com 3 of 8 SS8021 8/21/2004 Rev.2.01

ELECTRICAL CHARACTERISTICS

VDD = 5 V; V SS= 0V; TA = 25°C; fI= 1kHz; RL = 32Ω connected to VDD/2; unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT Supplies Supply voltage 3.0 5.0 6.5 V Single 3.0 5.0 6.5 V VDD Dual 1.5 2.5 3.25 V VSS Negative supply voltage -1.5 -2.5 -3.25 V IDD Supply current no load - 3.0 5.0 mA Ptot Total power dissipation no load - 15 25 mW DC Characteristics VI(OS) Input offset voltage -50 - 50 mV VCM Common mode voltage 0 - 3.5 V GV Open-loop voltage gain RL = 5kΩ 60 90 - dB IO Maximum output current THD+N <0.1% - 70 - mA RO Output resistance closed-loop - 0.1 - Ω VDD-VOH Output Voltage Swing High Sourcing current = 100mA - 0.4 1 V VOL-VSS Output Voltage Swing Low Sinking current = 100mA - 0.5 1 V PSRR Power supply rejection ratio fi = 1kHz; Vripple(rms) = 100mVrms - 70 - dB α CS Channel separation RL=32Ω ,Cb=1µF, PO=70mW - 65 - dB AC Characteristics THD Total harmonic distortion note 2 - < 0.1 - % fG Unity gain frequency open-loop; RL = 5kΩ - 5 - MHz note 1; RL = 16Ω ; f=1kHz - 125 - mW PO Maximum output power note 1; RL = 32Ω ; f=1kHz - 75 - mW Notes: 1. Values are proportional to VDD; THD+N < 0.1% 2. VDD = 5.0V; VO(P-P) = 4.0V (at 0 dB)

www.SiliconStandard.com 4 of 8 SS8021 8/21/2004 Rev.2.01 CIN=2.2µF, COUT=330µF, Cb=1µF, Av=1, Ri=18kΩ , Rf=18kΩ ; Av=-2, Ri=18kΩ , Rf=36kΩ ; Av=-4, Ri=9kΩ ,Rf=36kΩ ,TA=25°C 0.01 0.02 0.05 0.1 0.2 0.5 1m 200m2m 5m 10m 20m 50m 100m W VDD=5V RL=32Ω Av=-1 20kHz 1kHz 20Hz 0.01 0.02 0.05 0.1 0.2 0.5 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=5V RL=32Ω Po=50mW Av=-1V/V Av=-2V/V Av=-4V/V 0.01 0.02 0.05 0.1 0.2 0.5 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=5V RL=32Ω Av=-1 Po=70mW Po=60mW 0.01 0.02 0.05 0.1 0.2 0.5 2m 200m5m 10m 20m 50m 100m W VDD=5V RL=16Ω Av=-1 20kHz 1kHz 20Hz 0.01 0.02 0.05 0.1 0.2 0.5 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=5V RL=16Ω Po=50mW Av=-4V/V Av=-2V/V Av=-1V/V 0.01 0.02 0.05 0.1 0.2 0.5 1m 100m2m 5m 10m 20m 50m W VDD=3.3V RL=32Ω Av=-1 20kHz 1kHz 20Hz THD+N vs Output Power THD+N vs Frequency THD+N vs Frequency THD+N vs Output Power THD+N vs Frequency THD+N vs Output Power

www.SiliconStandard.com 5 of 8 SS8021 8/21/2004 Rev.2.01 ELECTRICAL CHARACTERISTICS (continued) 0.01 0.02 0.05 0.1 0.2 0.5 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=3.3V RL=32Ω Po=25mW Av=-1V/V Av=-2V/V Av=-4V/V 0.01 0.02 0.05 0.1 0.2 0.5 2m 100m3m 4m 5m 6m 7m 10m 20m 30m 40m 50m 70m W VDD=3.3V RL=16Ω Av=-1 20kHz 1kHz 20Hz 0.01 0.02 0.05 0.1 0.2 0.5 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=3.3V RL=16Ω Po=25mW Av=-4V/V Av=-2V/V Av=-1V/V 10u 100u 20u 30u 40u 50u 60u 70u 80u 90u V 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=5V RL=32Ω Av=-1 Cb=1µF BW=20kHz , No filters A- Weighting -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 d B 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=5V RL=32Ω Av=-1 Po=70mW Cb=1µF Channel B to A Channel A to B -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d B 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD=5V RL=32Ω Av=-1 Vripple=100mVrms Cb=1µF Vpin 3,5=2.5V FORCED THD+N vs Frequency THD+N vs Output Power THD+N vs Frequency Output Noise Channel Separation Power Supply Rejection Ratio

www.SiliconStandard.com 6 of 8 SS8021 8/21/2004 Rev.2.01 ELECTRICAL CHARACTERISTICS (continued) Open Loop Frequency Response

www.SiliconStandard.com 7 of 8 SS8021 8/21/2004 Rev.2.01 ELECTRICAL CHARACTERISTICS (continued) 1.2 1.4 1.6 1.8 2.2 2.4 2.6 Supply Voltage(V) Supply Current (mA) 1.2 1.4 1.6 1.8 2.2 2.4 -50 -25 0 25 50 75 100 125 Temperature (°C) Supply Current (mA) VDD=5V VDD=3V 3.2 3.4 3.6 3.8 4.2 4.4 4.6 4.8 Supply Voltage (V) Offset Voltage (mV) 2.5 3.5 4.5 -50 -25 0 25 50 75 100 125 Temperature (°C) Offset Voltage (mV) VDD=3V VDD=5V 100 150 200 250 300 350 00 . 511 . 522 . 53 VO-Vss(V) Sinking Current(mA) Sinking Current vs. Vo-Vss VDD=5V VDD=3V 100 150 200 250 300 350 00 . 511 . 522 . 53 V DD - VO(V) Sourcing Current(mA) Sourcing Current vs. VDD-Vo VDD=5V VDD=3V Supply Current vs.Supply Voltage Supply Current vs. Temperature Offset Voltage vs. Supply Voltage Offset Voltage vs.Temperature

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. www.SiliconStandard.com 8 of 8 SS8021 8/21/2004 Rev.2.01 PHYSICAL DIMENSIONS 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless other wise specified 4. Controlling di mension is milli me ter converted inch di mensions a re not necessarily exac t. Taping Specification Feed Direction Typical SOP Package Orientation D E H A2 A e B y C L D E H 7° (4X) A2 A e B y C L Θ