SS8000G

SS8000G SSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

www.SiliconStandard.com 1 of 14 SS8000G GSM Power-Management System Handles all GSM baseband power management Input range 2.8V to 5.5V Charger input up to 15V Seven LDOs optimized for specific GSM subsystems High operating efficiency and low stand-by current Li-Ion and NiMH battery charge function SIM card interface Three open-drain output switches to control the LED, alerter and vibrator Thermal overload protection Under-voltage lock-out protection Over-voltage protection Power-on reset and start-up timer QFN-48 package The SS8000 is a power-management system chip optimized for GSM handsets. It contains seven LDOs, one to power each of the critical GSM sub-blocks. Sophisticated controls are available for power-up during battery charging, keypad interface, and RTC alarm. The SS8000 is optimized for maximum battery life featuring a ground current of only 107µA in standby and 187µA when the phone is in operation. The SS8000 battery charger can be used with lithium ion (Li-Ion) and nickel metal hydride (NiMH) batteries. The SS8000 contains three open-drain output switches for LED, alerter and vibrator control. The SIM interface provides the level shift betwe en SIM card and microprocessor. The SS8000 is available in a 48-pin QFN package. The operating temperature range is from -25 °C to +85°C. FEATURES DESCRIPTION

APPLICATIONS

12/06/2004 Rev.2.10 This device is supplied with a Pb-free lead finish (second-level interconnect).

www.SiliconStandard.com 2 of 14 SS8000G

ORDERING INFORMATION

Packing: TR: Tape and reel TY: Tray Package type GQ: QFN-48L, Pb-free lead finish SS8000GQXX LEDEN ALERTEREN VIBRATOREN PWRBB PWRKEY SRCLKEN VREF NC AGND VA AVBAT VTCXO DGND DGND SIMSEL SIO SRST SCLK VM VBAT VIO VRTC RSTCAP RESET CHRIN GATEDRV NC ISENSE CHRCNTL CHRDET BATSNS VSIM SIMIO SIMRST SIMCLK SIMVCC VCORE VBAT DGND VMSEL VASEL BATDET BATUSE LED PGND ALERTER PGND 12 25 VIBRATOR LEDEN ALERTEREN VIBRATOREN PWRBB PWRKEY SRCLKEN VREF NC AGND VA AVBAT VTCXO DGND DGND SIMSEL SIO SRST SCLK VM VBAT VIO VRTC RSTCAP RESET CHRIN GATEDRV NC ISENSE CHRCNTL CHRDET BATSNS VSIM SIMIO SIMRST SIMCLK SIMVCC VCORE VBAT DGND VMSEL VASEL BATDET BATUSE LED PGND ALERTER PGND 12 25 SS8000 VIBRATOR PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS 12/06/2004 Rev.2.10

www.SiliconStandard.com 3 of 14 SS8000G

ELECTRICAL CHARACTERISTICS

(Vbat = 3V-5.5V, CVa=10 µF, CVcore =CVm=4.7mF, CVrtc=0.22µF, CVref=CVtcxo=C Vsim=CVio=1µF, minimum loads applied on all outputs, unless otherwise noted. Typical values are at T A=+25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS Main Controller Battery Input Voltage Range 3 5.5 V Charger Input Voltage Range 15 V Shutdown Supply Current Vbat<2.5V 2.5V<Vbat<3.2V 3.2V<Vbat µA Operation Ground Current All Output on Vtcxo off, all others on Va, Vtcxo off, all others on 187 148 108 500 200 150 µA UVLO on Threshold Vbat 3.15 3.18 3.2 V UVLO Hysteresis Vbat 200 mV Deep Discharging Lockout on Threshold 2.6 V Deep Discharging Lockout Hyster esis 100 mV Thermal Shutdown Threshold 165 °C Thermal Shutdown Hysteresis 25 °C LDO Enable Response Time 250 µs Power Key Input High Voltage PWRKEY 0.7xVbat V Power Key Input Low Voltage PWRKEY 0.3xVbat V PWRBB Input High Voltage PWRBB 1 PWRBB Input Low Voltage PWRBB 0.2 Control Input High Voltage 2 V Control Input Low Voltage VMSEL,SIMSEL,SIMVCC,SR CLKEN,VASEL, BATUSE,LEDEN,VIBRATOREN,ALERTERE N 0.5 V Digital Core Voltage LDO (Vcore) Output Voltage 1.7 1.8 1.9 V Output Short Current Limit 430 mA Load Regulation 0.05mA < I_load< 200mA 1.3 10 mV Line Regulation 3.2V < Vbat < 5.5V 3.3 5 mV Digital IO Voltage LDO (Vio) Output Voltage 2.7 2.8 2.9 V Output Short Current Limit 275 mA Load Regulation 0.05mA<I_load<100mA at Vbat=3.6V 3 10 mV Line Regulation 3.2V<Vbat<5.5V 4.6 5 mV Analog Voltage LDO (Va) Output Voltage 2.7 2.8 2.9 V Output Short Current Limit 400 mA Load Regulation 0.05mA<I_load<150mA at Vbat=3.6V 3.3 10 mV Line Regulation 3.2V<Vbat<5.5V 0.4 5 mV Output Noise Voltage Frequency from 10Hz to 100kHz 50 µVrms Ripple Rejection Frequency from 10Hz to 3kHz Frequency from 3kHz to 1MHz dB VTCXO Voltage LDO (Vtcxo) Output Voltage 2.7 2.8 2.9 V Output Short Current Limit 45 mA Load Regulation 0.05mA<I_load<20mA at Vbat=3.6V 0.1 2 mV Line Regulation 3.2V<Vbat<5.5V 0.4 3 mV Output Noise Voltage Frequency from 10Hz to 100kHz 50 µVrms Ripple Rejection Frequency from 10Hz to 3kHz Frequency from 3kHz to 1MHz dB 12/06/2004 Rev.2.10

www.SiliconStandard.com 4 of 14 SS8000G ELECTRICAL CHARACTERISTICS (cont.) PARAMETER CONDITIONS MIN TYP MAX UNITS RTC Voltage LDO (Vrtc) Output Voltage 1.3 1.5 1.65 V Output Short Current Limit 1.35 mA Off Reverse Input Current 0.02 1 µA Memory Voltage LDO (Vm) 1.8V Output Voltage 1.7 1.8 1.9 V 2.8V Output Voltage 2.7 2.8 2.9 V Output Short Current Limit 315 mA Load Regulation(1.8V) Load Regulation(2.8V) 0.05mA<I_load<150mA at Vbat=3.6V 2.7 4.4 10 mV Line Regulation(1.8V) Line Regulation(2.8V) 3.2V<Vbat<5.5V 2.6 2.8 5 mV SIM Voltage LDO (Vsim) 1.8V Output Voltage 1.65 1.8 1.95 V 3.0V Output Voltage 2.75 3.0 3.1 V Output Short Current Limit 38 mA Load Regulation(1.8V) Load Regulation(3.0V) 0.05mA<I_load<20mA at Vbat=3.6V 1 1.7 2 mV Line Regulation(1.8V) Line Regulation(3.0V) 3.2V<Vbat<5.5V 1.2 3 3 mV Reference Voltage Output Reference Voltage 1.235 V Line Regulation 2.7V<Vbat<5.5V without load 0.3 2 mV Output Noise Voltage Frequency from 10Hz to 100kHz 40 µVrms Ripple Rejection Frequency at 217Hz 65 75 dB Reset Generator Reset Output High Voltage Vio-0.5 V Reset Output Low Voltage 0.2 V Reset Output Current 1 mA Reset on Delay Time per unit Cap. 2 ms/nF LED/Alerter/Vibrator Driver Sink Current of LED Driver Von<0.3V 150 mA Sink Current of Alerter Driver Von<0.3V 300 mA Sink Current of Vibrator Driver Von<0.5V 250 mA Battery Charger Charge Output Voltage (Li-ion Battery) BATUSE=0 4.2 V Charge Output Voltage (NiMH Battery) BATUSE=1 5.1 V Chr_Det On Threshold (Chrin-Vbat)/Vbat , Chrin>4V 3.75 % Chr_Det Off Threshold (Chrin-Vbat)/Vbat , Chrin>4V 2.5 % Pre-charging Current I_charge@Vbat=3V(UVLO Active), R1=0.2 Ω 50 mV GSM Interface Vih(SIMCLK,SIMRST) Vio-0.6 V Vil (SIMCLK,SIMRST) 0.6 V Vol? 0.4V, Iol=1mA 0.23 V Vilsimio Vol? 0.4V, Iol=0mA 0.335 V Vihsimio , Vohsimio Iih,Ioh=± 20µA Vio-0.6 V Iilsimio Vil=0V -0.9 mA Volsimio Vil=0.4V 0.42 V SIMIO Pull-up Resistance to Vio 16 20 24 KΩ 12/06/2004 Rev.2.10

www.SiliconStandard.com 5 of 14 SS8000G ELECTRICAL CHARACTERISTICS (cont.) PARAMETER CONDITIONS MIN TYP MAX UNITS Interface to 3V SIM card Volrst I=20µA 0.4 V Vohrst I=-200µA 0.9Vsim V Volclk I=20µA 0.4 V Vohclk I=-200µA 0.9Vsim V Vil 0.4 V Vihsio , Vohsio I=± 20µA Vsim-0.4 V Iil Vil=0V -1 mA Vol Iol=1mA , SIMIO? 0.23V 0.4 V Interface to 1.8V SIM card Volrst I=20µA 0.2Vsim V Vohrst I=-200µA 0.9Vsim V Volclk I=20µA 0.2Vsim V Vohclk I=-200µA 0.9Vsim V Vil 0.4 V Vihsio , Vohsio I=± 20µA Vsim-0.4 V Iil Vil=0V -1 mA Vol Iol=1mA , SIMIO? 0.23V 0.4 V SIM Card Interface Timing SIO Pull-up Resistance to Vsim 8 10 12 KΩ SRST , SIO rise/fall time Vsim=3/1.8V, load with 30pF 1 µS Vsim=3V, CLK load with 30pF 18 nS SCLK rise/fall time Vsim=1.8V, CLK load with 30pF 50 nS SCLK frequency CLK load with 30pF 5 Mhz SCLK duty cycle SIMCLK Duty=50%, fsimclk=5Mhz 47 53 % SCLK Prop. Delay 30 50 nS 12/06/2004 Rev.2.10

www.SiliconStandard.com 6 of 14 SS8000G PIN DESCRIPTIONS PIN NAME FUNCTION

1 CHRIN Charger Input Voltage

2 GATEDRV Gate Drive Output

3,29 NC

4 ISENSE Charger Current Sense Input

5 CHRCNTL Microprocessor Control Input Signal for Gate Drive

6 CHRDET Charger Detect Output

7 BATSNS Battery Input Voltage Sense

8 VSIM SIM Supply

9 SIMIO Non-Level-Shifted Bidirectional Data I/O

10 SIMRST Non-Level-Shifted SIM Reset Input

11 SIMCLK Non-Level-Shifted SIM Clock Input

12 SIMVCC SIM Enable

13 SIMSEL High for Vsim=3.0V, Low for Vsim=1.8V

14 SIO Level-Shifted SIM Bidirectional Data Input/Output

15 SRST Level-Shifted SIM Reset Output

16 SCLK Level-Shifted SIM Clock Output

17,21,46 DGND Digital Ground

18 VM Memory Supply

19 VBAT Battery Input Voltage

20 VIO Digital IO Supply

22 VRTC Real Time Clock Supply

23 RSTCAP Reset Delay Time Capacitance

24 /RESET System Reset, Low Active

25 VTCXO TCXO Supply

26 AVBAT Battery Input Voltage for Analog Block Circuits

27 VA Analog Supply

28 AGND Analog Ground

30 VREF Reference Voltage Output

31 SRCLKEN VTCXO and VA Enable

32 PWRKEY Power on/off Key

33 PWRBB Power on/off Signal from Microprocessor

34 VIBRATOREN Vibrator Driver Enable

35 ALERTEREN Alerter Driver Enable

36 LEDEN LED Driver Enable

37,40 PGND Power Ground

38 VIBRATOR Vibrator Driver Input

39 ALERTER Alerter Driver Input

41 LED LED Driver Input

42 BATUSE Battery Type Selection, High for NiMH, Low for Li -ion

43 BATDET Battery Detect Output

44 VASEL High for VA enabled with VTCXO, Low for VA enabled wit h VD

45 VMSEL High for Vm=2.8 V, Low for Vm=1.8V

47 VBAT Battery Input Voltage

48 VCORE Digital Core Supply

12/06/2004 Rev.2.10

www.SiliconStandard.com 7 of 14 SS8000G

APPLICATION INFORMATION

The SS8000 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows the block diagram of the SS8000. Seven low-dropout regulators (core, digital I/O, analog, crystal oscillator, real-time clock, memory, SIM) SIM card interface Vibrator, alerter, and LED drivers Power sequence and protection logic Reset generator Under-voltage lockout Deep discharge lockout Battery charger Figure 1. Functional Block Diagram

22 VRTC

25 VTCXO

www.SiliconStandard.com 8 of 14 SS8000G APPLICATION INFORMATION (cont.) Low Dropout Regulator ( LDOs ) and Reference The SS8000 integrates seven LDOs that are optimized for their given functions by balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise. Digital Core LDO (Vcore) The digital co re LDO is a regulator that can source 200mA (max) with 1.8V output voltage. It supplies the baseband circuitry in the handset. The LDO is optimized for very low quiescent current. Digital IO LDO (Vio) The digital I/O LDO is a regulator that can source 100mA (max) with 2.8V output voltage. It supplies the baseband circuitry in the handset. The LDO is optimized for very low quies cent current and will power up at the same time as the digital core LDO. Analog LDO (Va) The analog LDO is a regulator that can source 150mA (max) with 2.8V output voltage. It supplies the analog sections of the baseband chips ets. The LDO is opt i- mized for low frequency ripple rejection in order to reject the ripple coming from the RF power amplifier burst fr e- quency at 217kHz. TCXO LDO (Vtcxo) The TCXO LDO is a regulator that can source 20mA (max) with 2.8V output voltage. It supplies the temperature com- pensated crystal oscillator, which needs its own ultra low noise supply and very good ripple rejection ratio. RTC LDO (Vrtc) The RTC LDO is a regulator that can source 200 µA (max) with 1.5V output voltage. It charges up a capac i- tor-type backup coin cell to run the real -time clock mod- ule. The LDO features the reverse current protection and is optimized for ultra low quiescent current since it is always on except when the battery voltage is below 2.5V. Memory LDO (Vm) The memory LDO is a regulator that can source 150mA (max) with 1.8V or 2.8V output voltage , select ed ac- cording to the supply specs of the memory chips. It sup- plies the memory circuitry in the handset. The LDO is optimized for very low quiescent current and will power up at the same time as the digital core LDO. SIM LDO (Vsim) The SIM LDO is a regulator that can source 20mA (max) with 1.8V or 3.0V output voltage , selected according to the supply specs of the subscriber identity modules (SIM) card. It supplies the SIMs in the handset. The LDO is controlled independently of the others LDO. Reference Voltage Output (Vref) The reference voltage output is a low noise, high PSRR and high precision reference with a guaranteed accuracy of 1.5% over temperature. It is used as an internal system reference within the SS8000. However, to maintain ac- curate specs on every LDO output voltage, it is important to avoid loading the reference voltage and it should be bypassed to GND with 100 nF minimum. SIM Card Interface The SIM card interface circuitry of the SS8000 meets all ETSI and IMT -2000 SIM interface requirements. It provides level shifting needs for the low -voltage GSM controller to communicate with either 1.8V or 3V SIM cards. All SIM cards contain a clock input, a reset i nput, and a bi -directional data input/output. The clock and reset inputs to SIM cards are level shifted from the su p- ply of the digital IO (Vio) of the baseband chipset to the SIM supply (Vsim). The bi -directional data bus is in ter- nally pulled high with a 20kohm resistor on the controller side and with a 10kohm resistor on the SIM side. All pins that connect to the SIM card (Vsim, SRST, SCLK, SIO) withstand over 5kV of human -body-mode ESD. In order to ensure proper ESD protection, careful board layout is required. Vibrator, Alerter, LED Switches Three built -in open -drain output switches drive the vi- brator motor, alerter beeper and LEDs in the handset. Each switch is controlled by the baseband chipset with enable pins. The LED switch can sink 150mA to drive up to 10 LEDs simultaneously for backlight. The vibr ator switch can sink 250mA for a vibrator motor. The alerter switch can sink 300mA to drive the beeper. All the open-drain output switches are high impedance when disabled. 12/06/2004 Rev.2.10

plying the adapter will not start up the LDOs. Table 1. States of Mobile Handset and LDO the battery decays to below 3.0V. SS8000 draws 5µA of quiescent current. turn off the phone when the battery drops below 3.0V. At power-off, RESET will be kept low. new power-on sequence is required to enable the LDOs. pin from the baseband chipset.

Figure 2. Batter Charger Flow Chart

Figure 3. Typical Application Circuit

current charging mode is used. voltage is applied to the batter y and keeps it at 4.2V. charger block of the SS8000. Table 2. Charger and Voltage Detection Notes: OV terminates charging at 4.3V for Li-ion battery or 5.1V for NiMH battery.

www.SiliconStandard.com 13 of 14 APPLICATION INFORMATION (cont.) SS8000G External Components Selection Input Capacitor Selection For each of the input pins (V BAT) of the SS8000, a 10µF, low ESR capacitor is recommended for local by- pass. MLCC capacitors provide the best co mbination of low ESR and small size. Using a 10µF tantalum capaci- tor with a small (1 µF or 2.2 µF) ceramic in pa rallel is an alternative low cost solution. For the charger input pin (CHRIN), a 1 µF ceramic ca- pacitor is recommended for bypass. LDO Capacitor Selection The digital core, analog, and memory LDOs require a 4.7µF capacitor, the digital IO and SIM TCXO LDOs require a 1µF capacitor and the RTC LDO require s a 0.22µF capacitor. Larger value capacitors may be used for improved noise or PSRR performance, but do not forget to consider the settling time that is a cceptable for the application. For these, MLCC is recommended. RESET Capacitor Selection RESET is held low during power-up for a delay until the LDOs are up. The delay is set by an external capacitor on the RESCAP pin. It can be determined by Eq.(1). A 100nF capacitor will produce a 200ms delay. Setting the Charge Current The SS8000 is capable of charging the battery with a charging current programmed by an external sense re- sistor, Rsen. It is calculated using Eq.(3). If the charge current is defined, Rsen can be found. Appropriate sense resistors are available from the fo l- lowing vendors: Vishay Dale, IRC, Panasonic. Charger FET Selection In selecting the P-channel MOSFET for the charger, consider the minimum drain -source breakdown voltage (BVDS), the minimum turn-on threshold voltage (VGS), and current-handling and power-dissipation capabilities. Charger Diode Selection The diode shown in Figure 3 is used to prevent the bat- tery from discharging through the P-channel MOSFETs body-diode into the charger’s internal circuits. Choose a diode with a current rating high enough to handle the battery char ging current and a voltage rating greater than Vbat. Layout Guidelines Use the following general guidelines when designing the printed circuit boards: 1. Split the battery connection to the VBAT, AVBAT pins of the SS8000. Locate the input capacitor as close to the pins as possible. 2. Va and Vtcxo capacitors should be returned to AGND. 3. Split the ground connec tion. Use separate traces or planes for the analog, digital, and power grounds (i.e. AGND, DGND, PGND pins of the SS8000, respec- tively) and tie them together at a single point, prefera- bly close to the battery return. 4. Run a separate trace from the BATSNS pin to the battery to prevent any voltage drop error in the meas- urement. 5. Kelvin-connect the charge -current sense -resistor by running separate traces to the BATSNS and ISENSE pins. Make sure that the traces are term inated as close to the resistor’s body as possible. 6. Careful use of copper area, weight, and multi -layer construction will help to improve thermal performance. 12/06/2004 Rev.2.10

www.SiliconStandard.com 14 of 14 PHYSICAL DIMENSIONS Note: Coplanarity applies to leads, corner leads and die attach pad. D 7 BSC 0.276 BSC E 7 BSC 0.276 BSC e 0.5 BSC 0.020 BSC P 45° REF 45° REF Taping Specification 4837 P 48X L 48X b0.1 M C A B J PIN 1 CORNER EXPOSED DIE ATTACH PAD

0.1 C A B

K e e/2 VIEW M -M 0.1 C PIN 1 CORNER DA E B M M A1 A2 A 0.1 C 0.08 C C 4837 P 48X L 48X b0.1 M C A B0.1 M C A B J PIN 1 CORNER EXPOSED DIE ATTACH PAD 0.1 C A B0.1 C A B K e e/2 VIEW M -M 0.1 C0.1 C PIN 1 CORNER DA E B M M A1 A2 A 0.1 C 0.08 C0.08 C C Feed Direction Typical QFN Package Orientation Feed Direction Typical QFN Package Orientation Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infr ingement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. SS8000G 12/06/2004 Rev.2.10