SS6804ACSTB

SS6804 SSC | Alldatasheet

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Technical content

www.SiliconStandard.com 1 of 12 SS6804 Three/Four-cell Lithium-Ion Battery Protection IC

FEATURES

Ultra-low quiescent current, 17µA (4-cell, Vcell = 3.5V). Ultra-low power-down current, 2.2µA (4-cell, Vcell = 2.3V). Wide supply voltage range: 2V to 18V. Precision over-charge protection voltage: 4.35V±30mV for the SS6804A 4.30V±30mV for the SS6804B 4.25V±30mV for the SS6804C 4.20V±30mV for the SS6804D Externally set over-charge, over-discharge and over-current delay time. Built-in cell-balancing bleeding network under over-charge condition. Three detection levels for over-current protection.

APPLICATIONS

Protection IC for three/four-cell lithium-ion battery packs.

DESCRIPTION

The SS6804 is designed to protect a lithium-ion battery from damage or degraded lifetime due to over-charging, over-discharging and over-current for three- or four-cell lithium-ion battery powered systems such as notebook PCs. It provides the cell-balancing "bleeding" function to automatically discharge the over-charged cell until the over-charge condition is eliminated. Safe charging with full utilization is ensured by the accurate ±30mV over-charge detection. Four different specification values for over-charge protection voltage are provided for various protection requirements. The very low standby current represents little drain from the cell while in storage. TYPICAL APPLICATION CIRCUIT 0.1µF 0.1µF 0.1µF 0.1µF BATT-SS6804 1 16 OC 2 CS 3 OD TD TI TC GND 9 UD4 33K UD3 11 VC3 BAT4 200 UD2 VC2 BAT3 UD1 VCC BAT1 VC1 BAT2 NSL BATT+ FUSE M2M1SSM4435M SSM4435M 2N3906 CTC 82nF CTD 82nF CTI 2.2nF Protection Circuit for Four-Cell Lithium-Ion Battery Pack 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 2 of 12 SS6804 /G01 /G01 ORDERING INFORMATION PIN CONFIGURATION SS6804XCXXX Packing type TR: Tape and reel TB: Tube Package type S: SO-16 Over-charge Protection Voltage A: 4.35V B: 4.30V C: 4.25V D: 4.20V Example: SS6804ACSTR $/G014.35V version, in SO-16, shipped on tape and reel TOP VIEW OC CS TC OD NSL TI VCC UD1 TD VC2 VC1 UD2 UD3 VC3 UD4 9GND ABSOLUTE MAXIMUM RATINGS /G21/G0C/G22/G22/G03/G23/G01/G17/G09/G03/G04/G06/G24/G0E/G01 /G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G44/G44/G44/G44/G44/G44/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G01/G13/G27/G17/G01 /G1D/G12/G01/G17/G09/G03/G04/G06/G24/G0E/G01/G15/G22/G22/G03/G0D/G0E/G20/G01/G09/G11/G01/G09/G04/G2A/G0E/G05/G01/G1C/G0D/G11/G0F/G01 /G19/G19/G19/G19/G19/G19/G19/G19/G19/G44/G44/G44/G44/G44/G44/G44/G19/G19/G44/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G01/G13/G27/G17/G01 /G28/G22/G0E/G05/G06/G04/G0D/G11/G24/G01/G34/G0E/G2D/G22/G0E/G05/G06/G04/G0C/G05/G0E/G01/G25/G06/G11/G24/G0E/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G44/G44/G44/G44/G44/G44/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G01/G07/G1E/G2C°/G12/G45/G46/G2C°/G12/G01/G01/G01/G01/G01 /G21/G04/G09/G05/G06/G24/G0E/G01/G34/G0E/G2D/G22/G0E/G05/G06/G04/G0C/G05/G0E/G01/G01/G25/G06/G11/G24/G0E/G01/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G44/G44/G19/G19/G44/G44/G44/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G19/G01/G01/G07/G01/G43/G1A°/G12/G01/G45/G13/G1E/G1A°/G12/G01 /G01 /G01 TEST CIRCUIT IOC S1 ROC VOC VCS UD1 SS6804 VCCNSL OC VC1 UD3 VC3 UD4 UD2 VC2 VOD OD CS3 TI TD 7 TC GND8 ICC IUD1 R1 200 0.1µF VCC IC1 IUD2 R2 2K 0.1µF VC1 IC2 IUD3 R3 2K 0.1µF VC2 IC3 IUD4 R4 33K 0.1µF VC3 CTD 1nF CTC 1nF CTI 2.2nF 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 3 of 12 SS6804 ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT VCC Pin Input Current in Normal Mode VCELL=3.5V I CC 17 26 µA VC1 Pin Input Current in Normal Mode V CELL=3.5V I C1 0.7 1.8 µA VC2 Pin Input Current in Normal Mode V CELL=3.5V I C2 0.4 1.0 µA VC3 Pin Input Current in Normal Mode V CELL=3.5V I C3 0.2 0.5 µA Vcc Pin Input Current in Power- Down Mode V CELL=2.3V I CC(PD) 2.2 4.0 µA VC1,VC2,VC3 Input Current in Power-Down Mode V CELL=2.3V I C(PD) 0.01 0.15 µA SS6804A 4.32 4.35 4.38 SS6804B 4.27 4.30 4.33 SS6804C 4.22 4.25 4.28 Overcharge Protection Voltage SS6804D VOCP 4.17 4.20 4.23 V Overcharge Hysteresis Voltage V HYS 150 200 250 mV Overdischarge Protection Voltage V ODP 2.27 2.40 2.53 V Overdischarge Release Voltage VODR 2.85 3.00 3.15 V Overcurrent Protection Voltage V CELL=3.5V V OIP 135 150 165 mV Overcharge Delay Time VCELL1=VOCP - 30mV →VOCP+30mV VCELL2= VCELL3= VCELL4= 3.5V, CTC=1nF TOC 10 21 32 mS Overdischarge Delay Time VCELL1= 2.5V→ 2.3V VCELL2= VCELL3= VCELL4= 3.5V, CTD=1nF TOD 10 21 32 mS Overcurrent Delay Time (1) VCELL= 3.5V,0.15V<VCC - VCS <0.3V,CTI=2.2nF TOI1 7 15 23 mS 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 4 of 12 SS6804 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT Overcurrent Delay Time (2) VCELL=3.5V, 0.3V<VCC-VCS<1.0V TOI2 2 4 6 mS Overcurrent Delay Time (3) V CELL=3.5V, VCC– VCS>1.0V T OI3 150 300 450 µS OC Pin Sink Current VCELL1=4.4V, VCELL2= VCELL3= VCELL4=3.5V, OC Pin Short to VCC IOC 2.2 3.2 4.2 mA OD Pin Output “H” Voltage V DH VCC-0.15V VCC-0.03V V OD Pin Output “L” Voltage V DL 0.01 0.15 V Charge Detection Threshold Voltage VCELL=2.3V V CH VCC+0.4 VCC+0.55 V UD1 Pin Cell-Balancing Bleeding Current V CELL1=4.4V, VCELL2= VCELL3= VCELL4=3.5V IUD1 6.5 9.3 12.1 mA UD2 Pin Cell-Balancing Bleeding Current V CELL2=4.4V, VCELL1= VCELL3= VCELL4=3.5V IUD2 6.3 9.0 11.7 mA UD3 Pin Cell-Balancing Bleeding Current V CELL3=4.4V, VCELL1= VCELL2= VCELL4=3.5V IUD3 6.2 8.8 11.4 mA UD4 Pin Cell-Balancing Bleeding Current V CELL4=4.4V, VCELL1= VCELL2= VCELL3=3.5V IUD4 6.4 9.2 12.0 mA Note: VCELL means the battery cell voltage. Therefore, VCELL1 = VCC – VC1 VCELL2 = VC1 – VC2 VCELL3 = VC2 – VC3 VCELL4 = VC3 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 5 of 12 SS6804 TYPICAL PERFORMANCE CHARACTERISTICS Fig. 1 Vcc Pin Input Current vs. Supply Voltage Vcc Pin Input Current (µA) Supply Voltage (V) TA=25°C 1.0 1.2 1.4 1.6 1.8 2.0 2.2 TA=25°C Fig. 2 Vcc Pin Power-Down Current vs. Supply Voltage Vcc Pin Power-Down Current (µA) Supply Voltage (V) - 2 0 - 1 00 1 02 03 04 05 06 07 014 Fig. 3 Vcc Pin Input Current vs. Temperature VCELL =3.5V Vcc Pin Input Current (µA) Temperature (°C) - 2 0 - 1 00 1 02 03 04 05 06 07 01.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VCELL=2.3V Fig. 4 Vcc Pin Power-Down Current vs. Temperature Vcc Pin Power-Down Current (uA) Temperature (°C) 4.20 4.22 4.24 4.26 4.28 4.30 Fig. 5 Overcharge Protection Voltage vs. Temperature Overcharge Protection Voltage (V) -20 0 20 40 60 70 SS6804C Temperature (°C) 2.36 2.37 2.38 2.39 2.40 2.41 2.42 - 2 0 - 1 00 1 02 03 04 05 06 07 0 Fig. 6 Overdischarge Protection Voltage vs. TemperatureOverdischarge Protection Voltage (V) Temperature (°C) 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 6 of 12 SS6804 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 148.0 148.5 149.0 149.5 150.0 150.5 151.0 151.5 152.0 Fig. 7 Overcurrent Protection Voltage vs. Temperature Overcurrent Protection Voltage (V) - 2 0 - 1 00 1 02 03 04 05 06 07 0 Temperature(°C) VCELL=3.5V Fig. 8 Overcharge/Overdischarge Delay Time vs. Temperature - 2 0 - 1 00 1 02 03 04 05 06 07 0 CTC /CTD=1nF Overcharge/Overdischarge Delay Time (mS)Temperature(°C) - 2 0 - 1 00 1 02 03 04 05 06 07 010 VCELL =3.5V Fig. 9 Overcurrent Delay Time 1 vs. Temperature Overcurrent Delay Time 1 (mS) Temperature (°C) Temperature (°C) - 2 0 - 1 00 1 02 03 04 05 06 07 0 4.02 4.03 4.04 4.05 4.06 4.07 4.08 Fig. 10 Overcharge Release Voltage vs. Temperature Overcharge Release Voltage (V) - 2 0 - 1 0 0 1 02 03 04 05 06 07 0 2.97 2.98 2.99 3.00 3.01 o Fig. 11 Overdischarge Release Voltage vs. Temperature Overdischarge Release Voltage (V) Temperature (°C) 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 7 of 12 SS6804 /G01 /G01 BLOCK DIAGRAM Battery Voltage Sense Circuit 450 400 350 300

12 VC2

14 VC1

16 VCC

VCC-0.3V VCC-0.15V VCC+0.4V Power-Down Control 1.2V Overcharge Delay Circuit Overcurrent Delay Circuit TI TD Overdischarge Delay Circuit PIN DESCRIPTIONS PIN 1: NSL- Input pin for cell number selection. Connect this pin to VCC for three-cell application and to GND for four-cell application. PIN 2: OC- NMOS open drain output for control of the charge control MOSFET M2. When overcharge occurs, this pin sinks current to switch the external PNP Q1 on, and charging is inhibited by turning off the charge control MOSFET M2. PIN 3: CS- Input pin for current sensing. Using the drain-source voltage of the discharge control MOSFET M1 (voltage between VCC and CS), it senses the discharge current during normal mode and detects whether charging current is present during power-down mode. PIN 4: OD - Output pin for control of discharge control MOSFET M1. When overdischarge occurs, this pin goes high to turn off the discharge control MOSFET M1 and discharging is inhibited. PIN 5: TD - Overdischarge delay time setting pin. PIN 6: TI - Overcurrent delay time setting pin. PIN 7: TC - Overcharge delay time setting pin. PIN 8: GND - Ground pin. This pin is to be connected to the negative terminal of the battery cell BAT4. PIN 9: UD4- This pin is to be connected to the positive terminal of the battery cell BAT4 for cell-balancing bleeding function under overcharge condition. 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 8 of 12 SS6804 PIN10: VC3- Input pin for battery BAT4 voltage sensing. This pin is to be connected to the positive terminal of the battery cell BAT4. PIN11: UD3 - This pin is to be connected to the positive terminal of the b a t t e r y c e l l B A T 3 f o r c e l l - balancing bleeding function under overcharge condition. PIN12: VC2 - Input pin for battery BAT3 voltage sensing. This pin is to be connected to the positive terminal of the battery cell BAT3. PIN13: UD2 - This pin is to be connected to the positive terminal of the battery cell BAT2 for cell-balancing bleeding function under overcharge condition. PIN14: VC1 - Input pin for battery BAT2 voltage sensing. This pin is to be connected to the positive terminal of the battery cell BAT2. PIN15: UD1 - positive terminal of the battery BAT1 for cell-balancing bleeding function under overcharge condition. PIN16: VCC - Power supply pin and input for battery BAT1 voltage sensing. This pin is to be connected to the positive terminal of the battery cell BAT1.

APPLICATION INFORMATION

On initial power-up, such as connecting the batte ry pack for the first ti me to the SS6804, the SS6804 enters the power-down mode. A cha rger must be app lied to the SS6804 circuit to enable the pack. Overcharge Protection When the voltage of either of the battery cells exceeds the overcharge protection voltage OCP) beyond the overcharge delay time (T OC) period, charging is inhibited by the turning-off of the charge control MOSFET M2. The overcharge delay time is set by the external capacitor C TC. Inhibition of charging is immediately released when the voltage of the overcharged cell becomes lower than overcharge release voltage (V OCR or VOCP-VHYS) through discharging. Overdischarge Protection When the voltage of either of the battery cells falls below the overdischarge protection voltage ODP) beyond the overdischarge delay time (TOD) period, discharging is inhibited by the turning-off of the discharge control MOSFET M1. The overdischarge delay time is set by the external capacitor C TD. Inhibition of discharging is immediately released when the voltage of the overdischarge cell becomes higher than the overdischarge release voltage (V ODR) through charging. Overcurrent Protection In no rmal mode, the SS6804 continuously monitors the discharge current by sensing the voltage of CS pin. If the voltage V CC-VCS exceeds the overcurrent protection voltage (V OIP) beyond the overcurrent delay time (T OI) period, the overcurrent protection circuit operates and discharging is inhibited by the turning-off of the discharge control MOSFET M1. Discharging must be inhi bit ed for at least 256 ms after overcurrent takes place to avoid damage to external control MOSFETs due to rapidly switching transient between BATT+ and BATT- terminals. The overcurrent condition returns to normal mode when the load is released and the impedance between the BATT+ and BATT- terminals is 20M Ω or higher. The SS6804 is provided with the three 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 9 of 12 SS6804 overcurrent detection levels (0.15V, 0.3V and 1.0V) and the three overcurrent delay time ( TOI1, TOI2 and T OI3) corresponding to each overcurrent detection level. T OI1 is set by the external capacitor C TI. T OI2 and T OI3 default to 4ms and 300 µs respectively, and can not be adjusted due to protection of external MOSFETs Cell-Balancing Bleeding after Overcharge When either of the battery cells is overcharged, the SS6804 provides the cell-balancing bleeding function to discharge the overcharged cell at about 9mA until the voltage of the overcharged cell decreases to overcharge release voltage (V OCR or V OCP-VHYS). Connecting UD1, UD2, UD3 and UD4 pins to the positive terminals of battery cells BAT1, BAT2, BAT3 and BAT4 accomplish this function, respectively. Inserting resistors along UD2 pin to BAT2 positive terminal path and UD4 pin to BAT4 positive terminal path can decrease the bleeding current. Power-Down after Overdischarge When overdischarge occurs, the SS6804 will go into power-down mode, turning off all the timing generation and detection circuitry to reduce the quiescent current to about 2.2 µA (VCC=9.2V). In the unusual case where one battery cell is overdischarged while another one under overcharge condition, the SS6804 will turn off all the detection circuitry except the overcharge detection circuit for the cell under overcharge condition. Charge Detection after Overdischarge When overdischarge occurs, the discharge control MOSFET M1 turns off and discharging is inhibited. However, charging is still permitted through the parasitic diode of M1. Once the charger is connected to the battery pack, the SS6804 immediately turns on all the timing generation and detection circuitry and goes into normal mode. Charging is determined to be in progress if the CS pin voltage is higher than VCC + 0.4V (charge detection threshold voltage V CH). DESIGN GUIDE Cell Number Selection The user must configure the SS6804 for three or four series cells application. For three-cell application, NSL pin should be connected directly to VCC pin. For four-cell application, NSL pin should be connected directly to GND pin. No. of Series Cells NSL Pin 3-cell Connected to VCC 4-cell Connected to GND The protection circuit for three-cell lithium-ion battery pack is shown in application examples Fig. 1. Setting the Overcharge and Overdischarge Delay Time The overcharge delay time is set by the external capacitor CTC and the overdischarge delay time is set by the external capacitor C TD. The relationship between capacitance of the external capacitors and delay time is tabulated as below. CTC ‚CTD(nF) TOC ‚TOD(ms) 1 21 5 52 10 132 22 253 33 347 47 617 68 748 82 1004 100 1630 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 10 of 12 SS6804 The del ay time can al so be app roximately calculated by the following equations (if C TC, CTD ≤ 82nF) : TOC(mS) = 11.8 x CTC(nF) TOD(mS) = 11.8 x CTD(nF) Setting the Overcurrent Delay Time 1 The overcurrent delay time 1 (T OI1) at 0.15V < VCC-VCS < 0.3V is set by the external capacitor CTI, while the overcurrent delay time 2 and 3 (TOI2 and TOI3) is fixed by IC internal circuit.The relationship between capacitance of the external capacitor and delay time is tabulated as below. CTI (nF) TOI (ms) 1 4.8 2.2 15.0 3.3 18.8 5 23.6 6.8 31.0 10 61.8 Selection of External Control MOSFETs Because the overcurrent protection voltage is preset, the threshold current for overcurrent detection is determined by the turn-on resistance of the discharge control MOSFET M1. The turn-on resistance of the external control MOSFETs can be determined by the equation: R ON=VOIP/IT (I T is the overcurrent threshold current). For example, if the overcurrent threshold current I T is designed to be 5A, the turn-on resistance of the external control MOSFETs must be 30m Ω. Users should be aware that turn-on resistance of the MOSFET changes with temperature variation due to heat dissipation. It changes with the voltage between gate and source as well. (Turn-on resistance of a MOSFET increases as the voltage between gate and source decreases). Once the turn-on resistance of the external MOSFET changes, the overcurrent threshold current will change accordingly. Suppressing the Ripple and Disturbance from Charger To suppress the ripple and disturbance from charger, connecting R1 to R4 and C1 to C4 is recommended. Larger R1 will cause larger error of battery sense voltage. Controlling the Charge Control MOSFET R5, R6, R7 and NPN transistor Q1 are used to switch the charge control MOSFET M2. If overcharge does not occur, no current flows into OC pin and Q1 is turned off, then M2 is turned on. When overcharge occurs, current flows into OC pin and Q1 is turned on, which turns off M2 in turn. Protection at CS Pin R8 is used for protection of IC when charger is connected in reverse. The charge detection function after overdischarge is possibly disabled by larger value of R8. Resistance of 1K Ω is recommended. 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 11 of 12 SS6804 APPLICATION EXAMPLE 0.1µF BAT1 BAT2 BAT3 0.1µF 0.1µF 0.1µF BATT- CTD 82nF CTI 2.2nF CTC 82nF SS6804 OC CS3 OD TD TI TC GND UD4 UD3 VC3 UD2 VC2 UD1 VCC VC1 NSL BATT+ FUSEM2M1SSM4435M SSM4435M 2N3906 Fig. 12 Protection Circuit for Three-Cell Lithium-Ion Battery Pack TIMING DIAGRAM z Overcharge and Overdischarge Protection (VCS=VCC) BAT4V BAT1V BAT2V ODT BAT3V CELL OD<T OC<T TOC Hi-ZHi-Z V VOC VOD CCV OCPV ODPV ODRV HYSVOCPV - 12/29/2003 Rev.2.0 2

www.SiliconStandard.com 12 of 12 SS6804 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. /G01 Overcurrent Protection (VCELL=3.5V) VCC CCV - 1V - 0.3V - 0.15V OI1T VCC CCV CCV OCV ODV CSV <256ms <256ms 256ms Hi-Z <TOI1OI3<TOI2 >256ms T PHYSICAL DIMENSIONS

16 LEAD PLASTIC SO (150 mil) (unit: mm)

A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 9.80 10.00 E 3.80 4.00 e 1.27 (TYP) H 5.80 6.20 L 0.40 1.27 E e D B C A L H 12/29/2003 Rev.2.0 2