SS6802

SS6802 SSC | Alldatasheet

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02/26/2008 Rev.1.00 www.SiliconStandard.com 1 BATTERY PROTECTION IC „ FEATURES z Ultra-Low Quiescent Current at 10µA (VCC=7V, VC=3.5V). z Ultra-Low Power-Down Current at 0.2µA (VCC =3.8V, VC=1.9V). z Wide Supply Range: 2 to 18V. z Precision Overcharge Protection Voltage 4.35V ± 30mV for the SS6802A 4.30V ± 30mV for the SS6802B 4.25V ± 30mV for the SS6802C z Built-in Del ay Circuit s for Overcha rge, Over-discharge and Overcurrent Protection. z Overcharge and Ove rdischarge Del ay T ime can be Extended by External Capacitors. z Built-in Cell-balancing Bleeding Network under Overcharge Condition. „ APPLICATIONS z Protection IC for T wo-Cell Lithium-Ion Battery Pack. „ DESCRIPTION The SS6802 battery protection IC is designed to protect lithium-ion batteries from damage due to overch arging, overdi scharging, and overcurrent f or tw o se ries c ells in po rtable phones and laptop com puters. It can be a p art of t he low- cost cha rge control sy stem wit hin a two-cell lithium-ion battery pack. Safe and full utilization ch arging is en sured by the accurate ±30mV overcha rge de tection. Three dif ferent spe cification valu es fo r overcharge protection volt age a re provided fo r various prote ction re quirements. The very low standby current drain s little cu rrent from the cells while in storage. „ TYPICAL APPLICATION CIRCUIT SS6802 *CTC & CTD are optional for delay time adjustment. **R1 & R2: Refer application informations. 1µF *CTC CEM9926 *CTD VCC TC VC TD GND OC OD CS BATTERY 1 BATTERY 2 CEM9926 1µF 1K M2 VBAT+ VBAT - R1 R2 0.01µF Protection Circuit for Two-Cell Lithium-Ion Battery Pack SS6802 Pb-free; RoHS-compliant

02/26/2008 Rev.1.00 www.SiliconStandard.com 2 „ ORDERING INFORMATION PIN CONFIGURATION TOP VIEW VC VCC OD TD GND CS TC OC 1 SS6802XXXXX PACKING TYPE TR: TAPE & REEL TB: TUBE PACKAGE TYPE S: SOP-8 G: LEAD FREE COMMERCIAL OVERCHARGE PROTECTION VOLTAGE A: 4.35V B: 4.30V C: 4.25V Example: SS6802AGSTR Æ 4.35V version, in SO-8 Lead Free Package & Tape & Reel Packing Type „ ABSOLUTE MAXIMUM RATINGS (Assume no ambient airflow, no heatsink) Absolute Maximum Rating are those value beyond which the life of a device may be impaired. „ TEST CIRCUIT VCC VC SS6802 OC VCC OD CS TD VC GND TC IC VCS CTC VOD ICO ICC CTD SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 3 „ ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS SYMBOL MIN. TYP . MAX. UNIT Supply Current in Normal Mode VCC=7V, VC=3.5V I CC 10 15 µA Supply Current in Power-Down Mode VCC=4.8V, VC=2.4V I PD 0.8 1.2 µA VC Pin Input Current VCC=7V, VC=3.5V I C 400 600 nA AIC1802A 4.32 4.35 4.38 AIC1802B 4.27 4.30 4.33Overcharge Protection Voltage AIC1802C VOCP 4.22 4.25 4.28 V Overcharge Release Voltage VOCR 3.85 4.0 4.15 V Overdischarge Protection Voltage V ODP 2.25 2.4 2.55 V Overdischarge Release Voltage VODR 2.85 3.0 3.15 V Overcurrent Protection Voltage VCC=7V V OIP 135 150 165 mV Overcharge Delay Time (1) VCC=8.6V, VC=4.3V, CTC=0µF TOC1 12 25 38 mS Overcharge Delay Time (2) VCC=8.6V, VC=4.3V, CTC=0.47µF TOC2 0.7 1.1 1.5 S Overdischarge Delay Time (1) VCC=4.8V, VC=2.4V, CTD=0µF TOD1 12 25 38 mS Overdischarge Delay Time (2) VCC=4.8V, VC=2.4V, CTD=0.47µF TOD2 0.7 1.1 1.5 S Overcurrent Delay Time (1) VCC=7V, VC=3.5V, VCS=0.15V TOI1 4 9 14 mS Overcurrent Delay Time (2) VCC=7V, VC=3.5V, VCS=0.36V TOI2 1.0 2.0 3.0 mS OC Pin Source Current VCC=8.6V, VC=4.3V, OC Pin Short to GND ICO 270 400 530 µA OD Pin Output “H” Voltage VDL V CC-0.1 VCC-0.02 V SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 4 „ ELECTRICAL CHARACTERISTICS (Continued) PARAMETER TEST CONDITIONS SYMBOL MIN. TYP . MAX. UNIT OD Pin Output “L” Voltage VDH 0.01 0.1 V Charge Detection Threshold Voltage VCC=4.8V V CH -0.55 -0.4 V Unbalance Discharge Current VCC=8.3V, VC=4V I UD 5.4 7.7 10 mA Note1: Specifications are production tested at TA = 25°C. Specifications over the -40°C to 85°C operating Temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). „ TYPICAL PERFORMANCE CHARACTERISTICS Supply Current (µA) Supply Voltage (V) Fig. 1 Supply Current vs. Supply Voltage 5.5 6.5 7.5 8.5 9.7 9.9 10.1 10.3 10.5 10.7 VC=1/2VCC TA=25°C Power-Down Current (µA) Supply Voltage (V) Fig. 2 Power-down Current vs. Supply Voltage VC=1/2VCC TA=25°C 0.2 0.35 0.5 0.65 0.8 Overcharge Protection Voltage (V) Temperature (°C) Fig. 3 Overcharge Protection Voltage vs. Temperature 0 102 03 04 0 506 07 0-10-20 4.3 4.305 4.31 4.315 4.32 AIC1802B Overcurrent Protection Voltage (mV) Temperature (°C) Fig. 4 Overcurrent Protection Voltage vs. Temperature 0 10 203 04 05 06 0 70-10-20 140 142.5 145 147.5 150 VCC=7V VC=3.5V SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 5 „ TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Supply Current (µA) Temperature (°C) Fig. 5 Su pply Current vs. Temperature 0 10 203 04 05 06 0 70-10-20 8.5 9.5 10.5 11.5 12.5 VCC=7V VC=3.5V Power-Down Current (µA) Temperature (°C) Fig. 6 Power-Down Current vs. Temperature 0 102 0 304 0 50 60 70-10-20 0.5 0.7 0.9 1.1 VCC=4.8V VC=2.4V Temperature (°C) -20 -10 0 10 20 30 405 06 07 0 2.395 2.400 2.405 2.410 2.415 2.420 Fig. 7 Overdischarge Protection Voltage vs. Temperature Overdischarge Protection Voltage Fig. 8 Ov ercharge Release Voltage vs. Temperature Overcharge Release Voltage (V) Temperature (°C) -20 -10 0 10 203 0 40 506 0 704.005 4.010 4.015 4.020 4.025 Temperature (°C) Fig. 9 O verdischarge Release Voltage vs. Temperature -20 -10 0 102 0 30 405 0 607 03.005 3.010 3.015 3.020 3.025Overdischarge Release Voltage (V) SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 6 „ BLOCK DIAGRAM VCC TC TD OC CSOD VC GND VCC 450 450 OVERCURRENT DELAY CIRCUIT OVERCURRENT DETECTOR CHARGE DETECTION OVERDISCHARGE DETECTOR 2 TIMING GENERATION OVERCHARGE DETECTOR 1 OVERCHARGE DELAY CIRCUIT OVERDISCHARGE DETECTOR 1 OVERDISCHARGE DELAY CIRCUIT OVERCHARGE DETECTOR 2 LOGIC CONTROL WAKE- UP POWER- DOWN UNBALANCE DISCHARGE „ PIN DESCRIPTIONS PIN 1: OC - PMOS ope n drai n out put for control of the ch arge control MOSFET M2 . When overcharge occurs, this pin sources current to switch the external NPN Q1 on, and charging is in hibited by turning of f the cha rge control MOSFET M2. PIN 2: OD - Output pin for co ntrol of the discharge co ntrol MOSF ET M1. When overdi scharge o ccurs, this pin go es l ow to turn off the discharge control M OSFET M1 and discharging is inhibited. PIN 3: TD - Overdischarge delay time setting pin. PIN 4: GND - Ground pin. This pin i s to be connected to the negative terminal of the lower battery cell. PIN 5: TC - Overcharge delay time setting pin. PIN 6: VC - To be connected to the po sitive terminal of the lower cell and the neg ative terminal of the upper cell. PIN 7: CS - Input pin for current se nsing. Using the d rain-source volt age of the discha rge co ntrol MOSFET M1 (voltage between CS an d G ND), it se nses discharge current during normal mode and detects whethe r charging cu rrent is prese nt during power down mode. PIN 8: VCC - Power su pply pin. It is to be connected to the positive terminal of the upper cell. SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 7 „ APPLICATION INFORMATION THE OPERATION Overcharge Protection When the volt age of either of the battery cells exceeds V OCP (overch arge prote ction volt age) beyond the overcha rge delay time period, charging is i nhibited by t he turni ng-off of th e charge control MOSFET M2. The o vercharge delay time (T OC) default s to 25mS an d can be extended by adding a capacitor CTC . Inhibition of charging is immediatel y relea sed when the voltage of the overcha rged cell be comes lo wer than VOCR (overcharge rel ease voltage) through discharge. Overdischarge Protection When the volt age of either of the battery cells goes bel ow V ODP (overdi scharge prote ction voltage) bey ond the overdischarge d elay time period, discharging is inhi bited by the turni ng-off of the discharge co ntrol MOSFET M1. The overdischarge delay time (TOD) defaults to 25 mS and can be e xtended by adding a capacitor CTD. Inhibition of discha rging i s immedi ately relea sed when the v oltage of the overdi scharged cell becomes hi gher than V ODR (ov erdischarge release voltage) through charging. Power-Down after Overdischarge When overdischarge occurs, the SS6802 will go into power-down mode, turning off all the timing generation a nd dete ction circuitry to reduce the quiescent cu rrent to 0.8 µA ( VCC=4.8V). In the unusual ca se whe re one battery cell is overdischarged while the other under overcharge condition, the SS6802 will turn of f all th e detection circuits except the overcharge detection circuit for the cell under overcharge condition. Charge Detection after Overdischarge When overch arge occurs, the disch arge control MOSFET M 1 turn s of f and di scharging is inhibited. However , charging is still permitted through the p arasitic di ode of M1. Once the charger i s conne cted to the battery p ack, the SS6802 im mediately tu rns on all t he timing generation a nd dete ction circuitry an d goes into normal mode . Chargi ng is determine d to be in progress if th e voltage between CS and GND i s below –0.4V (charge detection threshold voltage VCH) Overcurrent Protection In norm al mode, the SS6802 co ntinuously monitors the discha rge current by sensing the voltage of CS pin. If the volt age of CS pin exceeds V OIP (overcu rrent prote ction volt age) beyond overcurrent delay time T OI p eriod, the overcurrent protection circuit op erates and discharging i s inhibite d by turning -off of th e discharge control M OSFET M1. Discha rging must b e in hibited fo r at least 256mS af ter overcurrent t akes pla ce to avoid damage to external co ntrol MOSF ETs due to rapidly switching tra nsient betwe en V BAT+ a nd V BAT- terminals. Th e overcurre nt condition returns to the normal mode when th e load is rele ased and the impeda nce between the V BAT+ and VBAT- terminals is 10MΩ or higher. Fo r the sake of protection of the external MOSFETs, the large r the CS pin volt age (which mea ns the larger discharge cu rrent) the sh orter the ov ercurrent delay time. T he relation ship betwee n volt age of SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 8 CS pin and overcu rrent delay time T OI is tabulated as below. VCS (V) TOI (S) 150m 9.0m 200m 5.6m 300m 2.8m 360m 2.0m 1V 540µ 3V 290µ 5V 270µ Unbalanced Discharge after Overcharge When eithe r of the battery cells i s ove rcharged, the SS6802 will autom atically di scharge the overcharged cell at about 7.7mA until the volt age of the overch arged cell i s equal to the volt age of the other cell . If the voltage of the other cell is below V OCR, the internal cell-balance “bleeding” will proceed until the volt age of the ove rcharged cell decreases to VOCR. DESIGN GUIDE Adjustment of Overcharge and Overdischarge Delay Time Both the overcha rge a nd overdi scharge del ay times default to 25mS and can be extende d by adding the external ca pacitors C TC and CTD, respectively. Increasing the capacitance value will increase th e delay time. The relation ship between ca pacitance of the external capacitors and delay time is tabulated as below: CTC (F) TOC (S) 0µ 25m 0.1µ 320m 0.3µ 890m 0.47µ 1.12 0.57µ 1.43 CTD (F) TOD (S) 0µ 25m 0.1µ 320m 0.3µ 820m 0.47µ 1.08 0.57µ 1.39 Selection of External Control MOSFETs Because the overcu rrent protectio n volt age is preset, the threshold cu rrent for ov ercurrent detection is determined by the turn-on resi stance of the discharge co ntrol MOSFET M1. The turn-on re sistance of the external control MOSFETs ca n be dete rmined by the equation: RON=VOIP/IT (I T is the overcu rrent thresh old current). For example, if the o vercurrent threshold cu rrent I T is de signed to b e 5A, the turn-on re sistance of the external control MOSFETs must be 30m Ω. Users should be aware that turn -on resistance of the MOSFET changes with temperature variation due to he at dissipation. It chan ges with the volt age between gate and source as well. (Turn-on resistance of a MOSFET increases a s the voltage between gate and sou rce decrea ses). Once the turn-o n resistance of the external MOSFET changes, the SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 9 overcurrent threshold current will change accordingly. Suppressing the Ripple and Disturbanc e from Charger To supp ress the ripple and dist urbance fro m charger, connecting C1 to cell 1 and C2 to cell 2 is necessary. Controlling the Charge Control MOSFET R3, R4, R5 and NP N tra nsistor Q1 a re used to switch t he cha rge cont rol MOS FET M2. I f overcharge does not occur, no curre nt flows out from O C pi n and Q1 a re turne d of f, then M 2 is turned on. When ove rcharge o ccurs, cu rrent flows out from OC pin and Q1 is turned on, which turns off M2 in turn. High resistance for R3, R4, and R5 is recommended for reducing loading of the batteries. Latch-Up Protection at CS Pin R6 is used for latch-up protection when charger is connected under overdischarge condition, and also for ove rstress prote ction whe n charger i s connected i n reve rse. The charge detectio n function after overdischa rge is possibl y disabled by large r value of R6. Re sistance o f 1K Ω is recommended. Selection of R1 and R 2 R1 and R2 a re used to avoid large current flow through the battery pack under the situation of IC damage o r pin sh ort. On the o ther ha nd, resistance of R1 and R2 will af fect o vercharge release volt age an d bl eeding funct ion. The relationship amon g V release1,Vrelease2, R1, and R2 is shown as following equations: Vrelease1=VOCR+IUD*R1 Vrelease2=VOCR+IUD*R2 where Vrelease1 is Battery 1, real overcharge release voltage Vrelease2 is Battery 2, real overcharge release voltage Therefore, resist ance of R1 and R2 sho uld not higher than 30Ω. Otherwise, overcharge release voltage wou ld be high er than ov ercharge protection voltage and the charging current may oscillate. In addition, if overch arge protectio n function occurs, SS6802 will discharge the overcharged cell and will stop blee ding function even if the voltage is not equal to the other. The recommended resi stance of R1 and R2 is from 20 to 30Ω. Effect of C3 C3 has to be applied to th e circuit. Because C3 will keep SS6802 to be charg ed af ter overdischarge occurred. In addition, whe n the differential vo ltage b etween ch arger and battery pack is hi gher than 2. 1V and overcha rge protection function work, C3 will avoid battery pack from b eing charged even if the battery voltage lower than 4V (To avoid battery pack from being cha rged und er charger malfunction situation). The battery pack can be charged again till remove it from charger. SS6802

02/26/2008 Rev.1.00 www.SiliconStandard.com 10 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. h θ L D e H E C B 0.500.25 0.40 1.27

1.27 BSC

4.80 5.80 3.80 0.33 0.19 0.10 5.00 6.20 4.00 0.51 0.25 0.25 S Y M B O L A SOP-8 MILLIMETERS 1.35 MIN. 1.75 MAX. A θ L VIEW B 0.25 SEATING PLANE BASE METAL GAUGE PLANE WITH PLATING B C D e AA H E h X 45° SEE VIEW B „ PHYSICAL DIMENSIONS z SOP-8 (unit: mm) Note: 1.Refer to JEDEC MS-012AA. 2.Dimension “D” does not include mold flash, protrusions or gate burrs. Mold fl ash, protrusion or gate burrs shal l not exceed 6 mil per side. 3.Dimension “E” does not include inter-lead flash or protrusi ons. Inter-lead flash or protrusion shall not exceed 10 mil per side. 4.Controlling dimension is millimeter, converted i nch dimensions are not necessarily exact.