SS6383A SSC | Alldatasheet
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www.SiliconStandard.com 1 of 7 SS6383A(G) 11/07/2004 Rev.2.01 2A DDR Termination Regulator FEATURES DESCRIPTION Source and sink current capability of 2A Low output voltage offset, ±20mV High accuracy output voltage at full-load VOUT adjustable by external resistors Low external component count Current limit protection Thermal protection SO-8 and TO-252-5 packages
APPLICATIONS
DDR Termination Voltage Supply - supports The SS6383A linear regulator is designed to provide 2A source and sink current while regulating an output voltage to within 20mV. The SS6383A converts voltage supplies ranging from 1.6V to 6V into an output voltage that is set by two external voltage-divider resistors. It provides an excellent voltage source for active termination schemes for high-speed transmission lines such as those seen in high- speed memory buses. The built-in current-limiting in source and sink mode, together with thermal shutdown, provides maximum protection to the SS6383A against fault conditions. TYPICAL APPLICATION CIRCUIT DDR1 (1.25VTT), DDR2 (0.9VTT), and meets JEDEC SSTL-2 and SSTL-3 term. specifications This device is available with Pb-free lead finish (second-level interconnect) as SS6383AGxx + COUT 220µF + CIN 470µF CCNTL 47µF 100K 100K VIN=2.5V VIN GND VCNTL VOUT VREF SS6383ACE5 SSM7002EN EN C1 VOUT VCNTL=3.3V 100pF
www.SiliconStandard.com 2 of 7 SS6383A(G) 11/07/2004 Rev.2.01 ORDERING INFORMATION PIN CONFIGURATION Example: SS6383AGE5TR Æ in TO-252-5 package, Pb-free lead finish, shipped on tape and reel SS6383AXXX XX Packing TR: Tape and reel Package type CE5: TO-252-5, commercial GE5: TO-252-5, Pb-free, commercial TO-252-5 TOP VIEW 1: VIN 2: GND 3. VCNTL 4. VREF 5: VOUT 1 2 3 4 5 SO-8 TOP VIEW VCNTL VCNTL VCNTL VCNTL VREF GND VOUT VIN 1 ABSOLUTE MAXIMUM RATINGS Supply Voltage -0.4V to 7V Operating Temperature Range -40°C~85°C Storage Temperature Range -65°C ~150°C Lead Temperature (Solder, 10sec) 260°C Thermal Resistance θJC TO-252 12.5°C /W SO-8 40°C /W Thermal Resistance θJA TO-252 (Assumes no ambient airflow, no heatsink) 100°C /W SO-8 160°C /W CS: SO-8, commercial GS: SO-8, Pb-free, commercial Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
www.SiliconStandard.com 3 of 7 SS6383A(G) 11/07/2004 Rev.2.01 TEST CIRCUIT VIN 1 GND2 VCNTL3 VOUT VREF SS6383ACE5 2.5V 3.3V 1.25V + COUT 10µF VOUT
ELECTRICAL CHARACTERISTICS
(VCNTL=3.3V, VIN=2.5V, VREF=0.5VIN, COUT=10µF, TA=25°C, unless otherwise specified) PARAMETER TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT VIN 1.6 2.5/1.8 Input Voltage (DDR1/2) Keep VCNTL≥VIN during power on and off sequences VCNTL 3.0 3.3 6 V Output Voltage IOUT = 0mA VOUT VREF V Output Voltage Offset IOUT = 0mA VOS -20 20 mV IOUT =0.1mA ~ +2A 10 20 Load Regulation (DDR1/2) IOUT =0.1mA ~ -2A ∆VLOR 10 20 mV Quiescent Current VREF<0.2V, VOUT = OFF IQ 8 30 µA Operating Current of VCNTL No load ICNTL 3 10 mA VREF Bias Current VREF=1.25V 0 1 µA Current Limit IIL 2.2 3 4.5 A THERMAL PROTECTION Thermal Shutdown Temperature 3.3V≤VCNTL≤5V TSD 125 150 °C Thermal Shutdown Hysteresis Guaranteed by design 30 °C SHUTDOWN SPECIFICATIONS Output ON (VREF=0VÆ1.25V) 0.8 Shutdown Threshold Output OFF (VREF=1.25VÆ0V) 0.2 V Note 2: VOS is the voltage measurement, which is defined as the difference between VOUT and VREF. Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low ON time. Note 4: Current limit is measured by pulsing a short time. Note 5: To operate the system safely; VCNTL must be always greater than VIN. Note 6: Specification s are guaranteed by Statistical Quality Controls (S QC), and not production tested, within the operating temperature range of -40°C to 85°C.
www.SiliconStandard.com 4 of 7 SS6383A(G) 11/07/2004 Rev.2.01 TYPICAL PERFORMANCE CHARACTERISTICS Threshold Voltage (V) Temperature (°C) Fig. 1 Turn-On Threshold vs. Temp. -20 0 20 40 60 80 100 120 0.32 0.36 0.40 0.44 0.48 0.52 VCNTL=3.3V VIN=2.5V 40 20 0 20 40 60 80 100 120 0.32 0.36 0.40 0.44 0.48 0.52 VCNTL=5V VIN=2.5V Threshold Voltage (V) Temperature (°C) Fig. 2 Turn On Threshold vs. Temp. Output Voltage Offset (mV) Temperature (°C) Fig. 3 Output Voltage Offset vs. Temp. -40 -20 0 20 40 60 80 100 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCNTL=3.3V VIN=2.5V VREF=1.25V No Load -40 -20 0 20 40 60 80 100 1200 Sourcing Current (A) Temperature (°C) Fig. 4 Current-Limit (Sourcing) vs. Temp. VCNTL=3.3V, VIN=2.5V VOUT=1.25V Sinking Current (A) Temperature (°C) Fig. 5 Current Limit (Sinking) vs. Temp. -40 -20 0 20 40 60 80 100 120 VCNTL=3.3V, VIN=2.5V VOUT=1.25V
www.SiliconStandard.com 5 of 7 SS6383A(G) 11/07/2004 Rev.2.01 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) BLOCK DIAGRAM VOUT - VOUT GND VIN Control VCNTL Shutdown Shutdown ThermalCurrent Limit VREF VCNTL=3.3V, VIN=2.5V VREF=1.25V Fig. 6 Output Short-Circuit (Sinking) VCNTL=3.3V VIN=2.5V VREF=1.25V Fig.7 Output Short-Circuit (Sourcing) VCNTL=3.3V, VIN=2.5V VREF=1.25V Fig.8 Transient Response at 1.25V TT/2A VCNTL=3.3V Fig. 9 Transient Response at 0.9V TT/2A VIN=1.8V VREF=0.9V
www.SiliconStandard.com 6 of 7 SS6383A(G) 11/07/2004 Rev.2.01 PIN DESCRIPTIONS (TO-252-5) PIN 1: VIN - Input su pply pin. It provides main power to create th e external reference volta ge by divider re sistors for regul ating VREF and VOUT. PIN 2: GND - Ground pin. PIN 3: VCNTL - Input sup ply pin. It is use d to supply all the internal control circuitry. PIN 4: VREF - Reference v oltage in put. Pull this pin low to shutdown device. PIN 5: VOUT - Output pin.
APPLICATION INFORMATION
As the SS6383A is in SO-8 and TO-252-5 packages, it is unable to dissipate heat easily when it operates at high current. To avoid exceeding the maximum junction temperature, a suitable copper area must be used. The larg e co pper area shown at V CNTL pins is able to relieve the thermal dissipation. Using the via to direct heat into the large copper area shown on the bottom layer also helps significantly. All capa citors shoul d be placed a s close a s possible to the relevant pins. Figure 10. Top layer Figure 11. Bottom layer Figure 12. Placement
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. www.SiliconStandard.com 7 of 7 SS6383A(G) 11/07/2004 Rev.2.01 SO-8 SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27(TYP) H 5.80 6.20 L 0.40 1.27 D H e A B C E L TO-252-5 SYMBOL MIN MAX A 2.19 2.38 A1 0 0.13 b3 5.21 5.46 c2 0.46 0.58 D 5.33 5.59 E 6.35 6.73 e 1.27 BSC H 9.40 10.41 L 1.4 1.78 L1 2.67 REF L2 0.51 BSC L3 1.52 2.03 θ 0° 8° A e D E A H L A PHYSICAL DIMENSIONS