SS1102C ETC1 | Alldatasheet
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Integrated MCU with Spread-Spectrum Transceiver (SST) External Specification PRELIMINARY (V 1.8) /G09/G0A /G0D/G0A/G0A/G0A/G09/G0A/G0A/G09/G0A/G0A /G09/G0A /G0A /G0D &&& ’/G0A/G0A() ’/G0A
PRELIMINARY V1.8 i Table of Contents
ii PRELIMINARY V1.8
PRELIMINARY V1.8 iii
iv PRELIMINARY V1.8
Description
PRELIMINARY V1.8 1 1. Description The SS1102C is a CMOS integrated solution for direct sequence spread spectrum digital wireless data communication applications. The chip performs all CPU, baseband modem and peripheral control functions. A baseband spread spectrum modem, a microcontroller, and I/O interfaces are integrated into a single chip. The RF interface is suitable for most RF module designs. A low speed link data path allows for supervisory and setup functions, while the communication channel is used for full duplex data transmission. The chip can be delivered in the 52-pin or 100-pin package. The 100-pin version has an interface to the external EPROM. The 52-pin version is a mask version of the chip. 2. Features
- Direct sequence spread spectrum transceiver
- Support for MSK
- RF interface signals
- Full and half duplex data transmission modes
- 125Kbps maximum data rate in half duplex mode
- 64Kbps maximum data rate in full duplex mode
- Low speed signalling full duplex data path
- 8051 compatible 8-bit CPU
- 16K bytes on-chip ROM
- 512 x 8 RAM
- Two capture timers
- WatchDog timer
- Time Base timer
- Programmable Serial Peripheral Interface (SPI)
- Low battery detect
- Programmable I/O lines
- Active, Low Power and Power Down Operation modes
- Two on-chip oscillator circuits - up to 24MHz Master clock and low speed 32KHz clock for the Low Power mode
- Power-on Reset
- Supply V oltage: 2.7V-5.5V
- 52-pin package
- Operating temperature: -20C to 85C
Figure 1. SS1102C Block Diagram
PRELIMINARY V1.8 3 4. Pin Description Port Pin # Pin Name I/O Type Functions VDD 1 Vdd Digital Supply Voltage NRESET 2 NRESET Reset TST 3 TST Test pin BXFOUT 4 BXFOUT Buffered High Frequency Output XFOUT 5 XFOUT Oscillator High frequency crystal output XFIN 6 XFIN Oscillator High frequency crystal input XSOUT 7 XSOUT Oscillator Slow frequency crystal output XSIN 8 XSIN Oscillator Slow frequency crystal input P4.0 9 RFPWR I/O 3 RF power switch output/ I/O P4.1 10 PLLSW I/O 3 Phase-lock loop switch output/ I/O P4.2 11 LOCK I/O 3 Lock Indicator P4.3 12 I/O I/O 3 Latched bi-directional I/O P4.4 13 I/O I/O 3 Latched bi-directional I/O P4.5 14 I/O I/O 3 Latched bi-directional I/O P4.6 15 I/O I/O 3 Latched bi-directional I/O P4.7 16 I/O I/O 3 Latched bi-directional I/O P3.0 17 CPTRU2 I/O 3 Capture Timer 2 P3.1 18 CPTRU1 I/O 3 Capture Timer 1 VSS 19 Vss Digital Ground P3.2 20 CPTRD1 I/O 3 Capture Timer 1/Down Counter P3.3 21 TXEN I/O 3 Transmitter enable output/ I/O P3.4 22 MODOUT I/O 3 Modulated output (chips output) P3.5 23 DI I/O 2 Digital (DI) / Analog (DI1) Data Input P3.6 24 IRQ1 I/O 3 External Interrupt 0 P3.7 25 IRQ2 I/O 3 External Interrupt 1 DIREF 26 DIREF I/O 3 Analog Data Input Comparator External reference voltage
TABLE 1. Pin Description
Figure 2. SS1102C Pinout
- High performance CMOS 8-bit CPU with the industry standard 80C51 instruction set.
- Extensive boolean processing (single bit logic) capabilities
- Arithmetic: 8 bit including multiply and divide
- Jumps, 8/16 bit address, conditional and unconditional
- Logical separation of program and data memory
- Six addressing modes
- Maximum operating speed 24MHz. 6. Memory organization 6.1. Data memory The SS1102C has separate address space for Program Memory and Data Memory. The SS1102C has 512 bytes of onchip data space, 256 bytes must be accessed by MOVX. P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.7/IRQ2 P3.6/IRQ1 P3.5/DI P3.4/MODOUT P3.3/TXEN P3.2/CPTRD1 P3.1/CPTRU1 P3.0/CPTRU2 NRESET XSIN XSOUT XFIN XFOUT VDD VSS A VDD AV S S BXFOUT DIREF P1.0 P1.1 P1.2 P1.3 P4.0/RFPWR P4.1/PLLSW P4.2/LOCK P4.3 TST P1.4/LBD P1.5/SPIO P1.6/SPIIN P1.7/SPICLK 1314 15 25 2627 4041 5152 19 2018 7 33 444546 Index Corner 52-PIN PQFP P4.4 P4.5 P4.6 P4.7 SS1102C
- Special function registers
block descriptions and the architectural overview section. TABLE 2. Special Function Registers Description
0 P0 P1 P2 P3 P4 PSW ACC B
1 SP WDCR TBCR SSTMCR CT1CR CT2CR SPI1CR
2 DPL WDCNT TBCNT CT1CNTL CT2CNTL SPI1DAT
3 DPH TBDAT CT1CNTH CT2CNTH SPI1SR
4 LBDCR CT1DATL CT2DATL
5 CMPRCR CT1DATH CT2DATH
6 SREL XICR0 CT1SR
Special function registers 8 PRELIMINARY V1.8 The SFR register definitions are described within each peripheral block description and the general CPU registers SP, DPTR, PSW, ACC, B, and MSIZ are described below. The underlined names are the registers for the CPU and the dashed lines are for registers used in standard 8051 devices but not used by the SS1102C microcontroller. 7.1. Stack Pointer (SP) The SP register contains the stack pointer. The stack pointer is used to load the program counter into memory during LCALL and ACALL instructions, and is used to retrieve the program counter from memory in RET and RETI instructions. The stack may also be saved or loaded using PUSH and POP instructions, which also increment and decrement the stack pointer. The stack pointer points to the top location of the stack. On reset the stack pointer is set to 07 hex. 7.2. Data Pointer (DPTR) The Data Pointer (DPTR) is 16 bits in size, and consists of two registers, the Data Pointer High byte (DPH), and the Data Pointer Low byte (DPL). Two 16 bit operations are possible on this register, they are load immediate and increment. This register is used for 16 bit address external memory accesses, for offset code byte fetches, and for offset program jumps. On reset the value of this register is 0000 hex. 7.3. Pro gram Status Word (PSW) This register contains status information resulting from CPU and ALU operation. The bit definitions are given below:
- PSW.7 CY . ALU carry flag.
- PSW.6 AC. ALU auxiliary carry flag.
- PSW.5 F0. General purpose user definable flag.
- PSW.4 RS1. Register bank select bit 1.
- PSW.3 RS0. Register bank select bit 0.
- PSW.2 OV . ALU overflow flag.
- PSW.1 F1. User definable flag.
- PSW.0 P. Parity flag. Set each instruction cycle to indicate odd/even parity in the accumulator. On reset this register returns 00 hex. The register bank select bits operate as follows
TABLE 3. Register bank select bits On reset this register returns 00 hex. it may be used as a scratch pad register. On reset this register returns 00 hex. On reset this register returns 3F hex or 16K of internal program memory.
- 16K byte internal ROM
- A total of 512 bytes of on-chip data RAM:
- 256 bytes standard RAM
- 256 bytes of additional on-chip data memory accessible by the MOVX com- mand (XRAM). 7.7. Interrupts - Two external interrupt input pins (IRQ1, IRQ2) RS1 RS0 Register Bank Select 0 0 RB0. Registers from 00 - 07 hex. 0 1 RB1. Registers from 08 - 0F hex. 1 0 RB2. Registers from 10 - 17 hex. 1 1 RB3. Registers from 18 - 1F hex.
10 PRELIMINARY V1.8 - Eleven internal interrupt sources. The following peripheral blocks can generate interrupt request: Watchdog Timer, Time Base Timer, Capture Timer 1, Capture Timer 2, SPI, TXFIFO, RXFIFO, Signaling Word, Signal/Noise Ratio, and Lock, LBD 8. Time Base Timer 8.1. Overview The Time Base Timer (TB-Timer) is an 8-bit auto-reload timer. The TB-Timer is composed of a input frequency select MUX, an 8-bit up-counter(TBCNT), a Comparator, an 8-bit data register(TBDAT), and a control register(TBCR). The TB-Timer has the 8 counting clocks that can be selected by TBFS[5:3]. Four of the clocks come from the System Clock block, i.e. F 1SEC , F1MIN , F1HOUR , and F125mS . If the slow oscillator is stopped, these four clocks will stop too. These four clocks will be very useful to generate a real time interval and to minimize the number of CPU wake- ups. The period of the F sys/12 clock is one machine cycle or one fastest instruction cycle. This clock will run during any power-saving mode except the StopAll mode. During the FastAll or FastPeri mode, the F sys/12 clock is equal to Ffast/12. During the SlowAll or SlowPeri mode, the Fsys/12 clock is equal to Fslow/12. The Ffast/24, Ffast/27, and Ffast/210 can be used during the FastAll or FastPeri mode only. After the TBEN bit is set to high, the TBCNT will start to count the negative edge of an input clock. When the TBEN bit is low, the Match signal is never generated even though the contents of the TBDAT and TBCNT are the same. The TBCNT is the 8-bit up-counter that can be cleared by the TBCLR bit or the Match signal. The TBCNT is a modulo-N counter (from 0 to N-1), N is the content of the TBDAT. The match signal will always set the TBINT bit to high. The TBINT bit can be cleared by the TB-Timer Interrupt Acknowledge or by software.
Figure 5. Time Base Timer
TABLE 4. Definition of TBCR TABLE 5. Description of TBCR A selected input clock is halted. The TBCNT keeps the counter value. A selected input clock runs. The TBCNT counts up the negative edge of the selected clock. 00H. Writing low will not affect anything. When read, a low(0) will be always read. Normal hour clock signal is used for F1hour. A test mode using XSout (32.768KHz) for F1hour. Note: The bit can only be set either under FastAll or FastPeri modes. User should write a 0 to this bit. A test mode using the XSout (32.768KHz) for F1min . Note: The bit can only be set either under FastAll or FastPeri modes. User should write a 0 to this bit.
TABLE 6. Definition of TBCNT TABLE 7. Description of TBCNT A Modulo-N (00 to N-1) up-counter. N is the content of TBDAT.
TABLE 8. Definition of TBDAT TABLE 9. Description of TBDAT be minimized because the Slow Clock prescaler can be cleared by software.
CT2DATL), an Edge Detector for Capture, and a control register(CT1CR, CT2CR). selected by the CT2MD[1:0] bits in the CT2CR. Down-Counter. In Capture mode, the C-Timer can be used as a Capture Timer. Figure 6. Capture Timer in Auto-Reload Mode
16 PRELIMINARY V1.8 9.2. Auto-Reload Mode If the CT1MD[2:0] bits in the CT1CR are 000, the C-Timer1 will operate in the Auto- Reload Mode. If the CT2MD[1:0] bits in the CT2CR are 00, the C-Timer2 will operate in the Auto- Reload Mode. A C-Timer has 8 counting clocks that can be selected by CT1FS[2:0] (or CT2FS[2:0]). The period of the Fsys/12 clock is one machine cycle or one fastest instruction cycle. This clock will be run during any power-saving mode except the StopAll mode. During the FastAll or FastPeri mode, the F sys/12 clock is equal to Ffast/12. During the SlowAll or SlowPeri mode, the Fsys/12 clock is equal to Fslow/12. The Ffast/24, Ffast/25, Ffast/27, Ffast/210, Ffast/214, and Ffast/218 can be used during the FastAll or FastPeri mode only. Two external interrupt pins(CPTRU1 and CPTRU2) are connected to the C-Timer1 and 2. Thus, the timers can be used as the Event Counters. To use this timer as an Event Counter, the CPTRU1 (or CPTRU2) should be assigned as an input port by the port control register. After the CT1EN(or CT2EN) bit is set to high, the CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) will start to count up the negative edge of a selected input clock. When the CT1EN (or CT2EN) bit is low, the Match signal is never generated even though the contents of the CT1DATH & CT1DATL (or CT2DATH & CT2DA TL) and CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) are the same. In Auto- Reload Mode, CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) act as a 16-bit up-counter that can be cleared by the CT1CNTLR (or CT2CNTLR) bit or by the Match signal. The CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) is a modulo-N counter (from 0 to N-1), N is the content of the CT1DATH & CT1DATL (or CT2DATH & CT2DATL). The match signal will always set the CT1INT (or CT2INT) bit to high. The CT1INT (or CT2INT) bit can be cleared by a C-Timer Interrupt Acknowledge or software. 9.3. Up Down-Count Mode If the CT1MD[2:0] bits in the CT1CR are 1XX (X means don’t care), the C-Timer1 will operate in the Up Down-Count Mode. After the CT1EN bit is set to high, the 16-bit up down-counter(CT1CNTH & CT1CNTL) will start to count. It counts up on the negative edge of CPTRU1 and counts down on the negative edge of CPTRD1. To use CPTRU1, CT1FS[5:3] must set to 111. In Up Down-Count Mode, CT1CNTH & CT1CNTL act as a 16-bit up down-counter that can be cleared by the CT1CNTLR bit. The CT1CNTH & CT1CNTL is a modulo- 65536 counter (from 0 to 65535). The overflow signal will set the CT1OV bit in CT1SR to high and the underflow signal will set the CT1UN bit in CT1SR to high. Both the overflow and underflow signal will always set the CT1INT bit in INT2 register and CT1OVUN bit in CT1SR to high. The CT1INT bit can be cleared by a C-Timer Interrupt Acknowledge or software, and CT1OV , CT1UN and CT1OVUN can be cleared by reading the CT1SR. Another Capture-Timer1 interrupt will not be generated if CT1OVUN is still not being cleared.
Figure 7. Capture Timer 1 in Up-Down Count Mode CT1OVUN is still not being cleared.
width or low width) can be measured. Note: While in Capture mode, the CTDATH and CTDA TL are still writable by S/W. Figure 8. Capture Timer in Capture Mode
TABLE 10. Definition of CT1CR/CT2CR
TABLE 11. The Description of CT1CR/CT2CR
7 C-Timer ENable bit
6 CTn counter CLeaR bit
read, a low(0) will be always read. the pin should be assigned to input mode by a port control register. CT2MD[2] of C-Timer2 is unused.
TABLE 12. Definition of CT1SR TABLE 13. Description of CT1SR [Bit Status: 0 (Initial Value)]: No Overflow and no Underflow. [Bit Status: 1]: Overflow or Underflow. [Bit Status: 0 (Initial Value)]: No Overflow. [Bit Status: 0 (Initial Value)]: No Underflow.
TABLE 14. Definition of CTnCNTH (n = 1 or 2)
TABLE 15. Definition of CTnCNTL (n = 1 or 2) TABLE 16. The Description of CTnCNTH & CTnCNTL any C-Timer will generate continuous Match signals with a fixed period. flow will generate continuous interrupt request with a fixed period. and underflow will generate continuous interrupt request.
TABLE 17. Definition of CTnDATH (n = 1 or 2)
TABLE 18. Definition of CTnDATL (n = 1 or 2) TABLE 19. The Description of CTnDATH & CTnDATL CTnCNTL when a selected edge of CPTRU1 or CPTRU2 is happened. The CTnDATH & CTnDATL is not used in Up Down-Count Mode.
enabling the WatchDog Interrupt, the WD-Timer can be used as a basic interval timer. Only Fsys/12 is supported when under SlowAll or SlowPeri modes. Figure 9. Watch Dog Timer
TABLE 20. Definition of WDCR In this mode, the WD-Timer turns off. Register keeps previous value without down-counting. In this mode, the WD-Timer turns on. Register operates as a down-counter. Do NOT write these values on these two bits. two redundant status is to prevent unexpected WD-Timer stop by device upset. value, the WD-Timer will be continuously running without stop.
TABLE 21. The Description of WDCR bit-7 to 4 TABLE 22. The Description of WDCR bit-3 to 0 ROM address 0000H. All registers will be initialized. Do NOT write these values on these two bits. WD-Timer can generate a Reset signal. The chip was initialized by the external pin reset signal. The chip was initialized by the WD-Timer underflow reset signal.
2 Reserved bit
TABLE 23. Definition of WDCNT
- STEP-1: First of all, a timer interval period should be decided. Then, a WDCNT value can be decided. Any instruction, whose destination is the WDCNT, can be used to write a value to the WDCNT. If the content of the WDCNT is FFH, that is the initial value after any Reset, and FFH is the needed value, you do not have to perform a write instruction to the WDCNT. The interval period is as follows. WD-Timer interval time = (1 / F selected-clock) X (WDCNT + 1) - Deviation period 0 <=Deviation period < (1 / Fselected-clock)
- STEP-2: You should perform a write instruction to the WDCR with proper content. To turn the WD-Timer on, you must set the WDON[1:0] to 10. While the WD-Timer is running, if you change the content of the WDON[1:0] to 01 the WDCNT will retain its last count value. If the WD-Timer Reset is needed, the WDREN[1:0] should be set to 10. If the WDREN[1:0] is 01, the WD-Timer can be used as a basic interval timer. You can choose a counting clock among four clock sources.
- STEP-3: While the WD-Timer is running, software must repeatedly re-initialize the WDCNT before the WD Reset is generated. This write operation can be performed without halting the WD-Timer.
- STEP-Underflow: BIT 7 6 5 4 3 2 1 0 NAME WDCNT[7:0] Definition WatchDog Timer Register (8-bit down-counter) Reset Value FFH Read/ Write by Software R/W Write by Hardware Written with a new count value.
SPI (Serial Peripheral Interface) 30 PRELIMINARY V1.8 If the WD Reset is enabled and a WD underflow happens, the MCU goes into Reset state and all registers are initialized again. The Program Counter will point to the address 0000H. The software initialization routine can check the WDRST bit to distinguish the reset source. In any case, the WDINT bit is set to high when the underflow happens. If the WD- Timer interrupt is enabled by the Interrupt Control Block, the interrupt service routine for the WD-Timer will be served. At this time the WDINT bit will be cleared by hardware. Note: Writing “FFh” to the down counter register while it is in the “00h” state, might cause the “Underflow”. Writing anything other than “FFh” will not cause the “Underflow”. 11. SPI (Serial Peripheral Interface) 11.1. Overview The SS1102C includes an 8-bit SPI which allows to communicate with peripheral or microcontroller devices equipped with a compatible SPI function. The SPI supports full-duplex communications by allowing 8-bit of data to be synchronously transmitted and received. An SPI system should contain one master device and several slave devices. The SS1102C can only be configured as an SPI master. 11.2. SPI Pin and Timing Description Basically, three pins (MI, MO, SCK) are used to accomplish the communication:
- Master In (MI): MI is configured as a data input. The most significant data bit is receive first.
- Master Out (MO): MO is configured as a data output. The most significant data bit is sent first.
- Serial Clock (SCK): The master clock used to synchronize data transfer through MI and MO. Since SCK is generated by the master device, this pin is configured as an output. 11.3. SPI Timing Description As shown in Fig. 1, four possible timing relationships may be chosen by using control bits CPOL (clock polarity) and CPHA (clock phase) in the serial peripheral control register(SPI1CR). Both master and slave device must operate with the same timing. The clock frequency is selected by using control bits SPR0 and SPR1 in the SPI1CR of the master device. The slave device has no control of the clock frequency.
Figure 10. SPI Timing Diagram allows the next data byte to start reception before reading the data that was just received. and data is shifted as soon as data is written to the shift register.
Figure 11. SPI Block Diagram
Figure 12. SPI Master-Slave Interconnection TABLE 24. Definition of SPICR
TABLE 25. Description of SPICR TABLE 26. SPI Status Register (SPI1SR) Select in slave device) may be thought of as simple enable control.
TABLE 27. Description of SPI Status Register (SPI1SR) TABLE 28. Definition of SPIDAT 1: Collision: Attempt to write to SPI1DAT while data transfer is still in progress. finishes when SS (Slave Select in slave device) goes high. Select in slave device) is low. The transfer finishes when SPIF is set. WCOL can be cleared by reading SPI1SR followed by a read of the SPI1DAT.
SPI (Serial Peripheral Interface) 36 PRELIMINARY V1.8 To send the data SP1CR should be set first, then the data should be written into SPI1DAT. In the interrupt subroutine SPIINT should be cleared by the application software. Even though if the SPIINT is not enabled, the flag should be cleared by the software to support another data transmission or receiving phases.
Direct Sequence Spread Spectrum Baseband Modem (SSTM) PRELIMINARY V1.8 37 12. Direct Sequence Spread Spectrum Baseband Modem (SSTM) The SSTM is a low-power, multi-purpose communication module designed to support spread spectrum data communications. The SSTM contains all the baseband function required for an FCC Part 15 compliant device. The SSTM supports both full-duplex and half-duplex operations in synchronous mode. In the half-duplex, no assumption about higher level protocols is made. Instead, the SSTM is designed to be flexible and can be configured for a variety of uses. In full-duplex operation communication is achieved by using a time-division duplex (TDD) protocol and burst structure. The SSTM supports full-duplex data rates up to 64Kbps and half-duplex data rates up to 166 Kbps. The SSTM is made up of five functional modules. These include the receiver, the transmitter, the time-division duplex (TDD) controller, the transmit and receive FIFOs, and the master clock generator. 12.1. Receiver The receiver module performs all the digital signal processing required by the spread spectrum receiver, including de-correlation and demodulation. The receiver samples the incoming baseband signal at two samples per PN chip. The samples are correlated with four possible PN sequences in 64-bit parallel correlators. The de-correlated signal is demodulated via a digital phase locked loop. To reduce power consumption, the receiver is powered down while the SSTM is transmitting and consumes peak power only during the brief period of initial acquisition. After acquisition, the receiver goes into tracking/detection mode, where the power consumption of the receiver module is reduced by two orders of magnitude. 12.2. Transmitter The transmit module generates the spread spectrum binary sequence for output to the RF modulator. The transmitter logic encodes two consecutive bits of data into one of four possible 32- bit PN sequences. The transmitted PN sequence is further randomized by modulus-2 addition with a fixed 2047-bit long PN sequence. This operation smooths the output spectrum of the transmitted signal and eliminates discrete spectral components. During TDD operation, the transmitter is powered off during the portion of the cycle when the SSTM is in receive mode in order to save power. The transmitter output is at high- impedance state during a receiving period.
Direct Sequence Spread Spectrum Baseband Modem (SSTM) 38 PRELIMINARY V1.8 12.3. TDD Controller The time-division duplex (TDD) controller implements the “ping-pong” protocol that allows a full-duplex link to be emulated by a half-duplex radio. The TDD controller also generates the appropriate clock and control signals to other modules of the SSTM. In full-duplex mode, the TDD controller multiplexes and de-multiplexes the overhead bits with the data bit-stream. The TDD controller also uses a digital phase locked loop to maintain an equal read and write rate to the FIFOs as to avoid FIFO overflow or underflow. In addition, the TDD controller contains logic to generate the proper handshaking signals. 12.4. FIFOs The transmit and receive FIFOs are used to buffer the transmit and receive data. The SSTM includes a 30-byte transmit FIFO and a 30-byte receive FIFO to buffer the input and output data. The control signals for the FIFOs are generated by the TDD controller. The FIFOs provide the internal interrupt signals for the microprocessor. 12.5. Master Clock Generator The master clock generator generates the various clock signals required by the modules described above. It can be disabled in power saving mode. 12.6. Full-Duplex Operation Although the SSTM actually only uses a half-duplex channel for communication with the remote device, full-duplex operation is provided by using a time-division duplex (TDD) protocol. The TDD protocol basically configures the SSTM alternatively as a transmitter and as a receiver. When two devices are communicating with each other, one is programmed to be the master, while the other is programmed to be the slave. The TDD protocol ensures that while the master is transmitting, the slave is receiving and vice versa in a timely fashion. The end result is that as far as the user is concerned, the communication link appears to be full-duplex. In order to achieve this, it is necessary for the SSTM to transmit at a higher rate than the actual user data rate. Ideally, for TDD operation, with 100% efficiency and 0% overhead, the SSTM must transmit the data at twice the user data rate since the SSTM has only half the time to transmit the user data (during the other half time period, the SSTM is receiving from the remote station). Overhead such as preamble, unique word (UW), as well as other signaling information bits result in the SSTM transmitting at 2.6 times the effective user data rate. The size of the FIFOs on the SSTM is designed to provide sufficient buffer during both transmit and receive operations so that underflow or overflow of the FIFOs does not occur. When communication between two devices first commences, the microprocessors must program one of the devices as the Master and the other device as the Slave. The master device transmits periodic bursts as soon as the reset signal is released. The burst timing of the Master is derived from its internal master clock oscillator and can be computed from (EQ 1) below:
Direct Sequence Spread Spectrum Baseband Modem (SSTM) PRELIMINARY V1.8 39 (EQ 1) In (EQ 1), fburst is the burst rate and fmosc is the master oscillator frequency. As the transmitter uses a quadrature modulation scheme, the chip rate is 16 times the burst rate or (EQ 2) where fchip is the chip rate and fmosc is the master oscillator frequency. Effectively, the spread spectrum transceiver operates at 16 chips/bit or 32 bits/symbol where each symbol is composed of 2 bits. The total number of bits per burst is fixed and equal for both the Master and the Slave. The Slave derives its burst timing from the Master by detecting the UW pulse transmitted by the Master. 12.7. TDD Protocol Initially, the two communicating devices need to establish “sync”. The TDD protocol achieves this by using a special handshaking protocol. The Master first transmits an “acquisition burst”. The acquisition burst consists of 32 bits of preamble (binary 0’s), followed by 230 bits of “zero stuffing”, and four 22-bit unique words (UW). When the Slave receives the acquisition burst from the Master correctly (by decoding the 4 consecutive UWs), it sends an acquisition burst in response. When the Master receives the acquisition burst, it sends an “empty burst”. An empty burst contains a 32-bit preamble followed by a single 22-bit unique word, and 296-bit of “1” (One stuffing). In response to the master’s empty burst, the Slave also sends an empty burst back to the Master. When the Master receives the empty burst from the Slave, the communication link is considered to have been established and “sync” condition achieved. On the following burst, both the Master and the Slave start genuine data transmission by sending out “data bursts”. Each of the data bursts contain a 32-bit preamble, followed by a 22-bit UW, a 8-bit Signaling Word (SW), and 288 bits of user data. The three different types of burst frame structures are shown in Figure 13. f burst fmosc fchip fmosc
Figure 13. Burst Frame Structures between the time the Slave stops transmission and the Master commences transmission. transmitter, the master and slave therefore contribute a total of 12-bit internal delay). fails to detect the proper UWs from the slave.
Figure 14. Receiver Lock State Machine to an RSSI signal. Note that the NMODE signal is independent of the UW detection. achieved. The LOCKED and RLOCK states are as described previously.
(MO) of 16.384 MHz, this system delay translates into 5.625 msec. Figure 15. System Delay
12.9.1 Full Duplex Operations
data transmission. A Slave waits for a valid spread spectrum signal to arrive. when LOCK is achieved is also sent to the interrupt module. The interrupts and transfer of data with the FIFOs is allowed once LOCK is achieved. achieved when the TXshl is 5 and TXshh is 22.
(when there is no data and transmission is enabled, all “1”s will be sent). overflow for the RXFIFO are provided. depends on the values of thresholds and burst rates. A typical start-up of the data link is also shown in Figure 17. data field) indefinitely or until the Master is disabled. Figure 16. Full-Duplex Data Interface Timing
12.9.2 Threshold Value Calculation
The performance of the MCU should be considered when calculating TXshl and RXshh.
Direct Sequence Spread Spectrum Baseband Modem (SSTM) 44 PRELIMINARY V1.8 time for receiving RXshh bytes from the channel should be more than the time required by the MCU to read the data from the RX FIFO. 12.10. Half-duplex Operation The half-duplex data mode is suitable for applications such as wireless LAN or pocket radio. The SSTM does not make any assumption about the higher level protocol and relies on these higher level protocols to provide the necessary framing, error correction, and preamble. The SSTM will transmit and deliver the data stream without multiplexing any protocol overhead bits, as it is the case for the full-duplex operation. Having the serial data stream from the channel and 8-bit wide parallel bus interface to the CPU, the data bytes should be aligned starting from the first bit of data. this alignment is supported by the SSTM hardware. The data alignment is achieved in the half duplex mode by the inserting the UW into the data stream as follows: 1. On the transmit side a 24 bits UW (22 bits of the UW and 2 bits “don't care”) should be inserted in front of the first data bit by the software. The 2 bits “don’t care” are the two MSBs of Byte0. The UW should not be loaded into the 3 UW registers of SS1105. 2. On the receive side the same 3 bytes of the UW should be loaded into the 3 UW registers of the SS1105. 3. A receiver recognizes the UW by SS1105 hardware and loads the data into the receive FIFO. The interrupt from the receive FIFO will be generated only after the UW was received properly. The data will be aligned in the receive FIFO by bytes. 4. The UW should be reloaded in the receiver each time the direction of transmission is changed (it should be done anyway because the chip will reset when the RTS_N value is changed). Thus if a transmitter became a receiver, the UW should be loaded into the register. 5. All required preamble bits should be sent anyway (at least 70 of them). The “Lock” UW is not received. It means that the “Lock” signal and “Lock” bit can be generated before the interrupt from the RXFIFO. 6. The UW should be inserted into the data stream as follows: Transmit side: (Byte2 MSB first) (Byte1 MSB first) (Byte0 MSB first) (Preamble bits) -> The transmit data and preamble should be loaded into the TX fifo in the following order: Preamble N byte Byte0 Byte1
Direct Sequence Spread Spectrum Baseband Modem (SSTM) PRELIMINARY V1.8 45 Byte2 Receive side: The UW should be loaded into the UW registers in the following order: Regtr Order UW0 Byte2 UW1 Byte1 UW2 Byte0 It is the user’s responsibility to ensure that each packet transmitted contains enough preamble bits so that acquisition can be achieved prior to actual data delivery. Also, the invalid receive data will be present at the output due to hysteresis of the digital phase-locked loop. Thus, the user must be able to detect the end-of-packet from the data received rather than relying on the SSTM to signify loss of the interrupt signal or loss of the lock. The SSTM in the Transmit mode (RTS_N is disabled) will transmit “1” if there is no data in the TXFIFO. Because no overhead in multiplexing is required, in half-duplex mode, the highest data rate supportable is equivalent to the burst rate of the full-duplex mode. For example using a MO of 30.72 MHz this can be set at 160 Kbps. The relationship between the data rate and the required MO is as followed: (EQ 4)fdata fmosc
Figure 17. Typical Communication Link Start-Up implement any desired collision avoidance schemes either in hardware and/or software. A typical timing diagram for half-duplex operation is shown in Figure 18.
Figure 18. Timing for half-duplex Operation RTS_N control bit. The SSTM Receiver will receive “1”s or data, accordingly. even if there is no transmission process at all. Those “1”s are a content of the RXFIFO. The Signaling Word (SW) and S/N register data are updated periodically by the SSTM.
circuit inside the SSTM once every 128 data bits (including overhead bits). will return by the hardware to “1” after it was cleared. TABLE 29. Table: Definition of SSTMCR
Direct Sequence Spread Spectrum Baseband Modem (SSTM) PRELIMINARY V1.8 49 Name Addr ess Bank Select CI_l[1] Inde x Write/ Read Functions CI_h 8F 0 [7:0] WR/ RD CI_h[0]: Master/Slave Selection bit (1/0) CI_h[3:1]:Number of errors allowed in the UW CI_h[4]:LockSMon CI_h[5]:Data Mode Selection/Test Mode (1/0) CI_h[6]: Half/Full Duplex Select (1/0) CI_h[7]:RTS_N bit (0 to enable) CI_l 8E 0 [7:0] WR/ RD CI_l[0]: Normal Mode CI_l[1]: High/Low Bank Select CI_l[3:2]:Width of ESD Window CI_l[4]: Set the Width of “Central Region” CI_l[5]: DPLL Accumulator 1 Reset CI_l[7:6]: Set the Width of “Detection Window” RDI FE 0 [7:0] WR/ RD Write data for TXFIFO Read data for RXFIFO IE C8 0 [7:0] WR ** Writes to this register will have no effect. The Interrupts IS[0] to IS[3] and IS[7] for the SSTM are con- nected directly to the interrupt module in the SS1102C. Thus enable can be performed in the interrupt module. The status for the remaining interrupts can be read in the SSTM IS status register. IS C8 0 [7:0] RD IS[0]: RXSW Interrupt Pending IS[1]: S/N Interrupt Pending IS[2]: TXFIFO Threshold Interrupt Pending IS[3]: RXFIFO Threshold Interrupt Pending IS[4]: TXFIFO Underflow Pending IS[5]: TXFIFO Overflow Pending IS[6]: RXFIFO Overflow Pending IS[7]: TXSW Transmit Interrupt Pending LCK 9E 0 [1:0] RD LCK[0]: LOCK Achieved for Full Duplex or NMODE Achieved for Half Duplex LCK[1]: RLOCK Achieved for Full Duplex TXSW AE 0 [7:0] Write Signaling Word to be transmitted RXSW AE 0 [7:0] Read Signaling Word received S/N AF 0 [7:0] Read Signal/Noise indicator PNA0 BE 0 [7:0] WR/ RD PNA[7:0] PNA1 CE 0 [7:0] WR/ RD PNA[15:8]
Direct Sequence Spread Spectrum Baseband Modem (SSTM) 50 PRELIMINARY V1.8 PNA2 DE 0 [7:0] WR/ RD PNA[23:16] PNA3 EE 0 [7:0] WR/ RD PNA[31:24] PNB0 BF 0 [7:0] WR/ RD PNB[7:0] PNB1 CF 0 [7:0] WR/ RD PNB[15:8] PNB2 DF 0 [7:0] WR/ RD PNB[23:16] PNB3 EF 1 [7:0] WR/ RD PNB[31:24] UW0 8F 1 [7:0] WR/ RD UW[7:0] UW1 FE 1 [7:0] WR/ RD UW[15:8] UW2 C8 1 [7:0] WR/ RD UW[21:16] TXshh 9E 1 [4:0] WR/ RD Transmitting FIFO interrupt threshold high TXshl 9F 1 [4:0] WR/ RD Transmitting FIFO interrupt threshold low RXshh AE 1 [4:0] WR/ RD Receiving FIFO interrupt threshold high RXshl AF 1 [4:0] WR/ RD Receiving FIFO interrupt threshold low PNC0 BE 1 [7:0] WR/ RD PNC[7:0] PNC1 CE 1 [7:0] WR/ RD PNC[15:8] PNC2 DE 1 [7:0] WR/ RD PNC[23:16] PNC3 EE 1 [7:0] WR/ RD PNC[31:24] PND0 BF 1 [7:0] WR/ RD PND[7:0] Name Addr ess Bank Select CI_l[1] Inde x Write/ Read Functions
TABLE 30. Control Registers CI_l[0] Should be set to LO. MSB. See Application Section. must be PLSL size).See Application Section.
CI_l[5] ACC1RES. DPLL Accumulator 1 reset. See Application Section. CI_l[7] is MSB. See Application Section. be set to LO in half-duplex data mode. Figure 14. for Locking State Machine state diagram).
the RFPWR and PLLSW are shown in Figure 19. and Figure 20. respectively. The RFPWR switch timing is designed to avoid damage to the sensitive analog receiver. that the RFPWR timing is valid for both full-duplex and half-duplex modes. data rate in full-duplex operation and is equaled to the data rate in half-duplex operation. LO as soon as transmission is finished and before receiving commences. µsec (28*11.72=328) prior to TXEN assertion. Figure 19. RFPWR Timing
Figure 20. PLLSW Timing (Full-Duplex Mode) included on the chip for testing purpose only). wide, and WSL to 8 samples wide). enhanced if ACC1 is reset during each “freeze PLL” period. In half-duplex operation. ACC1RES should be set to “1” to always reset ACC1.
Direct Sequence Spread Spectrum Baseband Modem (SSTM) PRELIMINARY V1.8 55 CI_h[0] is used to set the SSTM to be either a master or a slave. Typically the unit that initiates the signalling process should be programmed to become the master. NOTE, for half-duplex operation, CI_h[0] MUST be set to LO (e.g., as a slave). There is no concept of master or slave in the half-duplex operation. Instead, the SSTM is keyed by the RTS_N bit enable to go into transmit mode. The SSTM stays in the receive mode otherwise. The number of allowable errors in UW depends on the application. For example, applications that can tolerate a larger BER can usually allow more UW errors while still maintaining a reasonable communication link. Finally, CI_h[4] enables or disables the Locking State Machine. The locking state machine when used in conjunction with the programmable allowable UW errors gives the system designer the flexibility to tailor the SSTM for a particular operating environment. Typically, by enabling the Locking State Machine and by allowing more UW errors, the SSTM will continue to operate normally even in a marginal communication link channel without repeatedly loosing lock and going into acquisition. The disadvantage is the corresponding increase in the data errors; for some critical applications, this might not be tolerable. In this case, the number of allowable UW errors can be reduced and the locking state machine turned off. 12.17. PN Sequence and UW Selection Four 32-bit PN sequences and one 22-bit Unique Word (UW) are required for each spread spectrum communication device. Together, they can constitute a “security code” or “identification code” which can be use to distinguish different users as well as to provide privacy. In addition, the PN sequences and UW participate in the signal acquisition and burst synchronization processes. In order to ensure good system performance, the PN sequences and UW must be selected with some care. In the following, guidelines for choosing the PN sequences and UW are presented. 12.18. PN Sequence Selection The four PN sequences are used to represent a di-bit symbol in the SSTM. In order to correctly decode the transmitted symbol at the receiver, the following principles should be followed when choosing the four PN sequences. 1. The four PN sequences should be orthogonal to each other. Two PN sequences A and B are orthogonal to each other if, (EQ 5) where PN sequence A = [A31, A30, A29,…, A1, A0], for , and for ; similarly for B. 2. The PN sequences should be even, i.e., each sequence should have the same number of zeros and ones. 3. The PN sequences should not have more than four consecutive identical bits. ai bi⋅ i0= ∑ 0= ai 1–=A i 0=a i 1= A i 1=
Direct Sequence Spread Spectrum Baseband Modem (SSTM) 56 PRELIMINARY V1.8 With these three criteria outlined above, it is possible to generate a large set of valid PN sequences. Two additional and optional criteria can be used to further identify PN sequences for reduced self- and cross-interference. 4. The auto-correlation side lobes of the PN sequences should be less than the auto-cor- relation of the main lobe by at least 4. 5. The cross-correlation of PN sequences between sets (one set being the four orthogo- nal PN sequences for one spread spectrum chip) should also be less than the auto- correlation of the main lobe by at least 4. 12.19. UW Selection The UW is used in the receiver in full-duplex mode to establish synchronization. To avoid interference, the UW must be chosen such that it has good auto-correlation and cross-correlation properties. The auto-correlation of a sequence A denoted as S N is defined as, (EQ 6) where L is the length of the sequence A, , , for , and for . A “window” version of SN can also be defined as per (EQ 6) with the exception that , where W is the window size. The desired auto-correlation property is that the maximum value of the auto-correlation S N (with or without the window where the window size is the size of the detection window, WSL) is less than , where T is the allowable number of UW errors programmed into the SSTM. The cross-correlation of two sequences A and B, denoted by RN is defined as, (EQ 7) where L is the length of the sequence, , and for . As before, the desirable cross-correlation property is that the maximum value of the cross- correlation R N is less than , where L and T are as defined previously. Requirements for choosing good UWs can be thus summarized by the following equations. (EQ 8) For example, when T is programmed to be 4, then SN and RN should be less than 14 since L is 22. SN ai aiN–⋅ i0= L ai ai2 2–=i L ≥ 0NW<< L2T ×– R N ai biN–⋅ i0= L 0N≤ L< bi bi2 2+=i 0 < L2T ×– SN L2T ×–< R N L2T ×–<
Direct Sequence Spread Spectrum Baseband Modem (SSTM) PRELIMINARY V1.8 57 12.20. Generating the PN and UW sequences There are many ways of generating the PN and UW sequences, including brute force search of the complete code space. A more efficient but probably not optimal way of generating the PN and UW sequences is to 1. Generate the M and Gold sequences of order N where (EQ 9) and where L is the length of the PN or UW sequence. 2. Because M and Gold sequences are only bits long, it is necessary to append an additional bit to these sequences so that they are 2 N bits long. The additional bit should be chosen such that the modified M or Gold sequence is even. 3. Apply the criteria outlined in the previous sections to pick out the good set of PN and UW sequences. NL 2log= 2N 1–
IRQ1 Pin Event, and reset make the device change modes. Figure 21. Power Saving Modes & Transitions
modes. These are controlled by PSCR[2:0] (Power Saving Register bit 2 to 0). (High-Z mode). The bit-4 of PSCR(HIZ) selects a mode between them. In any mode of Clocking Modes, any Pin State Mode can be selected. two instructions should be NOP (No Operation). TABLE 31. Clocking Power-Saving Mode Definition and PSCR
TABLE 32. Clocking Power-Saving Mode Definition and PSCR used as a System Clock to control the CPU and Peripherals. In the FastAll mode, the content of the PSCR is xxxxx000B (x: don’t care, B:binary). After Reset from any mode, the MCU goes into the FastAll mode. transitions from FastAll mode are performed by software. This is a slow operation mode. All of MCU may operate with low speed(32.768KHz). Slow Clock is used as a System Clock to control the CPU and Peripherals. In the SlowAll mode, the content of the PSCR is xxxxx010B (x: don’t care, B:binary). After Reset from this mode, the MCU goes into the FastAll mode. mode. All three mode transitions from SlowAll mode are performed by software. In the StopAll mode, the content of the PSCR is xxxxx110B (x: don’t care, B:binary). into FastAll mode. In this transition case, all SFR and RAM data will be retained.
PRELIMINARY V1.8 61 13.6. FastPeri mode (a Clocking Mode) This is a fast Peripheral operation mode. The CPU is halted. All of Peripheral may operate with fast speed. Fast and Slow oscillators generate clock signals. The Fast Clock is used as a System Clock to control the Peripherals. In the FastPeri mode, the content of the PSCR is xxxxx001B (x: don’t care, B:binary). After Reset from this mode, the MCU goes into the FastAll mode. Next available Clocking Modes is the FastAll mode only. The mode transition from FastPeri mode is performed by an interrupt. In this mode CPU SFRs (Special Function Registers such like PSW, ACC, and etc.) and RAM data will be retained. 13.7. SlowPeri mode (a Clocking Mode) This is a slow Peripheral operation mode. The CPU is halted. All of Peripheral may operate with slow speed (32.768KHz). Fast oscillator is halted. Slow oscillators generate clock signals. The Slow Clock is used as a System Clock to control the Peripherals. In the SlowPeri mode, the content of the PSCR is xxxxx011B (x: don’t care, B:binary). After Reset from this mode, the MCU goes into the FastAll mode. Next available Clocking Modes is the SlowAll mode. The mode transition from SlowPeri mode is performed by an interrupt. In this mode CPU SFRs (Special Function Registers such like PSW, ACC, and etc.) and RAM data will be retained. 13.8. NorPin mode (a Pin State Mode) This is a normal operation mode. All of pin state can be controlled by software or hardware. This is an initial state after Reset. In the NorPin mode, the content of the PSCR is xxx0xxxxB (x: don’t care, B:binary). The mode transition from NorPin mode to HIZ mode is performed by software. The NorPin mode can be combined with any kinds of Clocking Power-Saving modes. 13.9. HIZ mode (a Pin State Mode) This is a Pin State Power-Saving mode. All of normal port pin state become high- impedance state to remove static current. Thus, port pin state can not be controlled by software or other hardware. In the HIZ mode, the content of the PSCR is xxx1xxxxB (x: don’t care, B:binary). The mode transition from HIZ mode to NorPin mode is performed by software and reset. The HIZ mode can be combined with any kinds of Clocking Power-Saving modes. In the HIZ mode, the port register content will be retained if software or hardware don’t change them. For PORT-0 to 4, each port will be controlled by ZCR register. But, HIZ bit directly controls PORT-4. Please, refer PORT block specification chapter.
TABLE 33. Device States in Power-Saving Modes
TABLE 34. Summary of PSCR Figure 22. Clock System & Power-saving Control tion time will be 6.4 uSec (1/10MHz x 27-1). [Bit Status: 0] Normal Pin state. [Bit Status: 1] All normal I/O pins become High-Z (impedance) state. [Bit Status: 0] Slow oscillator (32.768KHz) is used. Slow oscillator is not used. The pin XSIN is connected to ground.
TABLE 35. The Definition of Each PSCR bit TABLE 36. Summary of SREL [Bit Status: 0] Slow oscillator (32.768KHz) operates. [Bit Status: 1] Slow oscillator stops. Fast oscillator (up to 24MHz) operates and drives all CPU and peripherals. CPU control clocks drive CPU. Thus, instructions may be executed its operations normally. Thus, CPU stops to execute instructions.
TABLE 37. The Definition of Each SREL bit has different configuration. Thus, the user should carefully read the port specification. outputs the high byte of the external memory address when the address is 16-bits wide. Otherwise the Port-2 pins continue to emit the P2 SFR content. it is enabled in other mode, unexpected mode transition will be happened.
TABLE 38. Port 1 and Port 3 Functions port pin is stuck at 0 (low). Some instructions, that read a port (Port-0 to 3 only), read the latch and others read pin.
TABLE 39. Read-Modify-Write Instructions
- Reading the latch rather than the pin will return the correct value of 1.
TABLE 40. Definition of PCR Figure 23. Pcr & Port Direction Control: Port-0 To 3
TABLE 41. Definition of ZCR Figure 24. Pad Cell
is disconnected and pin status becomes high impedance. Register) becomes high, pin status becomes high impedance. A/D Mode, the ZCR0 must be low (reset value) not to support Hi-Z state. = 1, Port-0.x output buffer will become N-channel Open Drain. Figure 25. PORT-0
TABLE 42. Definition of P0
TABLE 43. Definition of P0IO TABLE 44. Definition of P0RD
TABLE 45. Definition of P0NOPN Modify-Write instructions read the port latch than the pin. is disconnected and pin status becomes high impedance. Register) becomes high, pin status becomes high impedance. Mode, the ZCR2 must be low (reset value) not to support Hi-Z state. = 1, Port-2.x output buffer will become N-channel Open Drain.
Figure 26. PORT-2
TABLE 46. Definition of P2 TABLE 47. Definition of P2IO
TABLE 48. Definition of P2RD TABLE 49. Definition of P2NOPN before. Read-Modify-Write instructions read the port latch than the pin.
P1.6/SPIIN, and P1.7/SPICLK can be used LBD or SPI input pins. Register) becomes high, pin status becomes high impedance. To use P1.5/SPIO and P1.7/SPICLK as an SPIO output port, PCR1 should be high. And, an SPI output should be enabled in the SPI block. = 1, Port-1.x output buffer will become N-channel Open Drain. TABLE 50. Definition of P1
TABLE 51. Definition of P1IO TABLE 52. Definition of P1RD
TABLE 53. Definition of P1NOPN before. Read-Modify-Write instructions read the port latch than the pin. Register) becomes high, pin status becomes high impedance.
To use P3.3/TXEN and P3.4/MODOUT as a special output port, PCR3 should be high. And, a special output should be enabled in each block. = 1, Port-3.x output buffer will become N-channel Open Drain. Figure 27. Port 3
TABLE 54. Definition of P3 TABLE 55. Definition of P3IO
TABLE 56. Definition of P3RD
TABLE 57. Definition of P3NOPN During External Memory Mode, P4.2 to P4.3 are used as ALE, and PSEN. be used as special output pins (P4.0/RFPWR, P4.1/PLLSW, P4.2/LOCK). reads pin status. If P4LATIN(PCR bit-5) = 1, CPU reads port latch rather than pin. status becomes high impedance. Register) becomes high, pin status becomes high impedance. should be enabled in register SSTMCR of the SSTM block. = 1, Port4.x output buffer will become N-channel Open Drain.
Figure 28. Port 4
TABLE 58. Definition of P4 TABLE 59. Definition of P4IO
TABLE 60. Definition of P4RD TABLE 61. Definition of P4NOPN
cycle, interrupt request flag IRQiF will be set. Flag bit IRQiF then requests the interrupt. state) in the interrupt service routine. TABLE 62. IRQi (i = 0 to 5) Mode Selection Ratio, and Lock. These interrupt sources are divided into 5 groups.
Enable), which disables all interrupts at once. Figure 29. Block Diagram of Interrupt Group-A
Figure 34. Interrupt Control Block Diagram
TABLE 63. Definition of INT0 TABLE 64. Definition of INT1
TABLE 65. Definition of INT2
15.3.1 Interrupt Source Enable Registers (ISE0, ISE1, ISE2)
TABLE 66. Definition of ISE0
TABLE 67. Definition of ISE1
TABLE 68. Definition of ISE2
15.3.2 Interrupt Group Enable Register (IE)
TABLE 69. Definition of IE
15.3.3 Interrupt Priority Register (IP)
by the polling sequence, as follows.
1 Group-A IRQ1/1 0003H Highest
2 Group-B RXFINT/TXFINT/LOCKINT 000BH
3 Group-C SWINT/SNRINT/SPIINT 0013H
4 Group-D LBDINT/WDINT 001BH
TABLE 70. Internal Priority and Vector Address TABLE 71. Definition of IP
15.3.4 Interrupt Processing
- An interrupt of equal or higher priority level is already in progress
- The current polling cycle is not the final cycle in the execution of the instruction in
- The instruction in progress is RETI.
- The instruction in progress is any access to the IE or IP registers.
5 Group-E TBINT/CT1INT/CT2INT 0023H Lowest
PRELIMINARY V1.8 97 before vectoring to any service routine. Condition 3 & 4 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before any interrupt is vectored to. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note then that if an interrupt flag is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag once active but not serviced is not remembered. Every polling cycle is new. The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate service routine. It also clears the flag that generated the interrupt. The hardware generated LCALL pushes the contents of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to. Executing proceeds from that location until the RETI instructions is encountered. The RETI instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress.
will return to the to the general purpose I/O functions after reset has gone inactive. through the emulation interface. TABLE 72. Extra Pins Function
PRELIMINARY V1.8 99 program memory fetch and all MOVX data memory fetches either internal or external are made to look like external data memory fetches. Both of these fetches are designed to occur through the same emulation interface bus with no disturbances to the port outputs. The emulator can access the internal IRAM by using the appropriate opcodes to read and write this onchip data memory. The ENMON input is used by the emulator to stop internal activities such as timers, interrupts, and serial I/O for exercising emulation activities such as step mode, or modifying registers etc.Figure 35. Emulation Instruction Fetch From Program Memory State 4 State 5 State 6 State 1 State 2 State 3 NX1 EALE Data In Address 7-0 out Address 7-0 out Adress 15-8 out Address 15-8 out EAD7-0 EPSEN EA15-8
SM8200 core being the opcode input to the CPU. TABLE 73. External Memory Interface Pin Description
Figure 38. External Instruction Fetch From Program Memory functions are listed below along with timing diagrams.
TABLE 74. External Memory Pins Description
performs as a 1-bit A/D converter. necessary for the block and their timing. TABLE 75. Comparator Main Features
Figure 39. Comparator Module Block Diagram register allows the user to read the comparator output.
TABLE 76. Definition of CMPRCR Figure 40. Comparator Output Plot
Power-On Reset (POR) PRELIMINARY V1.8 107 18. Power-On Reset (POR) 18.1. General The power-on reset circuit provides internal SS1102C reset for most power-up situations. POR consists of power-up detect block, start-up timer, and reset latch. Output of the reset latch is an internal reset (chip_reset) signal. This signal goes low when Vcc rises to the specified level and the signal goes high after some specified interval of time. This interval is determined by the start-up timer. Ramping up of Vcc generates the Power-up Detect (PUD) signal. This signal does not come until Vcc achieves a level where the logic circuits of the POR start to operate. The POR is used only at power-up and should not be used to detect drops in power supply voltage. The PUD is multiplexed with Nreset (external reset signal). The SS1102C becomes functional after the chip_reset is generated. Figures 1 and 2 show timing diagrams. 18.2. Operation At power-up, the reset latch and the start-up timer are reset to appropriate state by the PUD pulse. After some time interval (2n pulses of the high frequency clock for an n-bit counter) the start-up timer will trigger the reset latch (if there is no Nreset active) and thus issue the chip_reset signal. The chip_reset signal will be generated by the internal POR circuit when Nreset signal is held high. The Nreset can be used to override the internal reset. 18.3. Crystal Oscillator Start-Up Time After Vcc achieves the operational level, the crystal oscillator will require time to stabilize. This is the crystal oscillator start-up time. Low frequency crystals have a typical start-up time of 1-2sec. Higher frequency crystals have shorter start-up times (1-2ms). Start-up times are voltage dependent. The SS1102C uses the high frequency crystal for the start-up timer because it is the default clock at reset time. The counter delay is designed to be longer than the start-up time of the high frequency crystal so the fast clock will be stabilized before the chip is reset. The user’s software should account for the low frequency crystal’s start-up time.
Figure 41. External Reset Asserted
Low Battery Detect (LBD) - Low Voltage Reset 110 PRELIMINARY V1.8 19. Low Battery Detect (LBD) - Low Voltage Reset 19.1. General Information The low battery detect and low voltage reset circuit has two main functions.
- Used as a low battery detector, the circuit will detect the Vcc of the SS1102C falling below the selected programmable level of 2.9, 2.8 or 2.7 volts. Once detected, the circuit will send an interrupt to the SS1102C interrupt block.
- For non-battery usage the circuit can be programmed to detect Vcc falling below 2.6 volts and provide a hardware reset to the SS1102C, thus protecting the user from getting corrupted data on chip from power supply glitches below the 2.6 volt, mini- mum voltage level. 19.2. Functional Description The low battery detect and low voltage reset circuit uses a programmable resistor ladder to sense the variation of the power supply Vcc. The sensed voltage is compared against a reference voltage generated on chip. The output of the comparator is used to provide an interrupt signal for the low battery detect function or the reset for the low voltage reset function. The selection of low battery detect thresholds or the low voltage reset is controlled by the microprocessor. Once a low battery detect threshold has been detected, the circuit could be reprogrammed by the software to use the next lower voltage threshold. The circuit may be disabled to save power between readings or when not required for a particular application. supply voltage (Vdd) 2.7 - 3.3V and 4.5 - 5.5V current enable mode max. 28uA at 3.3V and max. 41uA at 5.5V supply current disable mode 3nA at 3.3V and 83nA at 5.5V temperature range -20 to +85
Figure 44. Low Battery Detect Block Diagram
TABLE 77. Definition of LBDCR This status corresponds to normal operation. reset outputs of the LBD are disabled. analog input and disable the digital input to the port. This status is to enable the digital input for the i/o port. This status corresponds to a low battery detect voltage of 2.9V, level 4. This status corresponds to a low battery detect voltage of 2.8V, level 3. This status corresponds to a low battery detect voltage of 2.7V, level 2.
114 PRELIMINARY V1.8 20. DC PARAMETRICS 20.1. I/O Characteristics 20.2. Power Characteristics 21. AC Specifications VIL VIH VOL VOH IOL IOH Vcc Vss Temperatur e Vss + 0.8 max Vcc - 0.8 min Vss + 0.4 max Vcc-0.4 min 2.96 mA @VOL=V ss+ 0.4V 3.10 mA @VOH= Vcc-0.4V 3V+/ 10% 0V -20 C degree to +85 C degree ICC Standby ICC Active Vcc Vss Temperatur e 50 uA max 30mA max 3V+(- )10% 0V -20 C degree to +85 C degree SPEC Description Min Max Unit Condition TCYC XFIN oscillator period 83.3 ns TCYCH XFIN high 30 ns TCYCL XFIN low 30 ns TCYCR XFIN rise time 10 ns TCYCF XFIN fall time 10 ns TCYS XSIN oscillator period 31.3 us TCYSH XSIN high 12 us TCYSL XSIN low 12 us TCYSR XSIN rise time 25 ns TCYSF XSIN fall time 25 ns
Figure 49. Interrupt Timing
- Oscillator Pad Characteristics
SS1102C I/O PAD Information PRELIMINARY V1.8 117 23. SS1102C I/O PAD Information 23.1. I/O Type 1 and Type 3 Description: Bidirectional CMOS I/O with active “High” Enable and Pullup-Enable and Open-Drain Enable Frequency (cell 2) f 1 32.768 60 KHz Peak-to-Peak Voltage Vpp 3 V Duty cycle of Xfout 50 -1% 50% 50 +1% ITEMS Symbol Min Typ Max Units Supply Voltage Vcc 3- 10% 3 3 + 10% V Ground Vss 0 V Temperature T -20 25 +85 degree C POUT-to-PAD (OUTEN-to-PAD) (Output Drive: 2 mA) @ Cl=50pF toPLH 6.5 nS toPHL 10.6 nS TR 12.6 nS TF 16.8 nS PAD-to-PADIN tiPLH 2 nS tiPHL 2 nS Transistor-pullup Rpu 50 70 100 KOhm Output High @ IOH=200 uA VOH Vcc - 0.4 V Output Low @ IOL=200 uA VOL Vss + 0.4 V Leakage Current Ileakage 1 micro A ITEMS Symbol Min Typ Max Unit
TABLE 80. I/O-Type 1 and Type 3 Specifications
TABLE 81. I/O-Type 2 Specification Description: I/O-Type 4 is Input with static Pullup equivalent 70 KOhm. TABLE 82. I/O-Type 4 Specification
TABLE 83. Oscillator Pads Specification
TABLE 84. Standard 52 Pin Device Chip
TABLE 85. Special Function Pins/Pads for Bond-out Chip (Development Version)
- 52-pins PQFP 26. Operating temperature:
- 20C to +85C PIN NAME I/O TYPE Function Description BXSOUT Buffered slow crystal clock output. (Disable with fast clock) TX input1 Voice mode transmit serial data in. Pull-up resistor. Test pin RX Voice mode receive serial data out. Test pin MHZ2_ST Voice mode clock out. FCLK_RT Voice mode frame clock out. Test Pin NXROM input1 Multichip program memory interface enable. Pull-up resistor. MD7-0 input1 Multichip program memory data interface. Pull-up resistor. EAD7-0 Low byte address and data I/O. EA15-8 High byte address EPSEN Program store enable for program memory read active low EALE Address latch enable ENWR Data memory write active low ENRD Data memory read active low ENICE input1 In circuit emulation mode input active low. Pull-up Resistor. ENMON input1 Monitor mode active low. Pull-up Resistor.
100-pin Chip. PRELIMINARY V1.8 123 27. 100-pin Chip. The table above provides the description for additional functional pins of the 100-pin SS1102. The 100-pin SS1102 pinout is shown below. PIN NAME Function Description BXSOUT Buffered slow crystal clock output. (Disable with fast clock) TX V oice mode transmit serial data in. Pull-up resistor. Test Pin RX V oice mode receive serial data out. Test Pin MHZ2_ST V oice mode clock out. Test Pin FCLK_RT V oice mode frame clock out. Test Pin NXROM Multichip program memory interface enable. Pull-up resistor. MD7-0 Multichip program memory data interface. Pull-up resistor. EAD7-0 Low byte address and data I/O. EA15-8 High byte address EPSEN Program store enable for program memory read active low EALE Address latch enable ENWR Data memory write active low ENRD Data memory read active low ENICE In circuit emulation mode input active low. Pull-up Resistor. ENMON Monitor mode active low. Pull-up Resistor.
100-pin Chip. 124 PRELIMINARY V1.8 3132 33 34 35 36 37 3839 40 41 42 43 44 45 46 47 4849 50 81828384858687888990919293949596979899100 NC VCC NRESET EA10 TST EA9 EA8 BXFOUT XFOUT XFIN EAD7 EAD6 BXSOUT XSOUT EXVSS XSIN EAD5 P40/RFPWR NC NC EAD4 P41/PLLSW EAD3 P42/LOCK XVDD P43 TX P44 EAD2 NC P45 RX P46 MHZ2_ST P47 FCLK_RT P30/CPTRU2 EAD1 P31/CPTRU1 EAD0 VSS P32/CPTRD1 EPSEN P33/TXEN P34/MODOUT EALE P35/DI P36/IRQ1 P37/IRQ2 DIREF NC NC ENRD P20 ENWR P21 P22 MD0 P23 MD1 P24 MD2 P25 MD3 P26 XVSS MD4 AVDD P00 MD5 P01 MD6 P02 MD7 NC P03 P04 P27 NC AVSS NXROM P05 ENMON P06 ENICE P07 P10 P11 NC EA15 P12 P13 EA14 P14/LBD P15/SPIO EA13 P16/SPIIN EA12 P17/SPICLK EA11 SS1102 100PQFP