SRV05-4 YFWDIODE | Alldatasheet

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1 / 10 www.yfwdiode.com Dongguan YFW Electronics Co, Ltd. ■ Features

  • ESD protection for high-speed data lines to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20μs)
  • Protects four I/O lines
  • Low capacitance: 3pF typical
  • Low clamping voltage
  • Low operating voltage: 5V ■ Absolute Maximum Ratings Ta = 25℃ Parameter Symbol Rating Unit ESD per IEC 61000-4-2 (Air) 15 ESD per IEC 61000-4-2 (Contact) 8 Peak Pulse Current (tp = 8/20μs) I PP 12 A Peak Pulse Power (tp = 8/20μs) P PK 300 W Lead Soldering Temperature T L 260 (10 Sec) Junction Temperature T J 125 Storage Temperature range T stg -55 to 150 KVV ESD 1 3 4 6 Simplified outline(SOT23-6) Low Capacitance TVS Diode Array

2 / 10 www.yfwdiode.com Dongguan YFW Electronics Co, Ltd. ■ Electrical Characteristics Ta = 25℃ Parameter Symbol Test Conditions Min Typ Max Unit Reverse Stand-Off Voltage V RWM Pin 5 to 2 5 Reverse Breakdown Voltage V BR I t = 1 mA Pin 5 to 2 6 Forward voltage V F I F = 15 mA 1.2 I PP = 1A, tp = 8/20μs Any I/O pin to Ground 12.5 I PP = 5A, tp = 8/20μs Any I/O pin to Ground 17.5 Reverse voltage leakage current I R V RWM = 5V, T=25°C Pin 5 to 2 5 uA V R = 0V, f = 1MHz Any I/O pin to Ground 3 5 V R = 0V, f = 1MHz Between I/O pins 1.5 V Junction Capacitance C J pF Clamping Voltage V C ■ Typical Characterisitics 100 110 0 25 50 75 100 125 150 Ambient Temperature - T A o % of Rated Power or I PP 0.01 0.1 0.1 1 10 100 1000 Pulse Duration - tp (µs) Peak Pulse Power - P Pk (kW)

3 / 10 www.yfwdiode.com Dongguan YFW Electronics Co, Ltd. ■ Typical Characterisitics Clamping Voltage vs. Peak Pulse CurrentPulse Waveform Forward Voltage vs. Forward Current Capacitance vs. Reverse Voltage 0 1 2 3 4 5 Reverse Voltage - V R (V) Capacitance - C j (pF) 0.00 5.00 10.00 15.00 20.00 25.00 30.00 Peak Pulse Current - I PP (A) Clamping Voltage -V C (V) Waveform Parameters: tr = 8µs td = 20µs 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 Forward Current - I F (A) Forward Voltage -V F (V) Waveform Parameters: tr = 8µs td = 20µs 100 110 0 5 10 15 20 25 30 Time (µs) Percent of I PP e td = I PP Waveform Parameters: tr = 8µs td = 20µs 3 dB/ CH1 S21 LOG REF 0 dB START .030 000 MHz STOP 3 000 . 000 000 MHz CH1 S21 LOG 20 dB/ REF 0 dB START .030 000 MHz STOP 3 000 . 000 000 MHz klaTssorCgolanA12SssoLnoitresnI

4 / 10 www.yfwdiode.com Dongguan YFW Electronics Co, Ltd. ■ Applications Information Device Connection Options for Protection of Four High-Speed Data Lines The SRV05-4 TVS is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode V F ) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 1, 3, 4 and 6. The negative reference (REF1) is connected at pin 2. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (REF2) is connected at pin 5. The options for connecting the positive reference are as follows: 1. To protect data lines and the power line, connect pin 5 directly to the positive supply rail (V CC ). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail. 2. The SRV05-4 can be isolated from the power supply by adding a series resistor between pin 5 and V CC . A value of 100k is recommended. The internal TVS and steering diodes remain biased, providing the advantage of lower capacitance. 3. In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may be used as the reference. In this case, pin 5 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). ESD Protection With RailClamps RailClamps are optimized for ESD protection using the rail-to-rail topology. Along with good board layout, these devices virtually eliminate the disadvantages of using discrete components to implement this topology. Consider the situation shown in Figure 1 where dis- crete diodes or diode arrays are configured for rail-to- rail protection on a high speed line. During positive duration ESD events, the top diode will be forward biased when the voltage on the protected line exceeds Data Line and Power Supply Protection Using Vcc as reference Data Line Protection with Bias and Power Supply Isolation Resistor Data Line Protection Using Internal TVS Diode as Reference

5 / 10 www.yfwdiode.com Dongguan YFW Electronics Co, Ltd. ■ Applications Information PIN Descriptions the reference voltage plus the V F drop of the diode. For negative events, the bottom diode will be biased when the voltage exceeds the V F of the diode. At first approximation, the clamping voltage due to the charac- teristics of the protection diodes is given by: V C = V CC + V F (for positive duration pulses) V C = -V F (for negative duration pulses) However, for fast rise time transient events, the effects of parasitic inductance must also be consid- ered as shown in Figure 2. Therefore, the actual clamping voltage seen by the protected circuit will be: V C = V CC + V F + L P di ESD /dt (for positive duration pulses) V C = -V F - L G di ESD /dt (for negative duration pulses) ESD current reaches a peak amplitude of 30A in 1ns for a level 4 ESD contact discharge per IEC 61000-4-2. Therefore, the voltage overshoot due to 1nH of series inductance is: V = L P di ESD /dt = 1X10 (30 / 1X10 ) = 30V Example: Consider a V CC = 5V, a typical V F of 30V (at 30A) for the steering diode and a series trace inductance of 10nH. The clamping voltage seen by the protected IC for a positive 8kV (30A) ESD pulse will be: V C = 5V + 30V + (10nH X 30V/nH) = 335V This does not take into account that the ESD current is directed into the supply rail, potentially damaging any components that are attached to that rail. Also note that it is not uncommon for the V F of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. It is also possible that the power dissipation capability of the discrete diode will be exceeded, thus destroying the device. The RailClamp is designed to overcome the inherent disadvantages of using discrete signal diodes for ESD suppression. The RailClamp’sintegrated TVS diode Figure 1 - “Rail-Figure 1 - “Rail-Figure 1 - “Rail-Figure 1 - “Rail-Figure 1 - “Rail-TTTTTo-Ra il” Pro-Ra il” Pro-Ra il” Pro-Ra il” Pro-Ra il” Proooootttttect ion Tect ion Tect ion Tect ion Tect ion Topolog yopolog yopolog yopolog yopolog y (Fi rst Approxim ation)(Fi rst Approxima tion)(Fi rst Approxim ation)(Fi rst Approxima tion)(Fi rst Approxim ation) Fig ure 2 - The Eff ects of Parasi tic Inductanc eFig ure 2 - The Eff ects of Parasi tic Inductanc eFig ure 2 - The Eff ects of Parasi tic Inductanc eFig ure 2 - The Eff ects of Parasi tic Inductanc eFig ure 2 - The Eff ects of Parasi tic Inductanc e When Using Discrete Components to Implemen tWhen Using Discrete Components to Implemen tWhen Using Discrete Components to Implemen tWhen Using Discrete Components to Implemen tWhen Using Discrete Components to Implemen t Rail-Rail-Rail-Rail-Rail-TTTTTo-Rail Pro-Rail Pro-Rail Pro-Rail Pro-Rail Proooootttttectionectionectionectionection Fig ure 3 - Rail -Fig ure 3 - Rail -Fig ure 3 - Rail -Fig ure 3 - Rail -Fig ure 3 - Rail -TTTTTo-Rail Pro-Rail Pro-Rail Pro-Rail Pro-Rail Proooootttttect ion Usingect ion Usingect ion Usingect ion Usingect ion Using RailCla mRailCla mRailCla mRailCla mRailCla mp Tp Tp Tp Tp TVVVVVS Arr aS Arr aS Arr aS Arr aS Arr aysysysysys

9 / 10 www.yfwdiode.com Dongguan YFW Electronics Co, Ltd. ■ Applications Information 10/100 ETHERNET PROTECTION CONT’ Ethernet circuit to provide differential and common mode protection. The SRV05-4 can not be grounded on the line side because the hi-pot test requires the line side not to be grounded. GIGABIT ETHERNET PROTECTION The clock rate of gigabit Ethernet is the same 125MHz as the 10/100 Ethernet. However, it uses a complex five level signaling and transmits at a faster data rate that makes it more susceptible to capacitance and insertion loss. The low capacitance and low insertion loss of the SRV05-4 allow it to sit on the gigabit Ethernet line without loss of signal integrity. Figure 10 shows how to connect the SRV05-4 into a gigabit ethernet on the IC side for common and differential mode protection. Notice that pin 5 of the SRV05-4 is not connected. Some may be tempted to connect it to Vcc. In the ethernet application, the Vcc lines does Figure 10 - Gigabit Ethernet Protection for Bellcore 1089 Intra-Building Protection not come out through the connector and does not need to be protected. Figure 10 shows the LC03-3.3 on the line side for the secondary line protection to Bellcore 1089 intrabuilding. If the designer only needs to meet ESD, CDE and low level lightning, the LC03- 3.3 can be omitted.

10 / 10 www.yfwdiode.com Dongguan YFW Electronics Co, Ltd. Summary of Packing Options Package Package Description Packing Quantity Industry Standard SOT23-6 Tape/Reel,7”reel 3000 EIA-481-1 +0.2 -0.1 1 2 3 456 Unit: mm 1.6 +0.2 -0.1 2.8 0.4 0.15 +0.02 -0.02 0.55 0-0.1 0.68 +0.1 -0.1 1.1 +0.1 -0.1 +0.01 -0.01 +0.2 -0.1 0.4 -0.1 +0.1