SRT512 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 49
Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 AC1, AC0
- 3 Data transfer
- 3.1 Input data transfer from Reader to SRT512 (Request Frame)
- 3.1.1 Character transmission format for Request Frame
- 3.1.2 Request Start Of Frame
- 3.1.3 Request End Of Frame
- 3.2 Output data transfer from SRT512 to Reader (Answer Frame)
- 3.2.1 Character transmission format for Answer Frame
- 3.2.2 Answer Start Of Frame
- 3.2.3 Answer End Of Frame
- 3.3 Transmission Frame
- 3.4 CRC
- 4 Memory mapping
- 4.1 EEPROM area
- 4.3 EEPROM area
- 4.4 System area
- 4.4.1 OTP_Lock_Reg
- 4.4.2 Fixed Chip_ID (Option)
- 5 SRT512 operation
- 6 SRT512 states
- 6.1 POWER-OFF state
- 6.2 READY state
- 6.3 INVENTORY state
- 6.4 SELECTED state
- 6.5 DESELECTED state
Features
■ ISO 14443-2 Type B Air Interface compliant ■ ISO 14443-3 Type B Frame Format compliant ■ 13.56 MHz carrier frequency ■ 847 kHz subcarrier frequency ■ 106 Kbit/second data transfer ■ 8 bit Chip_ID based anticollision system ■ 2 count-down binary counters with automated anti-tearing protection ■ 64-bit Unique Identifier ■ 512-bit EEPROM with Write Protect feature ■ READ BLOCK and WRITE BLOCK (32 bits) ■ Internal tuning capacitor ■ 1 million ERASE/WRITE cycles ■ 40-year data retention ■ Self-timed programming cycle ■ 5 ms typical programming time ■ Packages – ECOPACK® (RoHS compliant)
Applications
■ Transport Wafer Antenna (A3) Antenna (A4) Antenna (A5)
1 Description
contains a 512-bit user EEPROM fabricated with STMicroelectronics CMOS technology. 106 Kbit/s in both reception and emission modes. Figure 1. Logic diagram select tags present at the same time within range of the reader. Table 1. Signal names
- READ_BLOCK
- WRITE_BLOCK
- INITIATE
- PCALL16
- SLOT_MARKER
- SELECT
- COMPLETION
- RESET_TO_INVENTORY
- GET_UID The SRT512 memory is organized in three areas, as described in Table 3. The first area is an EEPROM area where all blocks behave as User blocks. The second area provides two 32-bit binary counters that can only be decremented from FFFF FFFFh to 0000 0000h, and gives a capacity of 4,294,967,296 units per counter. The last area is the EEPROM memory. It is accessible by block of 32 bits and includes an auto-erase cycle during each WRITE_BLOCK command.
Figure 2. Die floor plan
2 Signal description
2.1 AC1, AC0
The pads for the Antenna Coil. AC1 and AC0 must be directly bonded to the antenna.
3 Data transfer
3.1 Input data transfer from R eader to SRT512 (Request Frame)
represented in Figure 3. The data transfer rate is 106 Kbits/s. Figure 3. 10% ASK modulation of the received wave
3.1.1 Character transmission format for Request Frame
(Elementary Time Unit), is equal to 9.44 µs (1/106 kHz). command, but it does not generate an error frame. Figure 4. SRT512 Request Frame character format
1 ETU
3.1.2 Request Start Of Frame
- one falling edge,
- followed by 10 ETUs at logic-0,
- followed by a single rising edge,
- followed by at least 2 ETUs (and at most 3) at logic-1.
Figure 5. Request Start Of Frame
3.1.3 Request End Of Frame
- one falling edge,
- followed by 10 ETUs at logic-0,
- followed by a single rising edge.
Figure 6. Request End Of Frame Table 2. Bit description
3.2 Output data transfer from SRT512 to Reader (Answer Frame)
s as shown in Figure 7, and as specified in the ISO14443-2 Type B Standard. Figure 7. Wave transmitted using BPSK subcarrier modulation
3.2.1 Character transmission format for Answer Frame
3.2.2 Answer Start Of Frame
- followed by 10 ETUs at logic-0
- followed by 2 ETUs at logic-1
Figure 8. Answer Start Of Frame
3.2.3 Answer End Of Frame
- followed by 10 ETUs at logic-0,
- followed by 2 ETUs at logic-1.
Figure 9. Answer End Of Frame
3.3 Transmission Frame
13.56 MHz carrier frequency is modulated by the SRT512 at 847 kHz for a period of
Figure 10. Example of a complete Transmission Frame
3.4 CRC
The two-byte CRC is present in every Request and in every Answer Frame, before the EOF . The CRC is calculated on all the bytes between SOF (not included) and the CRC field. Upon reception of a Request from a reader, the SRT512 verifies that the CRC value is valid. If it is invalid, the SRT512 discards the frame and does not answer the reader. CRC. In case of error, the actions to be taken are the reader designer’s responsibility. the least significant bit first. Figure 11. CRC tr ansmission rules
4 Memory mapping
The SRT512 is organized as 16 blocks of 32 bits as shown in Table 3. All blocks are accessible by the READ_BLOCK command. Depending on the write access, they can be updated by the WRITE_BLOCK command. A WRITE_BLOCK updates all the 32 bits of the block. Table 3. SRT512 memory mapping
Description
5 32 bits binary counter Count down Counter6 32 bits binary counter 7U s e r A r e a Lockable EEPROM 8U s e r A r e a 9U s e r A r e a
10 User Area
11 User Area
12 User Area
13 User Area
14 User Area
15 User Area
255 OTP_Lock_Reg 1 ST Reserved Fixed Chip_ID
(Option) System OTP bits UID0 64 bits UID Area ROM UID1
4.1 EEPROM area
Blocks 0 to 4 define a User Area. They behave as standard EEPROM blocks, like blocks 7 to 15 as described in Figure 12. Each block can be individually write-protected using the OTP_Lock_Reg bits of the system area. Once a block has been protected, it can no longer be unprotected. Figure 12. Lockable EEPROM area (addresses 0 to 4) Figure 13. Binary counter (addresses 5 to 6) MSb 32-bit Block LSb Description Count down Counter 32-bit Binary Counter 32-bit Binary Counter ai12384 b31 b16 b15 b14 b8 b7 b0
Figure 14. Count down example (binary format)
4.3 EEPROM area
EEPROM area always includes an Auto-Erase cycle prior to the Write cycle. Figure 15. EEPROM (addresses 7 to 15)
4.4 System area
This area is used to modify the settings of the SRT512. It contains 3 registers: OTP_Lock_Reg, Fixed Chip_ID and ST Reserved. See Figure 16 for a map of this area. A WRITE_BLOCK command in this area will not erase the previous contents. Selected bits can thus be set from 1 to 0. All bits previously at 0 remain unchanged. Once all the 32 bits of a block are at 0, the block is empty and cannot be updated any more. Figure 16. System area
4.4.1 OTP_Lock_Reg
- When b16 is at 0, block 0 is Write-protected
- When b17 is at 0, block 1 is Write-protected
- When b18 is at 0, block 2 is Write-protected
- When b19 is at 0, block 3 is Write-protected
- When b20 is at 0, block 4 is Write-protected
- When b21 is at 0, block 5 is Write-protected
- When b22 is at 0, block 6 is Write-protected
- When b23 is at 0, block 7 is Write-protected
- When b24 is at 0, block 8 is Write-protected
- When b25 is at 0, block 9 is Write-protected
- When b26 is at 0, block 10 is Write-protected
- When b27 is at 0, block 11 is Write-protected
- When b28 is at 0, block 12 is Write-protected
- When b29 is at 0, block 13 is Write-protected
- When b30 is at 0, block 14 is Write-protected
- When b31 is at 0, block 15 is Write-protected. The OTP_Lock_Reg bits cannot be erased. Once Write-protected, the blocks behave like ROM blocks and cannot be unprotected. After any modification of the OTP_Lock_Reg bits, it is necessary to send a SELECT command with a valid Chip_ID to the SRT512 in order to load the block write protection into the logic. This bit is set by ST during production tests on customer request. It cannot be modified by the user. Block Address 255 MSB 32-bit Block LSB
OTPOTP_Lock_Reg ST Reserved Fixed Chip_ID (Option) ai13505 b31 b16 b15 b14 b8 b7 b0
4.4.2 Fixed Chip_ID (Option)
The SRT512 is provided with an anticollision feature based on a random 8-bit Chip_ID. Prior to selecting an SRT512, an anticollision sequence has to be run to search for the Chip_ID of the SRT512. This is a very flexible feature, however the searching loop requires time to run. For some applications, much time could be saved by knowing the value of the SRT512 Chip_ID beforehand, so that the SRT512 can be identified and selected directly without having to run an anticollision sequence. This is why the SRT512 was designed with an optional mask setting used to program a fixed 8-bit Chip_ID to bits b 7 to b0 of the system area. When the fixed Chip_ID option is used, the random Chip_ID function is disabled.
5 SRT512 operation
All commands, data and CRC are transmitted to the SRT512 as 10-bit characters using ASK modulation. The start bit of the 10 bits, b0, is sent first. The command frame received by the SRT512 at the antenna is demodulated by the 10% ASK demodulator, and decoded by the internal logic. Prior to any operation, the SRT512 must have been selected by a SELECT command. Each frame transmitted to the SRT512 must start with a Start Of Frame, followed by one or more data characters, two CRC Bytes and the final End Of Frame. When an invalid frame is decoded by the SRT512 (wrong command or CRC error), the memory does not return any error code. When a valid frame is received, the SRT512 may have to return data to the reader. In this case, data is returned using BPSK encoding, in the form of 10-bit characters framed by an SOF and an EOF . The transfer is ended by the SRT512 sending the 2 CRC Bytes and the EOF .
6 SRT512 states
The SRT512 can be switched into different states. Depending on the current state of the SRT512, its logic will only answer to specific commands. These states are mainly used during the anticollision sequence, to identify and to access the SRT512 in a very short time. The SRT512 provides 6 different states, as described in the following paragraphs and in Figure 17.
6.1 POWER-OFF state
The SRT512 is in POWER-OFF state when the electromagnetic field around the tag is not strong enough. In this state, the SRT512 does not respond to any command.
6.2 READY state
When the electromagnetic field is strong enough, the SRT512 enters the READY state. After Power-up, the Chip_ID is initialized with a random value. The whole logic is reset and remains in this state until an INITIATE() command is issued. Any other command will be ignored by the SRT512.
6.3 INVENTORY state
The SRT512 switches from the READY to the INVENTORY state after an INITIATE() command has been issued. In INVENTORY state, the SRT512 will respond to any anticollision commands: INITIATE(), PCALL16() and SLOT_MARKER(), and then remain in the INVENTORY state. It will switch to the SELECTED state after a SELECT(Chip_ID) command is issued, if the Chip_ID in the command matches its own. If not, it will remain in INVENTORY state.
6.4 SELECTED state
In SELECTED state, the SRT512 is active and responds to all READ_BLOCK(), WRITE_BLOCK(), and GET_UID() commands. When an SRT512 has entered the SELECTED state, it no longer responds to anticollision commands. So that the reader can access another tag, the SRT512 can be switched to the DESELECTED state by sending a SELECT(Chip_ID2) with a Chip_ID that does not match its own, or it can be placed in DEACTIVATED state by issuing a COMPLETION() command. Only one SRT512 can be in SELECTED state at a time.
6.5 DESELECTED state
Once the SRT512 is in DESELECTED state, only a SELECT(Chip_ID) command with a Chip_ID matching its own can switch it back to SELECTED state. All other commands are ignored.
6.6 DEACTIVATED state
When in this state, the SRT512 can only be turned off. All commands are ignored. Figure 17. State transition diagram
7 Anticollision
- INITIATE()
- PCALL16()
- SLOT_MARKER(). The reader is the master of the communication with one or more SRT512 device(s). It initiates the tag communication activity by issuing an INITIATE(), PCALL16() or SLOT_MARKER() command to prompt the SRT512 to answer. During the anticollision sequence, it might happen that two or more SRT512 devices respond simultaneously, so causing a collision. The command set allows the reader to handle the sequence, to separate SRT512 transmissions into different time slots. Once the anticollision sequence has completed, SRT512 communication is fully under the control of the reader, allowing only one SRT512 to transmit at a time. The Anticollision scheme is based on the definition of time slots during which the SRT512 devices are invited to answer with minimum identification data: the Chip_ID. The number of slots is fixed at 16 for the PCALL16() command. For the INITIATE() command, there is no slot and the SRT512 answers after the command is issued. SRT512 devices are allowed to answer only once during the anticollision sequence. Consequently, even if there are several SRT512 devices present in the reader field, there will probably be a slot in which only one SRT512 answers, allowing the reader to capture its Chip_ID. Using the Chip_ID, the reader can then establish a communication channel with the identified SRT512. The purpose of the anticollision sequence is to allow the reader to select one SRT512 at a time. The SRT512 is given an 8-bit Chip_ID value used by the reader to select only one among up to 256 tags present within its field range. The Chip_ID is initialized with a random value during the READY state, or after an INITIATE() command in the INVENTORY state. The four least significant bits ( b0 to b3) of the Chip_ID are also known as the CHIP_SLOT_NUMBER. This 4-bit value is used by the PCALL16() and SLOT_MARKER() commands during the anticollision sequence in the INVENTORY state.
Figure 18. SRT512 Chip_ID Description
Figure 19. Description of a possible anticollision sequence
- The value X in the Answer Chip_ID means a random hexadecimal character from 0 to F.
7.1 Description of an anticollision sequence
SLOT_MARKER(SN) anticollision commands. received the INITIATE() command and entered the INVENTORY state. generate a new sequence in order to identify all unidentified SRT512 devices in the field. The anticollision sequence can stop when all SRT512 devices have been identified. Table 4. Standard anticollision sequence – If no answer is detected, go to step1. SRT512, deselect the tag and go to step1. – If a collision (many answers) is detected, go to step2. – If no answer or collision is detected, go to step3. – If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step3. – If no answer or collision is detected, go to step4. – If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step4. – If no answer or collision is detected, go to step5. – If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step5. Send SLOT_MARKER(3 up to 14)... – If no answer or collision is detected, go to stepN+1. – If 1 answer is detected, store the Chip_ID, Send SELECT() and go to stepN+1. – If no answer or collision is detected, go to step18. – If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step18. depending on the application needs. – If collisions were detected between Step2 and Step17, go to Step2. – If no collision was detected between Step2 and Step17, go to Step1.
Figure 20. Example of an anticollision sequence
8 SRT512 commands
Table 5. Command Code
8.1 INITIATE() command
Figure 21. INITIATE request format
- No parameter
Figure 22. INITIATE response format
- Chip_ID of the SRT512
Figure 23. INITIATE frame exchange between Reader and SRT512
8.2 PCALL16() command
The SRT512 must be in INVENTORY state to interpret the PCALL16() command. CHIP_SLOT_NUMBER value (in the 4 least significant bits of the Chip_ID). until a new PCALL16() or INITIATE() command is issued, or until the SRT512 is powered off. INVENTORY state present in the reader field range. Figure 24. PCALL16 request format
- No parameter
Figure 25. PCALL16 response format
- Chip_ID of the SRT512
Figure 26. PCALL16 frame exchange between Reader and SRT512
8.3 SLOT_MARKER(SN) command
The SRT512 must be in INVENTORY state to interpret the SLOT_MARKER(SN) command.
- b3 to b0: 4-bit command code with fixed value 6.
- b7 to b4: 4 bits known as the SLOT_NUMBER (SN). They assume a value between 1 and 15. The value 0 is reserved by the PCALL16() command. On receiving the SLOT_MARKER() command, the SRT512 compares its CHIP_SLOT_NUMBER value with the SLOT_NUMBER value given in the command code. If they match, the SRT512 returns its Chip_ID value. If not, the SRT512 does not send any response. The SLOT_MARKER() command, used together with the PCALL16() command, allows the reader to search for all the Chip_IDs when there are more than one SRT512 device in INVENTORY state present in the reader field range.
Figure 27. SLOT_MARKER request format
- x: Slot number
Figure 28. SLOT_MARKER response format
- Chip_ID of the SRT512
Figure 29. SLOT_MARKER frame exch ange between Reader and SRT512
8.4 SELECT(Chip_ID) command
Chip_ID that does not match its own is automatically switched to DESELECTED state. Figure 30. SELECT request format
- 8-bit Chip_ID stored during the anticollision sequence
Figure 31. SELECT response format
- Chip_ID of the selected tag. Must be equal to the transmitted Chip_ID
Figure 32. SELECT frame exchange between Reader and SRT512
8.5 COMPLETION() command
the field. The COMPLETION() command does not generate a response. All SRT512 devices not in SELECTED state ignore the COMPLETION() command. Figure 33. COMPLETION request format
- No parameter
Figure 34. COMPLETION response format Figure 35. COMPLETION frame exchange between Reader and SRT512
8.6 RESET_TO_INVENTORY() command
commands and so, to set new random Chip_IDs. The RESET_TO_INVENTORY() command does not generate a response. Figure 36. RESET_TO_INVENTORY request format
- No parameter
Figure 37. RESET_TO_INVENTORY response format Figure 38. RESET_TO_INVENTORY frame ex change between Reader and SRT512
8.7 READ_BLOCK(Addr) command
Significant Byte first and each byte is transmitted with the least significant bit first. The address byte gives access to the 16 blocks of the SRT512 (addresses 0 to 15). commands sent to the SRT512 before a SELECT() command is issued are ignored. Figure 39. READ_BLOCK request format
- ADDRESS: block addresses from 0 to 15, or 255
Figure 40. READ_BLOCK response format
- DATA 1: Less significant data Byte
- DATA 2: Data Byte
- DATA 3: Data Byte
- DATA 4: Most significant data Byte
Figure 41. READ_BLOCK frame exchange between Reader and SRT512
8.8 WRITE_BLOCK (Add r, Data) command
transmitted with the least significant bit first. The address Byte gives access to the 16 blocks of the SRT512 (addresses 0 to 15).
- Figure 12: Lockable EEPROM area (addresses 0 to 4)
- Figure 13: Binary counter (addresses 5 to 6).
- Figure 15: EEPROM (addresses 7 to 15). The WRITE_BLOCK command does not give rise to a response from the SRT512. The reader must check after the programming time, tW, that the data was correctly programmed. The SRT512 must have received a SELECT() command and be switched to SELECTED state before any WRITE_BLOCK command can be accepted. All WRITE_BLOCK commands sent to the SRT512 before a SELECT() command is issued, are ignored.
Figure 42. WRITE_BLOCK request format
- ADDRESS: block addresses from 0 to 15, or 255
- DATA 1: Less significant data Byte
- DATA 2: Data Byte
- DATA 3: Data Byte
- DATA 4: Most significant data Byte.
Figure 43. WRITE_BLOCK response format
Figure 44. WRITE_BLOCK frame exchange between Reader and SRT512
8.9 GET_UID() command
the SRT512 before a SELECT() command is issued, are ignored. Figure 45. GET_UID request format
- No parameter
Figure 46. GET_UID response format
- UID 0: Less significant UID Byte
- UID 1 to UID 6: UID Bytes
- UID 7: Most significant UID Byte. DATA AI13514b DATA DATA DATA 4Reader SRT512 CRCL CRCH EOFSOF 09h ADDR No Response SOF GET_UID CRC L CRCH EOF AI07693 0Bh 8 bits 8 bits SOF UID 1 CRC L CRCH EOF AI07694 8 bits UID 2 UID 3 UID 4 8 bIts 8 bIts 8 bIts 8 bIts 8 bIts UID 0 UID 5 8 bIts UID 6 8 bIts8 bits UID 7 8 bIts
Members of the SRT512 family are uniquely identified by a 64-bit Unique Identifier (UID).
- an 8-bit prefix, with the most significant bits set to D0h
- an 8-bit IC Manufacturer code (ISO/IEC 7816-6/AM1) set to 02h (for STMicroelectronics)
- a 6-bit IC code set to 00 1100b = 12d for SRT512
- a 42-bit Unique Serial Number
Figure 47. 64-bit unique identifier of SRT512 Figure 48. GET_UID frame exchange between Reader and SRT512
8.10 Power-On state
- It is in the low-power state.
- It is in READY state.
- It shows highest impedance with respect to the reader antenna field.
- It will not respond to any command except INITIATE(). AI14080 D0h Unique Serial Number02h 63 55 47 0 Most significant bits Least significant bits 12d S O F CRCLCRCH E O F AI13515b Reader S O F CRCL CRCH E O F 0Bh UID UID UID UID UID UID UID UID
9 Maximum rating
Program and other relevant quality documents. Table 6. Absolute maximum ratings
- ESD test: ISO10373-6 for proximity cards
10 DC and AC parameters
Table 7. Operating conditions Table 8. DC characteristics Table 9. AC characteristics (1)
- All timing measurements were performed on a reference antenna with the following characteristics:
Figure 49. SRT512 synchronous timing, transmit and receive
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 50. A3 antenna specification Table 10. A3 antenna specification
Figure 51. A4 antenna specification Table 11. A4 antenna specification
Figure 52. A5 antenna specification Table 12. A5 antenna specification
12 Part numbering
Note: Devices are shipped from the factory with the memory content bits erased to 1. of this device, please contact your nearest ST Sales Office. Table 13. Ordering information scheme
SRT512 ISO14443 type B CRC calculation Appendix A ISO14443 type B CRC calculation #include <stdio.h> #include <stdlib.h> #include <string.h> #include <ctype.h> #define BYTE unsigned char #define USHORT unsigned short unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc) ch = (ch^(BYTE)((*lpwCrc) & 0x00FF)); ch = (ch^(ch<<4)); *lpwCrc = (*lpwCrc >> 8)^((USHORT)ch << 8)^((USHORT)ch<<3)^((USHORT)ch>>4); return(*lpwCrc); void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE *TransmitSecond) BYTE chBlock; USHORTt wCrc; wCrc = 0xFFFF; // ISO 3309 do chBlock = *Data++; UpdateCrc(chBlock, &wCrc); } while (--Length); wCrc = ~wCrc; // ISO 3309 *TransmitFirst = (BYTE) (wCrc & 0xFF); *TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF); return; int main(void) BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i; printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1”); printf("CRC_B of [ "); for(i=0; i<4; i++) printf("%02X ",BuffCRC_B[i]); ComputeCrc(BuffCRC_B, 4, &First, &Second); printf("] Transmitted: %02X then %02X.”, First, Second); return(0);
Table 14. Document revision history 12-Dec-2006 0.1 Initial release. Document status promoted from Preliminary Data to full Datasheet. 6-bit IC code changed under Unique Identifier (UID) on page 37. DC characteristics. Small text changes. All antennas are ECOPACK® compliant.