SRM2A256LLCX

SRM2A256LLMX EPSON | Alldatasheet

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EPSON ™ 256K-Bit Static RAM @ Low Supply Current @ Access Time 70ns/85ns/100ns @ 32,768 WordsxX8-bit Asynchronous @ DESCRIPTION The SRM2A256LLMX70/85/10 is a 32,768 wordsx8-bit asynchronous, static, random access memory fabricated using an advanced CMOS technology. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. The asynchronous and static nature of the memory re- quires no external clock or refresh circuit. Input and output ports are TTL compatible and the 3-state output allows easy expansion of memory capacity. @ FEATURES @ PIN CONFIGURATION SRM2A256LLMXe85 = 85s aes $ oshas SRM2A256LLMX10 —_100ns mde © Spats @ TTL compatible inputs and outputs. vests ‘ob os @ 3-state output Ves Gis 8p vos @ Battery back-up operation TSO @ Package SRM2A256LLCX70/85/10 DIP-28pin (plastic) edz Fbato SRM2A256LLMX70/85/10 SOP2-28pin (plastic) Aig 2 2oHCs SRM2A256LLTMX70/85/10 TSOP(1)-28pin (plastic) as 2 reBvoz SRM2A256LLRMX70/85/10 TSOP()-28pin-R {plastic) we C7, 16B vos BLOCK DIAGRAM aretle 1sBiuos as Ga HBivo1 as ds 101a0 aa de 9 pat as 7 a Baz zo i (ISOP-AT) Wace 3 312 Memory Cell Array as q7 @ paz ws Ol & B12xe4xe aa de 9 Ba wOl 2 x as ds 10f1A0 w Ol @ as qa 1101 xu OL e ard 12p voz mele Atel] 2 1361/03 moo] * coe Ase) srwenosounux SVS, a1 wed 27 teBros, auc >% no C24 1961/03 = 6 Ang 23 20f1cs oe ze 2i ato BO Be 8 @ PIN DESCRIPTION AQ to A14 Address Input — wu WE Write Enable =O Bs Wwe of a ree VO Butter OE Output Enable we 04 885 cs Chip Select LITT TET 01 to. 08 Data Input/Output O—-0—-0-0—-0—-0—-0—-0 Voo Power Supply(+5V) VO1 vO2 U3 VOs 185 vOs 17 VOB Vss Power Supply(0V) SEIKO EPSON CORPORATION

@ ABSOLUTE MAXIMUM RATINGS (Vsg=0V) Supply voltage ~0.5 to 7.0 ~0.5* 107.0 Input/Output voltage ~0.5* to Voo+0.3 Power dissipation A | Operating temperature 25 to 85 “65 fo 150 ‘Soldering temperature and time 260°C, 10s(Lead onl [| - | * Vi, Vio (Min.)= -3V when pulse width is less or equal to 50ns m@ DC RECOMMENDED OPERATING CONDITIONS (Vgs=0V, Ta=-25 to 85°C) [| Vop [os 5s Supply voltage = [Vag fo Po To [ imputvotage | Fe ft 2 os TV Input vokage [yf oo os Tv * Vj, (Min.)= -3V when pulse width is less or equal to 50ns @ ELECTRICAL CHARACTERISTICS @ DC Electrical characyeristics (Vpp=5V+10%, Vss=0V, Ta=-25 to 85*C) Parameter Symbol Conditions [win ffyp*]Max. Min. Typ*]Max.|Min [Typ [Max] "" Input leakage [vu | VieotoVoo | -1] - | 1 [=a] -] is [1] - Jit | ua CS=Vinj or WE=V) Output leakage LO=VIH IL = ~ High level output voltage lowetioma[2.4| -[ = [24] =] = eal -[- Tv | Low level output voltage lue2ima | = | = Joa] =] -[oa]- |= foal v | Standby supply current — VieVit, Vin Average operating current VieVit, Vin 10 10 10 | mA lyo=OMA, teyc=1p1s - VeVi, V omaingnrpveonen | tw | tnt’ 1-1 -bef-[-fel-[- [ol = | * Typical values are measured at Ta=25°C and Vpp=5.0V @ Terminal Capacitance (f1MHz, Ta=25°C) Symbol[ Conditions | Min. Typ, Max. Unit _| Address Capacitance [ Caoo [| VaoowoV, | TT Input Capacitance Po f Veov VO Capacitance [Cro [Oo Vworov TT tp @ AC Electrical Characteristics O Read Cycle (Vop=5V#10%, Vgs=0V, Ta=-25 to 85°C) Read cycle time [ 7o | - | 85 | - [100 [ - | ns | CS output floating "2 [ = [ 30 [| - | 30 [ - [35 | ns | OE output set time { o [ - [| o |- [oo [ - | ns} OE output floating | - | 30 | - | 30 | - | 35 | ns | p LOutput hold time [tw [ot to PT = TP to | = JT to T= Tons |

a O Write Cycle (Vop=5V+10%, Vss=0V, Ta=-25 to 85°C) Wiite cycle time [| vo | - [es | - [too | - [ns | Chip select time | 6o | - | vo | - {so | - [ ns | Address valid to end of write | taw | {| eo | - | 70 | - {| 80 | - [ ns | Address setup time [tas | [fo [| - [oo [= [oo [= J ns | Write pulse width | twe | bl [65] - [os | - [7s | - | ns | Address hold time | twa | fof - [o {[- fo {| - | ns | Input data set time { 30 | - [35 | - | 40 | - [ ns | Input data hold time’ fo}; - [oo f- {of -T ns | Write to Output floating Py [ - | 30 [ - [30 {| - | 35 | ns | Output Active from endto wirte | tow | [os | - [s [- [5s | = [ns | *1 Test Conditions *2 Test Conditions 2. tret-5ns 2. trett-5ns 3. Input and output timing reference levels : 1.5V 3. _ Input timing reference levels : 1.5V 4. Output load : C.=100pF 4. Output timing reference levels : 200mV(the level displaced from stable output voltage level) 5. Output load : C.=5pF (Includes Jig Capacitance) +v +v 10K0 1 8k vo v0 T a 9902 T oO 9902 (= 100pF (Includes sig Capactance) Cu=SpF (Includes Jig Capactiance) @ Timing chart © Read Cycle*! (© White Cycle(1) (GS Control"? the we Tar =I =< tes ed =e ROO‘ eee LC EEANNANNANN ANN YITIZIIIDIL Dou RXXK EX Dour XX Note : © Write Cycle(2) (WE Control)*®: #4 %1 During read cycle time, WE is to be "H" level. +2 During write cycle time that is controlled by CS, Output Buffer is ADDRESS ) > in high impedance state, whether OE level is "H" or "L"

7 Tar +3 During write cycle time that is controlled by WE, Output Buffer is

os MAMAN LLLLLLLLL in high impedance state if OE is "L" level. we

4 When I/O terminals are output mode, be careful that do not give

We = the opposite signals to the /O terminals. z tow Dow WArATavavavavavavavararal Vavaravarav OOOO) OK ele ton on a

a @ DARA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (Vss=0V, Ta=-25 to 85°C) | Dataretention supply voltage | Voon |__| 2.0] - | 55 [20] - [55/20] - [55] v | wnare | [om Pome [| [ol] elo [Chip select datahoidtime | toon | FO |= | = fo | -[-fof-]-] ns | 2k : Typical values are measured at 25°C Data retention timing a Data hold mode =| Veo 45v Voor22.0V 45V. When retaining data in standby mode, supply voltage can be lowered within a certain range, But read or write cycle cannot be performed while the supply voltage is low. @ FUNCTIONS @ Truth Table i poe tw ite toe toe | X "H" or "L" @ Read Mode The data appear when the address is setted while holding CS="L", OE="L" and WE ="H". When OE="H", DATA I/O terminals are in high impedance state, that makes circuit design and bus control easy @ Write Mode There are the following 3 ways of writing data into memory. (1) Hold CS="L" and WE="L", set address. (2) Hold CS="L" then set address and give "L" pulse to WE. (3) After setting addresses, give "L" pulse to both CS and WE In above any case data on the DATA I/O terminals are put into the SRM2A256LLMX70/85/10 when both CS and WE are in "L". Since DATA V/O terminals are high impedance when CS or OE="H", bus contention between data driver and memory outputs can be avoided. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals. @ Standby Mode When CS is "L" the SRM2A256LLMX70/85/10 become in the standby mode. In this mode, data I/O terminals are Hi-Z and all inputs of addresses, WE and data can be any "H" or "L". When CS is over than Vpp-0.2V, the SRM2A256LLMX70/85/10 is in the data retention battery back-up mode, in this case, there is a small current in the SRM2A256LLMX70/85/10 which flow through the high resistances of the memory cells.

@ PACKAGE DIMENSIONS Plastic DIP-28pin (600mil)* . Fi y Et E:] ‘ ts ° ait oto, 4 . Unit: mm tinh) Plastic SOP2-28pin (450mil) hin oon uinononnit ee TUUTOT OTT OO OOD . “ Unit : mm (inch) Plastic TSOP (I)-28pin* ; — Unit: mm (inch) %* : The same characteristics as SRM2A256LLMX70/85/10.

Plastic TSOP (I)-28pin-R1” ; soa ws, rece ooue ti, ioe (ineh) 2% : The same characteristics as SRM2A256LLMX7o0v85/10. ™ CARACTERISTICS CURVES Normalized lppa-Ta Normalized lova—Frequency Normalized |lopa—Vop DSSS Ss 4.

16 FAA ee] ost] | ware V7 | I} Ep

we EEE) SOA | ee MCCCECCEET TT] os} +A 12 Cee ere JA [Atel tt | Lp | wane A | 412 05 7 14 ZA ee eee a -ae : SSE ee TT] 0 Hee LT YET TTT Ty [Laz ore ie || 08 08| = og HEE ee [TALI TTT ety Le | e8--CECECECELELL| SALE | 8 o7 of 07 TTT TTT TTT TTT) gg LE TT ETT TT I a ee ‘840-200 «20 40 60 80 0 2 4 6 8 10 12 14 16 18 20 06S 5.0 55 Tac) Fremency ue) Vop (V) Normalized loos1-Ta Normalized loos:—Voo Normalized loH—VoH FREER | open d | EE TT ewe 7 20 =552==522=222-( oa FREESE) | oops] el EE ro SEC) ope) uw Sean eeees eeee a a BSSSeeceaaanae oo + NP aoe ee Pe HEY GUEERRREE NE =ssa=SSS==SSS= oot | | N | os 4.0 5.0 60 “10 20 30 40 50 cos CLE EEE} 40 -20 0 20 40 60 80 Voo (V) Vou (V) Ta (°C)

Normalized tas5) ~Ta Normalized (£2 —Voo Normalized lo.-Vot al LLOOo ee ef ett 4 ee a ec OA OTH | oe i BOOTLE ETT TT] sos) Nh pe Peer) ofS | EP A OE ose | TS | os | ZF . ee ey 4 Taco) ott | J) ol LZP 1 TT ee 08 as 5.0 35 oO 02 04 O06 08 Von (V) VoL(V) Normalized (£22 -C1 ta. 11 J iw yep | 1 4} —} 4 ese 4 y3- | 7 | a 7, So {ZL 4o/ —” | | og 1. | | oss |_| o7-_| | og —__L TT 100 200 300 400 CL (pF)