SRM20V100

SRM20V100 EPSON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

CS1, CS2 I/O1 to I/O8 V DD VSS Address Input Write Enable Output Enable Chip Select Data I/O Power Supply (2.7V to 3.6V) Power Supply (0V) N. C. No connection A10 A11 A12 CS1 OE WE I/O Buffer Column Gate Memory Cell Array 1024×128×8 128×8 10 1024 7 128 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 A13 A15 A16 A14 CS2 Address Buffer X DecoderY Decoder Chip Control CS1, CS2 Chip Control OE, WE 1A11 32 OE 2A9 31 A10 3A8 30 CS1 4A13 29 I/08 5WE 28 I/07 6CS2 27 I/06 7A15 26 I/05 8VDD 25 I/04 9N.C. 24 V SS 10A16 23 I/03 11A14 22 I/02 12A12 21 I/01 13A7 20 A0 14A6 19 A1 15A5 18 A2 16A4 17 A3 16A4 17 A3 15A5 18 A2 14A6 19 A1 13A7 20 A0 12A12 21 I/01 11A14 22 I/02 10A16 23 I/03 9N.C. 24 V SS 8VDD 25 I/04 7A15 26 I/05 6CS2 27 I/06 5WE 28 I/07 4A13 29 I/08 3A8 30 CS1 2A9 31 A10 1A11 32 OE (SOP6) (TSOP/Slim-TSOP)

32 V DD

N.C. 1

31 A15A16 2

30 CS2A14 3

29 WEA12 4

28 A13A7 5

27 A8A6 6

26 A9A5 7

25 A11A4 8

24 OEA3 9

23 A10A2 10

22 CS1A1 11

21 I/08A0 12

20 I/07I/01 13

19 I/06I/02 14

18 I/05I/03 15

17 I/04VSS 16

(TSOP-R1/Slim-TSOP-R1) SRM20V100LLTX/KX SRM20V100LLRX/YX 1M-Bit Static RAM PF805-04 SRM20V100LLMX 7 n DESCRIPTION The SRM20V100LLMX 7 is an 131,072 words×8-bit asynchronous, static, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. And —25 to 85°C operating temperature range makes it ideal for portable equipment. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity. n FEATURES 0.3µA (Typ.): SL Version operation: 8mA/1MHz (Typ.) l TTL compatible inputs and outputs l 3-state output with wired-OR capability l Non-volatile storage with back-up batteries SRM20V100LLTX 7 TSOP ( I )-32pin (plastic) SRM20V100LLRX 7 TSOP ( I )-32pin-R1 (plastic) SRM20V100LLKX 7 Slim-TSOP ( I )-32pin (plastic) SRM20V100LLYX 7 Slim-TSOP ( I )-32pin-R1 (plastic) n BLOCK DIAGRAM ¡PIN DESCRIPTION Low Voltage Operation Products l Low Supply Voltage l Wide Temperature Range l Low Supply Current l Access Time 70ns (2.7V) l 131,072 Words×8-Bit Asynchronous n PIN CONFIGURATION

n ABSOLUTE MAXIMUM RATINGS n DC RECOMMENDED OPERATING CONDITIONS Supply voltage Input voltage Input/Output voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time VDD VI VI/O PD Topr Tstg Tsol –0.5 to 4.6 –0.5 to VDD +0.3 –0.5 to VDD +0.3 0.5 –25 to 85 –65 to 150 260°C, 10s (at lead) Parameter Symbol Ratings Unit (VSS = 0V) [ VI, VI/O (Min.) = –3.0V (Pulse width is 50ns) V V V W SS = 0V, Ta = –25 to 85°C) Parameter Input voltage Supply voltage Symbol Conditions VDD VSS VIH VIL [ If pulse width is less than 50ns, it is –3.0V Min. 2.7 2.2 –0.3 Typ. 3.0 Max. 3.6 V DD +0.3 0.4 V V V V Unit Parameter Symbol Conditions Unit Input leakage High level output voltage Low level output voltage Operating supply current Average operating current ILI VOH VOL IDDS IDDO µA mA V (VDD = 2.7 to 3.6V, VSS = 0V, Ta = –25 to 85°C) IDDA [ Typical values are measured at Ta=25°C and VDD =3.0V VI=0 to VDD CS1 = VIH or CS2 = VIL V µA mA Standby supply current IDDS1 IDDA1 CS1 = CS2‡VDD —0.2V or CS2≤0.2V VI = VIL, VIH II/O = 0mA, tcyc = Min. VI = VIL, VIH II/O = 0mA, tcyc = 1µs VI = VIL, VIH II/O = 0mA mA mA Min. Typ. [ Max. 2.4 VDD —0.2 LL SL 0.6 0.3 1.0 0.4 0.2 VDD ‡3V, IOH = –2.0mA IOH = –100µA VDD ‡3V, IOL = –2.0mA IOL = 100µA (f = 1MHz, Ta = 25°C) Parameter Symbol Address Capacitance Input Capacitance I/O Capacitance C ADD C I C I/O Min. Typ. Max. UnitConditions pF pF pF VADD =0V VI=0V VI/O=0V Output leakage I LO µACS1 = VIH or CS2 = VIL or WE = VIL or OE = VIH, VIO = 0 to VDD –1 — 1 n ELECTRICAL CHARACTERISTICS l DC Electrical Characteristics l Terminal Capacitance

Min. Max. Parameter Symbol Conditions DD = 2.7V to 3.6V, VSS = 0V, Ta = –25 to 85°C) Read cycle time Address access time Chip select1 access time Chip select2 access time Output enable access time Chip select1 output set time Chip select1 output floating Chip select2 output set time Chip select2 output floating Output enable output set time Output enable output floating Output hold time t RC tACC tACS1 tACS2 tOE tCLZ1 tCHZ1 tCLZ2 tCHZ2 tOLZ tOHZ tOH [ 1 [ 2 [ 1 Unit ns ns ns ns ns ns ns ns ns ns ns Min. Max. Parameter Symbol Conditions DD = 2.7V to 3.6V, VSS = 0V, Ta = –25 to 85°C) Write cycle time Chip select time1 Chip select time2 Address enable time Address setup time Write pulse width Address hold time Input data setup time Input data hold time WE Output floating WE Output setup time t WC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW [ 1 [ 2 +3V 1.0kΩ 920ΩC L I/O C L=5pF (Includes Jig Capacitance) +3V 1.0kΩ 920ΩC L I/O C L=100pF (Includes Jig Capacitance) [1 Test Conditions 1. Input pulse level: 0.4V to 2.4V 2. tr = tf = 5ns 3. Input and output timing reference levels : 1.5V 4. Output load CL = 100pF [2 Test Conditions 1. Input pulse level : 0.4V to 2.4V 2. tr = tf = 5ns 3. Input timing reference levels: 1.5V 4. Output timing reference levels: ±200mV (the level displaced from stable output voltage level) 5. Output load CL = 5pF l AC Electrical Characteristics m Read Cycle m Write Cycle

Note : 1. During read cycle time, WE is to be "H" level. 2. During write cycle time that is controlled by CS1 or CS2, Output Buffer is in high impedance state, whether OE level is "H" or "L". 3. During write cycle time that is controlled by WE, Output Buffer is high impedance state if OE is "H" level. 4. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals. m Write Cycle (3) (WE Control)[ 3, [ 4 Address CS1 CS2 WE Dout Din tWC tAW tWP tDW tWR tAS tWHZ tOW tDH m Write Cycle (2) (CS2 Control)[ 2 Address CS1 CS2 WE Dout Din tWC tAW tWP tCW2 tCLZ2 tWHZ tDW tWRtAS tDH m Read Cylcle[ 1 Address CS1 CS2 OE Dout m Write Cycle (1) (CS1 Control)[ 2 Address CS1 CS2 WE Dout Din tWC tAW tWR tCW1 tWHZ tCLZ1 tDW tWR tAS tDH tOH tCHZ1 tACS2 tCLZ2 tCHZ2 tOE tOHZ tOLZ tRC tACC tACS1 tCLZ1 l Timing chart [ when retaining data in standby mode, supply voltage can be lowered with in a certain range. But read or write cycle cannot be performed while the supply voltage is low. l DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY Parameter Symbol Conditions Min. Typ. Max. Unit Data retention Supply voltage Data retention current Chip select data hold time VDDR IDDR tCDR 2.0 3.6 V ns (VSS = 0V, Ta = –25 to 85°C) 5Operation recovery time t R ms VDD = 2.7V CS1 = CS2‡VDD —0.2V or CS2≤0.2V [ Ta = 25°C 0.5[—LL 250.25[—SL µA VDD CS2 tCDR tR VIL VIL VDDR ‡2.0V CS2 ‡0.2V Data hold mode Data retention timing (CS1 Control) 2.7V 2.7VVDD CS1 tCDR VIH tR VIH VDDR ‡2.0V CS1 ‡VDD —0.2V Data hold mode 2.7V 2.7V Data retention timing (CS2 Control)

Data is able to be read when the address is set while holding CS1 = "L", CS2 = "H", OE = "L" and WE = "H". Since DATA I/O terminals are in high impedance state when OE = "H", the data bus line can be used for any other objective, then access time apparently is able to be cut down. l Writing data There are the following four ways of writing data into the memory. (1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1. (2) Hold CS1 = "L", WE = "L" ,set addresses and give "H"pulse to CS2. (3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE. (4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2. Anyway, data on the Data I/O terminals are latched up into the SRM20V100LLMX 7 at the end of the period that CS1, WE are "L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of CS1, OE = "H", or CS2 = "L", the contention on the data bus can be avoided. l Standby mode When CS1 is "H" or CS2 is "L" level, the SRM20V100LLMX7 is in the standby mode which has retaining data operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or "L". When CS1 and CS2 level are in the range over V DD -0.2V, CS2 level is in the range under 0.2V, in the SRM20V100LLMX 7 there is almost no current flow except through the high resistance parts of the memory. n FUNCTIONS l Truth Table X : "H" or "L" H X L L L CS1 X L H H H CS2 X X X L H X X L H H OE WE DATA I/O I DDMode IDDS , IDDS1 IDDS , IDDS1 IDDO IDDO IDDO Hi-Z Hi-Z Input data Output data Hi-Z Unselected Unselected Write Read Output disable

Unit : mm (inch) Plastic SOP6-32pin 1732 161 1.27 (0.05) 20.45–0.1 (0.805 ) 11.295–0.1 (0.445 ) +0.003 –0.004 0.4–0.1 (0.016 ) +0.003 –0.004 3.1max (0.122max ) +0.004 –0.003 0.2 (0.008) 1.42 (0.056) 0.15–0.05 (0.006 ) +0.001 –0.002 20.85max (0.82max ) 14.135–0.3 (0.556 ) +0.012 –0.011 2.7–0.1 (0.106 ) +0.004 –0.003 0.8–0.2 (0.031 ) +0.008 –0.007 Plastic TSOP ( I ) -32pin Unit : mm (inch) 321 1716 INDEX 18.4–0.2 (0.724 ) +0.008 –0.007 10° 8–0.2 (0.315–0.007) 20–0.2 (0.787 ) +0.008 –0.007 0.5–0.1 (0.02 ) +0.003 –0.004 0.15 (0.006 ) +0.002 –0.003 0.5 (0.02) 1.27max (0.05max ) 0.2–0.1 (0.008 ) +0.003 –0.004 1 (0.039)+0.07 –0.075 0.8–0.2 (0.031 ) +0.008 –0.007 Unit : mm (inch) Plastic Slim-TSOP ( I ) -32pin Plastic TSOP ( I ) -32pin-R1 Unit : mm (inch) Unit : mm (inch) Plastic Slim-TSOP ( I ) -32pin-R1 1716 321 18.4–0.2 (0.724 ) +0.008 –0.007 10° 8–0.2 (0.315–0.007) 20–0.2 (0.787 ) +0.008 –0.007 0.5–0.1 (0.02 ) +0.003 –0.004 0.15 (0.006 ) +0.002 –0.003 0.5 (0.02) 1.27max (0.05max ) 0.2–0.1 (0.008 ) +0.003 –0.004 1 (0.039)+0.07 –0.075 0.8–0.2 (0.031 ) +0.008 –0.007 INDEX 321 1716 INDEX 11.8–0.1 (0.465–0.003) 10° 8–0.2 (0.315–0.007) 13.4–0.3 (0.528–0.011) 0.5–0.1 (0.02 ) +0.003 –0.004 0.15 (0.006 ) +0.002 –0.003 0.5 (0.02) 1.27max (0.05max ) 0.2–0.1 (0.008 ) +0.003 –0.004 1 (0.039)+0.07 –0.075 0.8–0.2 (0.031 ) +0.008 –0.007 1716 321 11.8–0.1 (0.465–0.003) 10° 8–0.2 (0.315–0.007) 13.4–0.3 (0.528–0.011) 0.5–0.1 (0.02 ) +0.003 –0.004 0.15 (0.006 ) +0.002 –0.003 0.5 (0.02) 1.27max (0.05max ) 0.2–0.1 (0.008 ) +0.003 –0.004 1 (0.039)+0.07 –0.075 0.8–0.2 (0.031 ) +0.008 –0.007 INDEX

1.7 1.6 1.5 1.4 1.3 1.2 1.1 0.9 0.8 0.7 0.6 –40 –20 0 2 04 06 08 0 WRITE VDD = 3.0V READ, WRITE READ Ta (°C) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 20181614121086420 Frequency (MHz) 1/t RC , 1/tWC 1.6 1.5 1.4 1.3 1.2 1.1 0.9 0.8 0.7 0.6 V DD (V) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 0.5 1 1.5 2 2.5 3 3.5 V OH (V) Normalized IDDA — Ta Normalized IDDA — VDDNormalized IDDA — Frequency Normalized IDDS1 — VDD Normalized IOH — VOH 100 0.1 0.01 806040200–20–40 Ta (°C) 100 0.1 VDD (V) Normalized IDDS1— Ta VDD = 3.0V Ta = 25°C VDD = 3.0V WRITE READ Ta = 25°C Ta = 25°C READ, WRITE WRITE READ Ta = 25°C VDD = 3.0V

IC Marketing & Engineering Group 421–8 Hino, Hino–shi, Tokyo 191, JAPAN Phone: 0425–87–5816 FAX: 0425 –87–5624 International Marketing Department I (Europe & U. S. A.) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425–87–5812 FAX: 0425 –87–5564 International Marketing Department II (Asia) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425–87–5814 FAX: 0425 –87–5110 ELECTRONIC DEVICE MARKETING DEPARTMENT First issue Oct. 1995, printed Feb. 1997 in Japan T © Seiko Epson Corporation 1996 All right reserved. NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. SRM20V100LLMX 7 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 0 0.2 0.4 0.6 0.8 1 V OL (V) Normalized tACS1 — Ta tACC tACS2 Normalized tACS1 — VDD tACC tACS2 Normalized tACS1 — C L tACC tACS2 Normalized IDDR — Ta Normalized IOL — VOL 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 Ta (°C) 1.3 1.25 1.2 1.15 1.1 1.05 0.95 0.9 0.85 0.8 VDD (V) VDD = 3.0V Ta = 25°C Ta = 25°C VDD = 3.0V 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 0.9 0.8 0.7 0.6 0.5 0 100 200 300 400 C L (pF) 100 0.1 0.01 –40 –20 02 04 0 6 08 0 Ta (°C) Ta = 25°C VDD = 3.0V VDD =2.7V