SRK2000 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 19
Technical content
Datasheet sections
- 1 Internal block diagram
- 2 Pin description
- 3 Maximum ratings
- 4 Typical application sche matic
- 5 Electrical characteristics
- 6 Application information
- 6.1 EN pin - pin function and usage
- 6.1.1 Pull-up resistor configuration
- 6.1.2 Resistor divider configuration
- 6.1.3 Remote on/off control
- 6.2 Drain voltage sensing
- 6.3 Gate driving
- 6.4 Intelligent automatic sleep mode
- 6.5 Protection against current reversal
- 6.6 Layout guidelines
- 7 Package information
- 7.1 SO-8 package information
- 8 Revision history
Features
Secondary-side synchronous rectifier controller optimized for LLC resonant converters Protection against current reversal Safe management of load transient, light load and startup condition Intelligent automatic sleep mode at light load Dual gate driver for N-channel MOSFETs with 1 A source and 3.5 A sink drive current Operating voltage range 4.5 to 32 V Programmable UVLO with hysteresis 250 µA quiescent consumption Operating frequency up to 500 kHz Available in SO-8 package
Applications
All-in-one PC High-power AC-DC adapters 80+/85+ compliant ATX SMPS 90+/92+ compliant server SMPS Industrial SMPS
Description
The SRK2000 smart driver implements a control scheme specific to secondary-side synchronous rectification in LLC resonant converters that use a transformer with center-tap secondary winding for full-wave rectification. It provides two high current gate drive outputs, each capable of driving one or more N-channel Power MOSFETs. Each gate driver is controlled separately and an interlocking logic circuit prevents the two synchronous rectifier MOSFETs from conducting simultaneously. The control scheme in this IC allows for each synchronous rectifier to be switched on as the corresponding half-winding starts conducting and switched off as its current goes to zero. A unique feature of this IC is its intelligent automatic sleep mode. It allows the detection of a low-power operating condition for the converter and puts the IC into a low consumption sleep mode where gate driving is stopped and quiescent consumption is reduced. In this way, converter efficiency improves at light load, where synchronous rectification is no longer beneficial. The IC automatically exits sleep mode and restarts switching as it recognizes that the load for the converter has increased. A noticeable feature is the very low external component count required. SO-8 Table 1. Device summary
1 Internal block diagram
Figure 1. Internal block diagram
2 Pin description
Figure 2. Pin configuration Table 2. Pin description Drain voltage threshold setting for synchronous rectifier MOSFET turn-off. the proper routing of the drain connection is recommended. energy buffer for the pulsed gate drive currents.
5 GD2
Figure 3. Typical system block diagram
3 Maximum ratings
4 Typical application schematic
Figure 4. Typical application schematic Table 3. Absolute maximum ratings Table 4. Thermal data
5 Electrical characteristics
specified; typical values refer to TJ = 25 °C. Table 5. Electrical characteristics
- Parameters tracking each other.
- For V CC > 30 V IDVS1,2_b may be greater than 1 µA because of the possible current contribution of the
internal clamp Zener (few tens of µA). Table 5. Electrical characteristics (continued)
6 Application information
6.1 EN pin - pin function and usage
gate drivers and can be used as Enable (remote on/off control).
6.1.1 Pull-up resistor configuration
the setting is frozen as long as VCC is greater than the turn-off level VCCOff (4.25 V typ.). and R1 = 270 k in the second case, is suggested. Figure 5. EN pin biased with a pull-up resistor (for logic level MOSFET driving)
1.8 V: if this threshold is exceeded the gate drivers GD1 and GD2 are enabled and the SR
to VCC, therefore exceeding VEN_On and enabling the operation of both SR MOSFETs.
6.1.2 Resistor divider configuration
Figure 6. EN pin biased with a resistor divider to program the gate drive UVLO
Solving these equations for R1 and R2 we get: Equation 4 If VCC_G is not too low (< 8 ÷ 9 V), its tolerance is not critical because it is related only to that of VEN_On (± 5.6%) and of the external resistors R1, R2 (± 1% each is recommended). Then, some care needs to be taken only as far as the selection of the -12/-25 mV threshold is concerned: in fact, the large spread of I EN considerably affects the voltage on the EN pin as the device turns on, a value that can be found by solving the first of (1) for VEN: Equation 5 A couple of examples clarify the suggested calculation methodology. Example 1 VCC_G = 10 V, VDVS1,2_Off = - 25 mV. In this case, VEN must definitely be lower than the minimum value of VEN_Th (= 0.32 V). From the second of (2), the nominal ratio of R1 to R2 is (10 – 1.8) / 1.8 = 4.555. Substituting the appropriate extreme values in (3) it must be (4.75 - 7·10-6·R1) / (1 + 4.555) < 0.32; solving for R1 yields R1 > 425 k; let us consider an additional 4% margin to take both the tolerance and the granularity of the R1 and R2 values into account, so that: R1 > 425·1.04 = 442 k. Choose R1 = 442 k (E48 standard value) and, from the second of (2), R2 = 442/4.555 = 97 k; use 97.6 k (E48 standard value). Example 2 VCC_G = 10 V, VDVS1,2_Off = - 12 mV. In this case, VEN must definitely be higher than the maximum value of VEN_Th (= 0.40 V). From the second of (2), the nominal ratio of R1 to R2 is (10 – 1.8) / 1.8 = 4.555. Substituting the appropriate extreme values in (3) it must be (4.25 - 13·10-6·R1) / (1 + 4.555) > 0.4; solving for R1 yields R1 < 156 k; with 4% additional margin R1 < 156/1.04 = 150 k. Choose R1 = 147 k (E48 standard value) and, from the second of (2), R2 = 147/4.555 = 32.3 k; use 32.4 k (E48 standard value). Note: In both examples the gate drivers are disabled as V CC falls below 9.75 V (nominal value), as the voltage on the EN pin falls 45 mV below VEN_On.
6.1.3 Remote on/off control
Whichever configuration is used, since a voltage on the EN pin 45 mV below VEN_On disables the gate drivers, any small-signal transistor can be used to pull down the EN pin and force the gate drivers into an off state. Finally, it should be noted that during power-up, power-down, and under overload or short- circuit conditions, the gate drivers are shut down if the VCC voltage is insufficient: < VCCOff in On_ENG_CC On_EN EN On_EN G_CC ENCCOn VV V1R2R I V VVV 1R1 1RIVV ENCCOn EN
configuration (the coefficient 0.975 depends on the hysteresis on the Enable pin threshold).
6.2 Drain voltage sensing
a center-tap transformer winding for full-wave rectification. DVS1-2, able to sense the voltage level of the MOSFET drains. Figure 7. Typical waveform seen on the drain voltage sensing pins -25 mV by properly biasing the EN pin).
(-0.2 V typ.), an internal current source IDVS1,2_On is activated; as this current exceeds 50 µA, the gate of the MOSFET is turned on. Therefore, the actual triggering threshold can be determined by Equation 6. Equation 6 For instance, with RD = 2 k, the triggering threshold is located at To avoid false triggering of the gate driver, a debounce delay TPD_On (= 250 ns) is used after sourcing IDS1,2_On (i.e. the current sourced by the pin must exceed 50 µA for more than 250 ns before the gate driver is turned on). This delay is not critical for the converter’s efficiency because the initial current is close to zero or anyway much lower than the peak value. Once the SR MOSFET has been switched on, its drain-to-source voltage drops to a value given by the flowing current times the MOSFET RDS(on). Again, since the initial current is low, the voltage drop across the RDS(on) may exceed the turn-off threshold VDVS1,2_Off, and determine an improper turn-off. To prevent this, the state machine enables the turn-off comparator referenced to VDVS1,2_Off only in the second half of the conduction cycle, based on the information of the duration of the previous cycle. In the first half of the conduction cycle only an additional comparator, referenced to zero, is active to prevent the current of the SR MOSFET from reversing, which would impair the operation of the LLC converter. Once the threshold VDVS1,2_Off is crossed (in the second half of the conduction cycle) and the GATE is turned off, the current again flows through the body diode causing the drain-to- source voltage to have a negative jump, going again below V TH-ON. The interlock logic, however, prevents a false turn-on. It is worth pointing out that, due to the fact that each MOSFET is turned on after its body diode starts conducting, the ON transition happens with the drain-source voltage equal to the body diode forward drop; therefore there is neither a Miller effect nor switching losses at MOSFET turn-on. Also at turn-off the switching losses are not present, in fact, the current is always flowing from source to drain and, when the MOSFET is switched off, it goes on flowing through the body diode (or the external diode in parallel to the MOSFET). Unlike at turn-on, the turn-off speed is critical to avoid current reversal on the secondary side, especially when the converter operates above the resonance frequency, where the current flowing through the MOSFET exhibits a very steep edge while decreasing down to zero: the turn-off propagation T PD_Off delay has a maximum value of 60 ns. The interlock logic, in addition to checking for consistent secondary voltage waveforms (one MOSFET can be turned on only if the other one has a positive drain-to-source voltage > VDVS1,2_A) to prevent simultaneous conduction, allows only one switching per cycle: after one gate driver has been turned off, it cannot be turned on again before the other gate drive has had its own on/off cycle. The IC logic also prevents unbalanced current in the two SR MOSFETs: if one SR MOSFET fails to turn on in one cycle, the other SR MOSFET is also not turned on in the next cycle. TH_2,1DVSOn2,1DVSDONTH VIRV
Figure 8. Typical connection of the SRK2000 to the SR MOSFET
6.3 Gate driving
excessive voltage levels on the gate in case the device is supplied with a high VCC. level at VCC below the turn-on threshold.
6.4 Intelligent auto matic sleep mode
lower than the power losses in the MOSFETs and those related to their driving. the moment the body diode ceases to conduct (drain-to-source voltage going over VTH-ON).
erroneous decisions, the sleep mode condition must be confirmed on at least one of the two sections for 16 consecutive switching cycles of the resonant converter. Once in sleep mode, SR MOSFET gate driving is re-enabled when the conduction time of the body diode (or the external diodes in parallel to the MOSFET) exceeds 60% (DON) of the switching cycles. Also in this case the decision is made considering the measurement on 8 consecutive switching cycles (i.e. 8 consecutive cycles for each SR MOSFET of the center- tap). Furthermore, after each sleep mode entering/exiting transition, the timing is ignored for a certain number of cycles, to let the resulting transient in the output current fade out. The number of ignored resonant converter switching cycles is 128 after entering sleep mode and 256 after exiting sleep mode. If by the end of the ignored cycles the condition to enter or exit the sleep mode is already met for the required number of cycles, the state will be changed immediately; otherwise the controller (after the ignored cycles) will wait until that condition is satisfied.
6.5 Protection against current reversal
The IC provides protection against SR MOSFET current reversal. If a current reversal condition is detected for two consecutive switching cycles, the IC goes into sleep mode, avoiding the turn-on of the SR MOSFETs until a safe condition is restored.
6.6 Layout guidelines
The IC is designed with two grounds, SGND and PGND. SGND is used as the ground reference for all the internal high-precision analog blocks, while PGND is the ground reference for all the noisy digital blocks, as well as the current return for the gate drivers. In addition, it is also the ground for the ESD protection circuits. SGND is protected by ESD events versus PGND through two anti-parallel diodes. When laying out the PCB, make sure to keep the source terminals of both SR MOSFETs as close as possible to one another and to route the trace that goes to PGND separately from the load current return path. This trace should be as short as possible and be as close to the physical source terminals as possible. A layout that is as geometrically symmetrical as possible helps the circuit to operate in the most electrically symmetrical way as possible. SGND should be directly connected to PGND using a path as short as possible (under the device body). Also drain voltage sensing should be performed as physically close to the drain terminals as possible: any stray inductance crossed by the load current that is in the drain-to-source voltage sensing circuit may significantly alter the current reading, leading to a premature turn-off of the SR MOSFET. It is worth mentioning that, especially in higher power applications or at higher operating frequencies, even the stray inductance of the internal wire bonding can be detrimental. In this case, a cautious selection of the SR MOSFET package is required. The use of bypass capacitors between V CC and both SGND and PGND is recommended. They should be low-ESR, low-ESL types and located as close to the IC pins as possible. Sometimes a series resistor (in the tens) between the converter's output voltage and the V CC pin, forming an RC filter along with the bypass capacitor, is useful in order to get a cleaner VCC voltage.
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
7.1 SO-8 package information
Figure 9. SO-8 package outline Table 6. SO-8 package mechanical data
- D dimensions do not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
should not exceed 0.15 mm (0.006 inch) in total (both sides).
8 Revision history
Table 7. Document revision history 10-Aug-2010 1 Initial release. Added Chapter 6.5: Protection against current reversal. Document status promoted from preliminary data to datasheet. Updated Figure 3 added L6699 device). Minor corrections throughout document. 04-May-2017 4 Updated text in Section 6.4 on page 14. Minor modifications throughout document.