SRI2K STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 AC1, AC0
- 3 Data transfer
- 3.1 Input data transfer from the reader to the SRI2K (request frame)
- 3.1.1 Character transmission format for request frame
- 3.1.2 Request start of frame
- 3.1.3 Request end of frame
- 3.2 Output data transfer from the SRI2K to the reader (answer frame)
- 3.2.1 Character transmission format for answer frame
- 3.2.2 Answer start of frame
- 3.2.3 Answer end of frame
- 3.3 Transmission frame
- 3.4 CRC
- 4 Memory mapping
- 4.1 Resettable OTP area
- 4.3 EEPROM area
- 4.4 System area
- 4.4.1 OTP_Lock_Reg
- 4.4.2 Fixed Chip_ID (Option)
- 5 SRI2K operation
- 6 SRI2K states
- 6.1 Power-off state
- 6.2 Ready state
- 6.3 Inventory state
- 6.4 Selected state
- 6.5 Deselected state
Features
■ ISO 14443-2 Type B air interface compliant ■ ISO 14443-3 Type B frame format compliant ■ 13.56 MHz carrier frequency ■ 847 kHz subcarrier frequency ■ 106 Kbit/second data transfer ■ 8 bit Chip_ID based anticollision system ■ 2 count-down binary counters with automated antitearing protection ■ 64-bit Unique Identifier ■ 2048-bit EEPROM with Write Protect feature ■ Read_block and Write_block (32 bits) ■ Internal tuning capacitor ■ 1million erase/write cycles ■ 40-year data retention ■ Self-timed programming cycle ■ 5 ms typical programming time –U n s a w n w a f e r – Bumped and sawn wafer
1 Description
SRI2K and the reader is 106 kbit/s in both reception and emission modes. Figure 1. Logic diagram coupler, CRX14, it is easy to design a reader and build a contactless system. Table 1. Signal names
2 Kbit
- Read_block
- Write_block
- Initiate
- Pcall16
- Slot_marker
- Select
- Completion
- Reset_to_inventory
- Get_UID The SRI2K memory is organized in three areas, as described in Figure 3. The first area is a resettable OTP (one time programmable) area in which bits can only be switched from 1 to 0. Using a special command, it is possible to erase all bits of this area to 1. The second area provides two 32-bit binary counters which can only be decremented from FFFF FFFFh to 0000 0000h, and gives a capacity of 4,294,967,296 units per counter. The last area is the EEPROM memory. It is accessible by block of 32 bits and includes an auto-erase cycle during each Write_block command.
Figure 2. Die floor plan
2 Signal description
2.1 AC1, AC0
The pads for the Antenna Coil. AC1 and AC0 must be directly bonded to the antenna.
3 Data transfer
3.1 Input data transfer from th e reader to the SRI2K (request
represented in Figure 3. The data transfer rate is 106 Kbits/s. Figure 3. 10% ASK modulation of the received wave
3.1.1 Character transmission format for request frame
unit), is equal to 9.44 µs (1/106 kHz). command, but it does not generate an error frame. Figure 4. SRI2K request frame character format
1 ETU
3.1.2 Request start of frame
- one falling edge,
- followed by 10 ETUs at logic-0,
- followed by a single rising edge,
- followed by at least 2 ETUs (and at most 3) at logic-1.
Figure 5. Request start of frame
3.1.3 Request end of frame
- one falling edge,
- followed by 10 ETUs at logic-0,
- followed by a single rising edge.
Figure 6. Request end of frame Table 2. Bit description
3.2 Output data transfer from the SRI2K to the reader (answer
s as shown in Figure 7, and as specified in the ISO 14443-2 Type B Standard. Figure 7. Wave transmitted using BPSK subcarrier modulation
3.2.1 Character transmission format for answer frame
3.2.2 Answer start of frame
- followed by 10 ETUs at logic-0
- followed by 2 ETUs at logic-1
Figure 8. Answer start of frame
3.2.3 Answer end of frame
- followed by 10 ETUs at logic-0,
- followed by 2 ETUs at logic-1.
Figure 9. Answer end of frame
3.3 Transmission frame
the reader waits a minimum time, t2, before sending a new request frame to the SRI2K. Figure 10. Example of a complete transmission frame
3.4 CRC
The two-byte CRC is present in every request and in every answer frame, before the EOF . The CRC is calculated on all the bytes between SOF (not included) and the CRC field. it is invalid, the SRI2K discards the frame and does not answer the reader. CRC. In case of error, the actions to be taken are the reader designer’s responsibility. the least significant bit first. Figure 11. CRC tr ansmission rules
4 Memory mapping
The SRI2K is organized as 64 blocks of 32 bits as shown in Table 3. All blocks are accessible by the Read_block command. Depending on the write access, they can be updated by the Write_block command. A Write_block updates all the 32 bits of the block. Table 3. SRI2K memory mapping
Description
5 32 bits binary counter Count down counter6 32 bits binary counter 7U s e r a r e a Lockable EEPROM 8U s e r a r e a 9U s e r a r e a
10 User area
11 User area
12 User area
13 User area
14 User area
15 User area
16 User area
EEPROM... User area
63 User area
255 OTP_Lock_Reg ST Reserved Fixed Chip_ID
(Option) System OTP bits UID0 64 bits UID area ROM UID1
4.1 Resettable OTP area
In this area contains five individual 32-bit Boolean words (see Figure 12 for a map of the area). A Write_block command will not erase the previous contents of the block as the write cycle is not preceded by an auto-erase cycle. This feature can be used to reset selected bits from 1 to 0. All bits previously at 0 remain unchanged. When the 32 bits of a block are all at 0, the block is empty, and cannot be updated any more. See Figure 13 and Figure 14 for examples of the result of the Write_block command in the resettable OTP area. Figure 12. Resettable OTP area (addresses 0 to 4) Figure 13. Write_block update in Standard mode (binary format) bit binary counters” for details). Figure 14. Write_block update in Reload mode (binary format) 1 ... 1 1 01011 11 1 0 11 1 ... 1 0 01011 00 1 1 11 1 ... 1 0 01011 00 1 0 11 Previous data stored in block Data to be written New data stored in block b31 b0 ai07659 1 . . .11 0 1011 11 1 0 11 1 . . .11 1 1011 00 1 1 11 1 ... 1 1 1 1011 00 1 1 11 Previous data stored in block Data to be written New data stored in block b31 b0
4.3 EEPROM area
The 57 blocks between addresses 7 and 63 are EEPROM blocks of 32 bits each (228 bytes in total). (See Figure 17 for a map of the area.) These blocks can be accessed using the Read_block and Write_block commands. The Write_block command for the EEPROM area always includes an auto-erase cycle prior to the write cycle. Blocks 7 to 15 can be write-protected. Write access is controlled by the 8 bits of the OTP_Lock_Reg located at block address 255 (see “OTP_Lock_Reg” for details). Once protected, these blocks (7 to 15) cannot be unprotected. Figure 17. EEPROM (addresses 7 to 63)
4.4 System area
OTP_Lock_Reg, Fixed Chip_ID and ST Reserved. See Figure 18 for a map of this area. block are at 0, the block is empty and cannot be updated any more. ... User area User area User area User area User area 127 User area User area EEPROM Block Address MSb b31 32-bit Block b16 b15b24 b23b 8 b7 LSb ... User Area User Area User Area User Area User Area User Area User Area EEPROM
Figure 18. System area
4.4.1 OTP_Lock_Reg
- When b24 is at 0, blocks 7 and 8 are write-protected
- When b25 is at 0, block 9 is write-protected
- When b26 is at 0, block 10 is write-protected
- When b27 is at 0, block 11 is write-protected
- When b28 is at 0, block 12 is write-protected
- When b29 is at 0, block 13 is write-protected
- When b30 is at 0, block 14 is write-protected
- When b31 is at 0, block 15 is write-protected. The OTP_Lock_Reg bits cannot be erased. Once write-protected, EEPROM blocks behave like ROM blocks and cannot be unprotected.
4.4.2 Fixed Chip_ID (Option)
the SRI2K. This is a very flexible feature, however the searching loop requires time to run. area. When the fixed Chip_ID option is used, the random Chip_ID function is disabled. OTPOTP_Lock_Reg ST reserved Fixed Chip_ID (Option) ai07663b
5 SRI2K operation
All commands, data and CRC are transmitted to the SRI2K as 10-bit characters using ASK modulation. The start bit of the 10 bits, b0, is sent first. The command frame received by the SRI2K at the antenna is demodulated by the 10% ASK demodulator, and decoded by the internal logic. Prior to any operation, the SRI2K must have been selected by a Select command. Each frame transmitted to the SRI2K must start with a start of frame, followed by one or more data characters, two CRC bytes and the final end of frame. When an invalid frame is decoded by the SRI2K (wrong command or CRC error), the memory does not return any error code. When a valid frame is received, the SRI2K may have to return data to the reader. In this case, data is returned using BPSK encoding, in the form of 10-bit characters framed by an SOF and an EOF . The transfer is ended by the SRI2K sending the 2 CRC bytes and the EOF .
6 SRI2K states
The SRI2K can be switched into different states. Depending on the current state of the SRI2K, its logic will only answer to specific commands. These states are mainly used during the anticollision sequence, to identify and to access the SRI2K in a very short time. The SRI2K provides 6 different states, as described in the following paragraphs and in Figure 19.
6.1 Power-off state
The SRI2K is in Power-off state when the electromagnetic field around the tag is not strong enough. In this state, the SRI2K does not respond to any command.
6.2 Ready state
When the electromagnetic field is strong enough, the SRI2K enters the Ready state. After Power-up, the Chip_ID is initialized with a random value. The whole logic is reset and remains in this state until an Initiate() command is issued. Any other command will be ignored by the SRI2K.
6.3 Inventory state
The SRI2K switches from the Ready to the Inventory state after an Initiate() command has been issued. In Inventory state, the SRI2K will respond to any anticollision commands: Initiate(), Pcall16() and Slot_marker(), and then remain in the Inventory state. It will switch to the Selected state after a Select(Chip_ID) command is issued, if the Chip_ID in the command matches its own. If not, it will remain in Inventory state.
6.4 Selected state
In Selected state, the SRI2K is active and responds to all Read_block(), Write_block() and Get_UID() commands. When an SRI2K has entered the Selected state, it no longer responds to anticollision commands. So that the reader can access another tag, the SRI2K can be switched to the Deselected state by sending a Select(Chip_ID2) with a Chip_ID that does not match its own, or it can be placed in Deactivated state by issuing a Completion() command. Only one SRI2K can be in Selected state at a time.
6.5 Deselected state
Once the SRI2K is in Deselected state, only a Select(Chip_ID) command with a Chip_ID matching its own can switch it back to Selected state. All other commands are ignored.
6.6 Deactivated state
When in this state, the SRI2K can only be turned off. All commands are ignored.
Figure 19. State transition diagram
7 Anticollision
- Initiate()
- Pcall16()
- Slot_marker(). The reader is the master of the communication with one or more SRI2K device(s). It initiates the tag communication activity by issuing an Initiate(), Pcall16() or Slot_marker() command to prompt the SRI2K to answer. During the anticollision sequence, it might happen that two or more SRI2K devices respond simultaneously, so causing a collision. The command set allows the reader to handle the sequence, to separate SRI2K transmissions into different time slots. Once the anticollision sequence has completed, SRI2K communication is fully under the control of the reader, allowing only one SRI2K to transmit at a time. The Anticollision scheme is based on the definition of time slots during which the SRI2K devices are invited to answer with minimum identification data: the Chip_ID. The number of slots is fixed at 16 for the Pcall16() command. For the Initiate() command, there is no slot and the SRI2K answers after the command is issued. SRI2K devices are allowed to answer only once during the anticollision sequence. Consequently, even if there are several SRI2K devices present in the reader field, there will probably be a slot in which only one SRI2K answers, allowing the reader to capture its Chip_ID. Using the Chip_ID, the reader can then establish a communication channel with the identified SRI2K. The purpose of the anticollision sequence is to allow the reader to select one SRI2K at a time. The SRI2K is given an 8-bit Chip_ID value used by the reader to select only one among up to 256 tags present within its field range. The Chip_ID is initialized with a random value during the Ready state, or after an Initiate() command in the Inventory state. The four least significant bits ( b0 to b3) of the Chip_ID are also known as the Chip_slot_number. This 4-bit value is used by the Pcall16() and Slot_marker() commands during the anticollision sequence in the Inventory state.
Figure 20. SRI2K Chip_ID description anticollision slot numbers from 1 to 15.
Figure 21. Description of a possible anticollision sequence
- The value X in the answer Chip_ID means a random hexadecimal character from 0 to F.
7.1 Description of an anticollision sequence
Initiate() command and entered the Inventory state. anticollision sequence can stop when all SRI2K devices have been identified. Table 4. Standard anticollision sequence – If no answer is detected, go to step1. SRI2K, deselect the tag and go to step1. – If a collision (many answers) is detected, go to step2. – If no answer or collision is detected, go to step3. – If 1 answer is detected, store the Ch ip_ID, Send Select() and go to step3. – If no answer or collision is detected, go to step4. – If 1 answer is detected, store the Ch ip_ID, Send Select() and go to step4. – If no answer or collision is detected, go to step5. – If 1 answer is detected, store the Ch ip_ID, Send Select() and go to step5. Send Slot_marker(3 up to 14)... – If no answer or collision is detected, go to stepN+1. – If 1 answer is detected, store the Chi p_ID, Send Select() and go to stepN+1. – If no answer or collision is detected, go to step18. – If 1 answer is detected, store the Ch ip_ID, Send Select() and go to step18. Deselected or Deactivated state, depending on the application needs. – If collisions were detected between Step2 and Step17, go to Step2. – If no collision was detected between Step2 and Step17, go to Step1.
Figure 22. Example of an anticollision sequence Each tag get a new random Chip_ID.
8 SRI2K commands
Table 5. Command code
8.1 Initiate() command
search process. The Chip_slot_number is not used during Initiate() command access. Figure 23. Initiate request format
- No parameter
Figure 24. Initiate response format
- Chip_ID of the SRI2K
Figure 25. Initiate frame exchange between reader and SRI2K
8.2 Pcall16() command
The SRI2K must be in Inventory state to interpret the Pcall16() command. value. If not, the SRI2K does not send any response. present in the reader field range. Figure 26. Pcall16 request format
- No parameter
Figure 27. Pcall16 response format
- Chip_ID of the SRI2K
Figure 28. Pcall16 frame exchange between reader and SRI2K
8.3 Slot_marker(SN) command
The SRI2K must be in Inventory state to interpret the Slot_marker(SN) command.
- b3 to b0: 4-bit command code with fixed value 6.
- b7 to b4: 4 bits known as the Slot_number (SN). They assume a value between 1 and 15. The value 0 is reserved by the Pcall16() command. On receiving the Slot_marker() command, the SRI2K compares its Chip_slot_number value with the Slot_number value given in the command code. If they match, the SRI2K returns its Chip_ID value. If not, the SRI2K does not send any response. The Slot_marker() command, used together with the Pcall16() command, allows the reader to search for all the Chip_IDs when there are more than one SRI2K device in Inventory state present in the reader field range.
Figure 29. Slot_marker request format
- x: Slot number
Figure 30. Slot_marker response format
- Chip_ID of the SRI2K
Figure 31. Slot_marker frame exchange between reader and SRI2K
8.4 Select(Chip_ID) command
own is automatically switched to Deselected state. Figure 32. Select request format
- 8-bit Chip_ID stored during the anticollision sequence
Figure 33. Select response format
- Chip_ID of the selected tag. Must be equal to the transmitted Chip_ID
Figure 34. Select frame exchange between reader and SRI2K
8.5 Completion() command
Completion() command does not generate a response. All SRI2K devices not in Selected state ignore the Completion() command. Figure 35. Completion request format
- No parameter
Figure 36. Completion response format Figure 37. Completion frame exchange between reader and SRI2K
8.6 Reset_to_inventory() command
The Reset_to_inventory() command does not generate a response. All SRI2K devices that are not in Selected state ignore the Reset_to_inventory() command. Figure 38. Reset_to_inventory request format
- No parameter
Figure 39. Reset_to_inventory response format Figure 40. Reset_to_inventory frame exchange between reader and SRI2K
8.7 Read_block(Addr) command
first and each byte is transmitted with the least significant bit first. The address byte gives access to the 64 blocks of the SRI2K (addresses 0 to 63). the SRI2K before a Select() command is issued are ignored. Figure 41. Read_block request format
- Address: block addresses from 0 to 63, or 255
Figure 42. Read_block response format
- Data 1: Less significant data byte
- Data 2: Data byte
- Data 3: Data byte
- Data 4: Most significant data byte
Figure 43. Read_block frame exchange between reader and SRI2K
8.8 Write_block (Addr, Data) command
transmitted with the least significant bit first. The address byte gives access to the 64 blocks of the SRI2K (addresses 0 to 63). SRI2K will not return any response, except for the System area located at address 255.
- Figure 12: Resettable OTP area (addresses 0 to 4).
- Figure 15: Binary counter (addresses 5 to 6).
- Figure 17: EEPROM (addresses 7 to 63). The Write_block command does not give rise to a response from the SRI2K. The reader must check after the programming time, tW, that the data was correctly programmed. The SRI2K must have received a Select() command and be switched to Selected state before any Write_block command can be accepted. All Write_block commands sent to the SRI2K before a Select() command is issued, are ignored.
Figure 44. Write_block request format
- Request parameters:
- Address: block addresses from 0 to 63, or 255
- Data 1: Less significant data byte
- Data 2: Data byte
- Data 3: Data byte
- Data 4: Most significant data byte.
Figure 45. Write_block response format
Figure 46. Write_block frame exchange between reader and SRI2K
8.9 Get_UID() command
SRI2K before a Select() command is issued, are ignored. Figure 47. Get_UID request format
- No parameter
Figure 48. Get_UID response format
- UID 0: Less significant UID byte
- UID 1 to UID 6: UID bytes
- UID 7: Most significant UID byte. DATA ai15588 DATA DATA DATA 4Reader SRI2K CRCL CRCH EOFSOF 09h ADDR No Response SOF Get_UID CRC L CRCH EOF AI07693b 0Bh 8 bits 8 bits SOF UID 1 CRC L CRCH EOF AI07694 8 bits UID 2 UID 3 UID 4 8 bIts 8 bIts 8 bIts 8 bIts 8 bIts UID 0 UID 5 8 bIts UID 6 8 bIts8 bits UID 7 8 bIts
- an 8-bit prefix, with the most significant bits set to D0h
- an 8-bit IC manufacturer code (ISO/IEC 7816-6/AM1) set to 02h (for STMicroelectronics)
- a 6-bit IC code set to 00 1111b = 15d for SRI2K
- a 42-bit unique serial number
Figure 49. 64-bit unique identifier of the SRI2K Figure 50. Get_UID frame exchange between reader and SRI2K
8.10 Power-on state
- It is in the low-power state.
- It is in Ready state.
- It shows highest impedance with respect to the reader antenna field.
- It will not respond to any command except Initiate(). ai15579 D0h Unique Serial Number02h 63 55 47 0 Most significant bits Least significant bits 15d S O F CRCLCRCH E O F ai15589 Reader SRI2K <-t0-> <-t1-> S O F CRCL CRCH E O F 0Bh UID UID UID UID UID UID UID UID
9 Maximum rating
Program and other relevant quality documents. Table 6. Absolute maximum ratings
10 DC and ac parameters
Table 7. Operating conditions Table 8. DC characteristics Table 9. AC characteristics (1)
- All timing measurements were performed on a reference antenna with the following characteristics:
Figure 51. SRI2K synchronous timing, transmit and receive
11 Part numbering
Note: Devices are shipped from the factory with the memory content bits erased to 1. of this device, please contact your nearest ST sales office. Table 10. Ordering information scheme
SRI2K ISO-14443 Type B CRC calculation Doc ID 15779 Rev 3 41/45 Appendix A ISO-14443 Type B CRC calculation #include <stdio.h> #include <stdlib.h> #include <string.h> #include <ctype.h> #define BYTE unsigned char #define USHORT unsigned short unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc) ch = (ch^(BYTE)((*lpwCrc) & 0x00FF)); ch = (ch^(ch<<4)); *lpwCrc = (*lpwCrc >> 8)^((USHORT)ch << 8)^((USHORT)ch<<3)^((USHORT)ch>>4); return(*lpwCrc); void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE *TransmitSecond) BYTE chBlock; USHORTt wCrc; wCrc = 0xFFFF; // ISO 3309 do chBlock = *Data++; UpdateCrc(chBlock, &wCrc); } while (--Length); wCrc = ~wCrc; // ISO 3309 *TransmitFirst = (BYTE) (wCrc & 0xFF); *TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF); return; int main(void) BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i; printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1”); printf("CRC_B of [ "); for(i=0; i<4; i++) printf("%02X ",BuffCRC_B[i]); ComputeCrc(BuffCRC_B, 4, &First, &Second); printf("] Transmitted: %02X then %02X.”, First, Second); return(0);
Table 11. Document revision history 01-Jun-2009 1 Initial release. 19-Oct-2009 2 Document promoted from Preliminary data to full datasheet status. Section 8.7: Read_block(Addr) command specified. 09-Sep-2011 3 Process technology removed from Section 1: ìDescription. Updated dislaimer on last page.