SRC4192-Q1

SRC4192-Q1 TI1 | Alldatasheet

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Technical content

AES, S/PDIF Output TX+ TX ± DIT4192 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community SRC4192-Q1 SLFS081A –OCTOBER 2015–REVISED NOVEMBER 2015 SRC4192-Q1192-kHzStereoAsynchronousSample-RateConverters

1 Features 2 Applications

1• Automatic Sensing of the Input-to-Output • Digital Audio Workstations Sampling Ratio • Audio Distribution and Broadcast Systems

• Wide Input-to-Output Sampling Range: 16:1 to • High-End A/V Receivers 1:16

3 Description• Supports Input and Output Sampling Rates Up to

212 kHz The SRC4192-Q1 device is an asynchronous, sample-rate converter designed for professional and• Dynamic Range: 144 dB (–60-dbFS Input, BW = broadcast audio applications. The SRC4192-Q120 Hz to fS/2, A-Weighted) device combines a wide input-to-output sampling ratio• THD+N: –140 dB (0-dbFS Input, BW = 20 Hz to with outstanding dynamic range and ultra-lowfS/2) distortion. Input and output serial ports support

• Attenuates Sampling and Reference Clock Jitter standard audio formats, as well as a Time Division Multiplexed (TDM) mode. Flexible audio interfaces• High-Performance, Linear-Phase Digital Filtering allow the SRC4192-Q1 device to connect to a widewith Stop Band Attenuation Greater than 140 dB range of audio data converters, digital audio receivers• Flexible Audio Serial Ports: and transmitters, and digital signal processors. – Master or Slave-Mode Operation The SRC4192-Q1 device is a standalone, pin-– Supports I2S, Left-Justified, Right-Justified, programmed device, with control pins for mode, data and TDM Data Formats format, mute, bypass, and low group-delay functions. – Supports 16-Bit, 18-Bit, 20-Bit, or 24-Bit Audio The SRC4192-Q1 device can operate from a singleData 3.3-V power supply. A separate digital I/O supply – TDM Mode Allows Daisy-Chaining of up to (VIO) operates over the 1.65-V to 3.6-V supply range, allowing greater flexibility when interfacing to currentEight Devices and future generation signal processors and logic• Low Group Delay Option for Interpolation Filter devices. The device is available in a 28-pin SSOP• Power Down Mode package.
• Operates From a Single 3.3-V Power Supply Device Information(1)
• Small 28-Pin SSOP Package PART NUMBER PACKAGE BODY SIZE (NOM)• Pin Compatible with the AD1896 SRC4192-Q1 SSOP (28) 5.30 mm × 10.20 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.

4 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLFS081A –OCTOBER 2015–REVISED NOVEMBER 2015 www.ti.com Table of Contents

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision Preview (October 2015) to Revision A Page

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6 Device Comparison Table

Part Number SNR (dB A-Weighted) Channel Count Control Interface Other Features SRC4184 128 4 SW (SPI) SRC4190 128 2 HW (Hardware) Q1 Version Available SRC4192 144 2 HW Q1 Version Available SRC4193 144 2 SW (SPI) (Software - SPI) SRC4194 144 4 SW (SPI) SRC4382 128 2 SW (SPI) / HW Integrated S/PDIF Transceiver SRC4392 144 2 SW (SPI) / HW Integrated S/PDIF Transceiver Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SRC4192-Q1

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7 Pin Configuration and Functions

NAME NO. BCKI 5 I Input port bit clock I/O BCKO 25 O Output port bit clock I/O BYPAS 9 I ASRC bypass control input (Active High) DGND – Digital ground IFMT0 10 I Input port data format control input IFMT1 11 I Input port data format control input IFMT2 12 I Input port data format control input LGRP 1 I Low group delay control input (active high) LRCKI 6 I Input port left/right word clock I/O LRCKO 24 O Output port left/right word clock I/O MODE0 26 I Serial port mode control input MODE1 27 I Serial port mode control input MODE2 28 I Serial port mode control input MUTE 14 I Output mute control input (active high) NC 3 – No connection OFMT0 19 I Output port data format control input OFMT1 18 I Output port data format control input OWL0 17 I Output port data word length control input OWL1 16 I Output port data word length control input RCKI 2 I Reference Clock Input RDY 15 O ASRC Ready Status Output (Active Low) RST 13 I Reset Input (Active Low) SDIN 4 I Audio Serial Data Input SDOUT 23 O Audio Serial Data Output TDMI 20 I TDM Data Input (Connect to DGND when not in use) VDD 22 I Digital Core Supply, 3.3 V VIO 7 I Digital I/O Supply, 1.65 V to VDD

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD –0.3 4 Supply Voltage V VIO –0.3 4 Digital Input Voltage –0.3 4 Operating Temperature –40 125 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

8.2 ESD Ratings

Human-body model (HBM), per AEC Q100-002(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per AEC Q100-011 ±1500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD 3 3.3 3.6 Supply voltage VIO 1.8 V 1.65 1.8 1.95 V VIO 3.3 V 3 3.3 3.6 Operating temperature –40 125 °C

8.4 Thermal Information

THERMAL METRIC(1) DB (SSOP) UNIT

28 PINS

RθJA Junction-to-ambient thermal resistance 78.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 39.3 °C/W ψJT Junction-to-top characterization parameter 7.1 °C/W ψJB Junction-to-board characterization parameter 38.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

All parameters specified with TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE(1) Resolution 24 Bits fSIN Input sampling frequency 4 212 kHz fSOUT Output sampling frequency 4 212 kHz (1) Dynamic performance measured with an Audio Precision System Two Cascade or Cascade Plus. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SRC4192-Q1

SLFS081A –OCTOBER 2015–REVISED NOVEMBER 2015 www.ti.com Electrical Characteristics (continued) All parameters specified with TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Upsampling 1:16Input: output sampling ratio Downsampling 16:1 44.1 kHz; 48 140kHz 48 kHz; 44.1 140kHz 48 kHz; 96 kHz 140 44.1 kHz; 192 138kHz BW = 20 Hz to fSOUT/2, –60-dBFS96 kHz; 48 kHz 141 InputDynamic range dB192 kHz; 12 fIN = 1 kHz, Unweighted (add 3 dB 141kHz to spec for A-weighted result) 192 kHz; 32 141kHz 192 kHz; 48 141kHz 32 kHz; 48 kHz 140 12 kHz; 192 138kHz 44.1 kHz; 48 –140kHz 48 kHz; 44.1 –140kHz 48 kHz; 96 kHz –140 44.1 kHz; 192 –137kHz 96 kHz; 48 kHz –140 Total harmonic BW = 20 Hz to fSOUT/2, 0-dBFS dB192 kHz; 12distortion + noise Input fIN = 1 kHz, Unweighted –140kHz 192 kHz; 32 –141kHz 192 kHz; 48 –141kHz 32 kHz; 48 kHz –140 12 kHz; 192 –137kHz Interchannel gain mismatch 0 dB Interchannel phase deviation 0 ° Mute attenuation 24-Bit Word Length, A-weighted –144 dB DIGITAL INTERPOLATION FILTER CHARACTERISTICS Passband 0.4535 × fSIN Hz Passband ripple ±0.007 dB 0.4535 ×Transition band 0.5465 × fSIN HzfSIN 0.5465 ×Stop band HzfSIN Stop band attenuation –144 dB 102.53125 /Decimation Filter On (DFLT = 0) fSINNormal group delay (LGRP = 0) s Decimation Filter Off (DFLT = 1) 102 / fSIN

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www.ti.com SLFS081A –OCTOBER 2015–REVISED NOVEMBER 2015 Electrical Characteristics (continued) All parameters specified with TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Decimation Filter On (DFLT = 0) 70.53125 / fSIN Low group delay (LGRP = 1) s Decimation Filter Off (DFLT = 1) 70 / fSIN DIGITAL DECIMATION FILTER CHARACTERISTICS 0.4535 ×Passband HzfSOUT Passband ripple ±0.008 dB 0.4535 × 0.5465 ×Transition band HzfSOUT fSOUT 0.5465 ×Stop band HzfSOUT Stop band attenuation –143 dB 36.46875 /Group delay – decimation filter sfSOUT DIGITAL I/O CHARACTERISTICS VIH High-level input voltage 0.7 × VIO VIO V VIL Low-level input voltage 0 0.3 × VIO V High-level input current (for pins IIH other than IFMT0, IFMT1, IFMT2, 0.5 10 µA OFMT0, OFMT1, OWL0) High-level input current for IFMT0, IIH IFMT1, IFMT2, OFMT0, OFMT1, 0.5 25 µA OWL0 (SRC4192 specific) IIL Low-level input current 0.5 10 µA VOH High-level output voltage IO = –4 mA 0.8 × VIO VIO V VOL Low-level output voltage IO = +4 mA 0 0.2 × VIO V CIN Input Capacitance 3 pF POWER SUPPLIES Operating voltage, VDD 3 3.3 3.6 V Operating voltage, VIO 1.65 3.3 3.6 V VDD = 3.3 V, VIO = 3.3 V, RST = 0,Supply current, IDD, power down 100 µANo Clocks VDD = 3.3 V, VIO = 3.3 V, fSIN =Supply current, IDD, dynamic 66 mAfSOUT = 192 kHz VDD = 3.3 V, VIO = 3.3 V, RST = 0,Supply current, IIO, power down 100 µANo Clocks VDD = 3.3 V, VIO = 3.3 V, fSIN =Supply current, IIO, dynamic 2 mAfSOUT = 192 kHz Total power dissipation, PD, power VDD = 3.3 V, VIO = 3.3 V, RST = 0, 660 µWdown No Clocks VDD = 3.3 V, VIO = 3.3 V, fSIN =Total power dissipation, PD, dynamic 225 mWfSOUT = 192 kHz

8.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE CLOCK TIMING fSMIN = min (fSIN, fSOUT), 128 ×RCKI frequency 50 MHzfSMAX = max (fSIN, fSOUT) fSMIN 1 / (128 ×tRCKIP RCKI period 20 nsfSMIN) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SRC4192-Q1

8.7 Typical Characteristics

At TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. Figure 1. FFT With 1-kHz Input Tone at 0 dBFS Figure 2. FFT With 1-kHz Input Tone at –60 dBFS

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At TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. Figure 9. FFT With 1-kHz Input Tone at 0 dBFS Figure 10. FFT With 1-kHz Input Tone at –60 dBFS Figure 11. FFT With 1-kHz Input Tone at 0 dBFS Figure 12. FFT With 1-kHz Input Tone at –60 dBFS Figure 13. FFT With 1-kHz Input Tone at 0 dBFS Figure 14. FFT With 1-kHz Input Tone at –60 dBFS

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At TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. Figure 21. FFT With 1-kHz Input Tone at 0 dBFS Figure 22. FFT With 1-kHz Input Tone at –60 dBFS Figure 23. FFT With 1-kHz Input Tone at 0 dBFS Figure 24. FFT With 1-kHz Input Tone at –60 dBFS Figure 25. FFT With 1-kHz Input Tone at 0 dBFS Figure 26. FFT With 1-kHz Input Tone at –60 dBFS

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At TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. Figure 33. FFT With 20-kHz Input Tone at 0 dBFS Figure 34. FFT With 20-kHz Input Tone at 0 dBFS Figure 35. FFT With 20-kHz Input Tone at 0 dBFS Figure 36. FFT With 20-kHz Input Tone at 0 dBFS Figure 37. FFT With 20-kHz Input Tone at 0 dBFS Figure 38. FFT With 80-kHz Input Tone at 0 dBFS

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At TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. Figure 45. THD+N vs Input Frequency, 0-dBFS Input Figure 46. THD+N vs Input Frequency, 0-dBFS Input Figure 47. THD+N vs Input Frequency, 0-dBFS Input Figure 48. THD+N vs Input Frequency, 0-dBFS Input Figure 49. Linearity With fIN = 200 Hz Figure 50. Linearity With fIN = 200 Hz

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At TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V, unless otherwise noted. Figure 57. Pass Band Ripple Figure 58. Pass Band Ripple

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9 Parameter Measurement Information

Dynamic performance can be measured with an Audio Precision System Two Cascade or Cascade Plus (or any newer Audio Precision product, along with the SRC4192EVM). (http://www.ti.com/tool/src4192evm). Schematics available from the SRC4190/92/93EVM - User Guide (SBAU088). Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: SRC4192-Q1

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10 Detailed Description

10.1 Overview

The SRC4192-Q1 device is an asynchronous, sample-rate converter (ASRC) designed for professional audio applications. Operation at input and output sampling frequencies up to 212 kHz is supported, with an input and output sampling ratio range of 16:1 to 1:16. Excellent dynamic range and Total Harmonic Distortion + Noise (THD+N) are achieved by employing high-performance, linear-phase digital filtering with image rejection better than 140 dB. Digital filtering options allow for lower group-delay processing. The digital filtering options include a low group-delay option for the interpolation and resampler function. The audio input and output ports support standard audio data formats, as well as a TDM interface mode. Word lengths of 24 bits, 20 bits, 18 bits, and 16 bits are supported. Both ports can operate in slave mode, deriving their word and bit clocks from external input and output devices. Alternatively, one port can operate in master mode while the other remains in slave mode. In master mode, the LRCK and BCK clocks are derived from the reference clock input, RCKI. The flexible configuration of the input and output ports allows connection to a wide variety of audio data converters, interface devices, digital signal processors, and programmable logic. A bypass mode is included, which allows audio data to be passed directly from the input port to the output port, bypassing the ASRC function. The bypass option is useful for passing through encoded or compressed audio data, or nonaudio control or status data. A soft mute function is available on the SRC4192-Q1 device. The soft mute function provides artifact-free operation, while allowing muting or level adjustment of the audio output signal. The mute attenuation is typically –144 dB, while the digital attenuation control is adjustable from 0 dB to –127.5 dB in 0.5-dB steps. The Functional Block Diagram shows a functional block diagram of the SRC4192-Q1 device. Audio data is received at the input port, clocked by either the audio data source in slave mode, or by the SRC4192-Q1 in master mode. The output-port data is also clocked by either the audio data source in slave mode, or by the SRC4192-Q1 in master mode. The input data is passed through interpolation filters which up-sample the data, which is then passed on to the resampler. The rate estimator compares the input and output sampling frequencies by comparing LRCKI, LRCKO, and a reference clock. The results include an offset for the FIFO pointer and the coefficients required for re-sampling function.

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10.2 Functional Block Diagram

10.3 Feature Description

10.3.1 Input Port Operation

The audio input port is a three-wire synchronous serial interface that can operate in either slave or master mode. The SDIN input (pin 4) is the serial audio data input. Audio data is input at the SDIN pin in one of three standard audio data formats: Philips I2S, Left-Justified, or Right-Justified. The audio data word length can be up to 24-bits for I2S and Left-Justified formats, while the Right-Justified format supports 16-bit, 18-bit, 20-bit, or 24-bit data. The data formats are shown in Figure 59, while critical timing parameters are shown in Figure 60 and listed in the Electrical Characteristics section. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: SRC4192-Q1

Figure 59. Input Data Formats Figure 60. Input Port Timing BCKI operates at a fixed rate of 64 fS. sampling frequency. The LRCKI duty cycle is fixed to 50% for master mode operation. and IFMT2 (pin 12) inputs are used to set the input port data format.

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Table 1. Input Port Data Format Selection

10.3.2 Output Port Operation

The audio output port is a four-wire synchronous serial interface that can operate in either Slave or Master mode. shown in Figure 68 and Figure 69. Figure 61. Output Data Formats

Figure 62. Output Port Timing regarding TDM mode operation is included in the Application and Implementation section. master mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in master mode. (pin 18), OWL0 (pin 17), and OWL1 (pin 16) inputs are used to set the output port data format and word length. Table 2. Output Port Data Format Selection

10.3.3 Soft Mute Function

artifact-free muting of the audio output port.

10.3.4 Ready Output

the rate estimator block, which indicates that the input-to-output sampling frequency ratio has been determined.

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10.4 Device Functional Modes

10.4.1 Reset and Power Down Operation

again to force a reset. Figure 63 shows the reset timing for the SRC4192-Q1 device. Figure 63. Reset Pulse Width Requirement

10.4.2 Audio Port Modes

using the MODE0 (pin 26), MODE1 (pin 27), and MODE2 (pin 28) inputs. reference clock input (RCKI). Only one port can be set to master mode at any given time, as indicated in Table 3. Table 3. Setting the Serial Port Modes

10.4.3 Bypass Mode

devices. The BYPAS pin and control bit should be set to 0 for normal operation.

validate and test their design implementation to confirm system functionality.

11.1 Application Information

designing the SRC4192-Q1 device into the end equipment.

11.1.1 Interfacing to Digital Audio Receivers and Transmitters

including receivers and transmitters commonly used for AES/EBU, S/PDIF, and CP1201 communications. transmitters to address these applications. 3.3 V for interface compatibility. Figure 64. Interfacing the SRC4192-Q1 to the DIR9001 Digital Audio Interface Receiver are set to 3.3 V for compatibility.

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One Sub-Frame contains 64 bits, with 32 bits per channel. For each channel, the audio data is left justified, MSB first format, with the word length determined by the OWL[1:0] pins/bits. Figure 65. Interfacing the SRC4192-Q1 to the DIT4096/4192 Digital Audio Interface Transmitter to ensure that the transmitter is synchronized to the output port data of the SRC4192-Q1 device.

11.1.2 TDM Applications

while Figure 67 shows TDM input timing parameters, which are listed in the Electrical Characteristics section. Figure 66. TDM Frame Format

Figure 67. Input Timing for TDM Mode

• fBCKO = Output Port Bit Clock (BCKO), 27.648-MHz maximum
• fs = Output Port Sampling (or LRCKO) Frequency, 216-kHz maximum. (1) This relationship holds true for both slave and master modes. Figure 68 and Figure 69 show typical connection schemes for TDM mode. Although the TMS320C671x DSP device family is shown as the audio processing engine in the figures, other TI digital signal processors with a multi-channel buffered serial port (McBSPTM) can also function with this arrangement. Interfacing to processors from other manufacturers is also possible. Refer to Figure 62 in this data sheet, along with the equivalent serial port timing diagrams shown in the DSP data sheet, to determine compatibility.

Figure 68. TDM Interface where all Devices are Slaves

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Figure 69. TDM Interface where one Device is Master to Multiple Slaves

11.2 Typical Application

bypass capacitors are included. The capacitors should be placed as close to the IC package as possible. Figure 70. Typical Connection Diagram for the SRC4192-Q1

11.2.1 Design Requirements

• Control: Hardware, I2C, or SPI
• Audio input: PCM serial data
• Audio output: PCM serial data
• Reference clock

11.2.2 Detailed Design Procedure

11.2.2.1 Control Method

GND directly or by the GPIO of a host controller.

11.2.2.2 Audio Input and Output

as 24-bit I2S or left justified PCM serial data at up to a 212-kHz sampling rate. A TDM format is also available. slave. A 16:1 or 1:16 is the max ratio supported between the input and output audio sampling rates.

11.2.3 Application Curves

Figure 71. FFT With 1-kHz Input Tone at 0 dBFS Figure 72. FFT With 1-kHz Input Tone at 0 dBFS

12 Power Supply Recommendations

the VIO and VDD supplies of the SRC4192-Q1 device must be set to 3.3 V.

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13 Layout

13.1 Layout Guidelines

13.1.1 Reference Clock

maximum external reference clock input frequency is 50 MHz. Figure 73. Reference Clock Input Connections and Timing Requirements

13.1.2 Pin Compatibility With the Analog Devices AD1896

indicated in the following paragraphs.

13.1.2.1 Crystal Oscillator

13.1.2.2 Reference Clock Frequency

768 fS reference clock rate.

13.1.2.3 Master Mode Maximum Sampling Frequency

design to support the higher sampling frequency of the SRC4192-Q1 device.

13.1.2.4 Matched Phase Mode

driven from the same clock source, the devices will be phase-matched.

13.2 Layout Example

pour to the lower main PCB-ground plane with multiple vias. Figure 74. SRC4192-Q1 Layout Example

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14 Device and Documentation Support

14.1 Documentation Support

14.1.1 Related Documentation

For related documentation, see the following: SRC4192EVM Evaluation Module, SBAU088

14.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

14.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

14.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

14.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: SRC4192-Q1

www.ti.com 10-Nov-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SRC4192QDBRQ1 PREVIEW SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SRC4192Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 10-Nov-2015 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF SRC4192-Q1 :

• Catalog: SRC4192 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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