SRC4190IDB

SRC4190 TI | Alldatasheet

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AES, S/PDIF Output Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SRC4190 SBFS023C –JUNE 2003–REVISED DECEMBER 2016 SRC4190192-kHzStereoAsynchronousSample-RateConverters

1 Features

1• Automatic Sensing of the Input-to-Output Sampling Ratio

• Wide Input-to-Output Sampling Range: 16:1 to 1:16
• Supports Input and Output Sampling Rates up to 212 kHz
• Dynamic Range: 128 dB (–60-dB fS Input, BW = 20 Hz to fS / 2, A-Weighted)
• THD+N: –125 dB (0-dB fS Input, BW = 20 Hz to fS / 2)
• Attenuates Sampling and Reference Clock Jitter
• High-Performance, Linear Phase Digital Filtering
• Flexible Audio Serial Ports: – Master or Slave Mode Operation Supports I2S, Left Justified, Right Justified, and TDM Data Formats – Supports 16-, 18-, 20-, or 24-Bit Audio Data, TDM Mode Allows Daisy Chaining of up to Eight Devices
• Supports 24-, 20-, 18-, or 16-Bit Input and Output – All Output Data is Dithered from the Internal 28-Bit Data Path
• Low Group Delay Option for Interpolation Filter
• Soft Mute Function
• Bypass Mode
• Power-Down Mode
• Operates from a Single 3.3-V Power Supply
• Small 28-Pin SSOP Package
• Pin Compatible With the SRC4192, AD1895, and AD1896 NOTE: U.S. Patent No. 7,262,716 NOTE: See Application and Implementation for details.

2 Applications

• Digital Mixing Consoles
• Digital Audio Workstations
• Audio Distribution Systems
• Broadcast Studio Equipment
• High-End A/V Receivers
• General Digital Audio Processing

3 Description

The SRC4190 device is an asynchronous sample rate converter designed for professional and broadcast audio applications. The SRC4190 combines a wide input-to-output sampling ratio with outstanding dynamic range and low distortion. Input and output serial ports support standard audio formats, as well as a Time Division Multiplexed (TDM) mode. Flexible audio interfaces allow the SRC4190 to connect to a wide range of audio data converters, digital audio receivers and transmitters, and digital signal processors. The SRC4190 is a standalone pin-programmed device, with control pins for mode, data format, mute, bypass, and low group delay functions. The SRC4190 may be operated from a single 3.3-V power supply. A separate digital I/O supply (VIO) operates with a 1.65-V to 3.6-V supply, allowing greater flexibility when interfacing to current and future generation signal processors and logic devices. The SRC4190 is available in a 28-pin SSOP package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SRC4190 SSOP (28) 10.20 mm × 5.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Diagram

SBFS023C –JUNE 2003–REVISED DECEMBER 2016 www.ti.com Product Folder Links: SRC4190 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Table of Contents

11.2 Receiving Notification of Documentation Updates 29

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2007) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision A (July 2003) to Revision B Page

www.ti.com SBFS023C –JUNE 2003–REVISED DECEMBER 2016 Product Folder Links: SRC4190 Submit Documentation FeedbackCopyright © 2003–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

NAME NO. BCKI 5 Input and Output Input port bit clock I/O BCKO 25 Input and Output Output port bit clock I/O BYPAS 9 Input ASRC bypass control input (active high) DGND 8, 21 Ground Digital ground IFMT0 10 Input Input port data format control input IFMT1 11 Input Input port data format control input IFMT2 12 Input Input port data format control input LGRP 1 Input Low group delay control input (active high) LRCKI 6 Input and Output Input port left and right word clock I/O LRCKO 24 Input and Output Output port left and right word clock I/O MODE0 26 Input Serial port mode control input MODE1 27 Input Serial port mode control input MODE2 28 Input Serial port mode control input MUTE 14 Input Output mute control input (active high) NC 3 — No connection OFMT0 19 Input Output port data format control input OFMT1 18 Input Output port data format control input OWL0 17 Input Output port data word length control input OWL1 16 Input Output port data word length control input RCKI 2 Input Reference clock input RDY 15 Output ASRC ready status output (active low) RST 13 Input Reset input (active low) SDIN 4 Input Audio serial data input SDOUT 23 Output Audio serial data output TDMI 20 Input TDM data input. Connect to DGND when not in use. VDD 22 Power Digital core supply, 3.3 V VIO 7 Power Digital I/O supply, 1.65 V to VDD

SBFS023C –JUNE 2003–REVISED DECEMBER 2016 www.ti.com Product Folder Links: SRC4190 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VDD –0.3 4 V Supply voltage, VIO –0.3 4 V Digital input voltage –0.3 4 V Operating temperature –45 85 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD VDD supply voltage 3 3.3 3.6 V VIO 1.8-V supply voltage 1.65 1.8 1.95 V VIO 3.3-V supply voltage 3 3.3 3.6 V Operating temperature –45 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) SRC4190 UNITDB (SSOP)

28 PINS

RθJA Junction-to-ambient thermal resistance 77.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 37.6 °C/W RθJB Junction-to-board thermal resistance 38.4 °C/W ψJT Junction-to-top characterization parameter 8.8 °C/W ψJB Junction-to-board characterization parameter 38.1 °C/W

www.ti.com SBFS023C –JUNE 2003–REVISED DECEMBER 2016 Product Folder Links: SRC4190 Submit Documentation FeedbackCopyright © 2003–2016, Texas Instruments Incorporated (1) Dynamic performance measured with an Audio Precision System Two Cascade or Cascade Plus.

6.5 Electrical Characteristics

TA = 25°C, VDD = 3.3 V = VIO = 3.3 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE(1) Resolution 24 Bits fSIN Input sampling frequency 4 212 kHz fSOUT Output sampling frequency 4 212 kHz Input:Output sampling ratio Upsampling 1:16 Downsampling 16:1 Dynamic range BW = 20 Hz to fSOUT / 2, –60-dBFS input, fIN = 1 kHz, Unweighted (add 3 dB for A‑weighted result) 44.1 kHz:48 kHz 125 dB 48 kHz:44.1 kHz 125 48 kHz:96 kHz 125 44.1 kHz:192 kHz 125 96 kHz:48 kHz 125 192 kHz:12 kHz 125 192 kHz:32 kHz 125 192 kHz:48 kHz 125 32 kHz:48 kHz 125 12 kHz:192 kHz 125 Total harmonic distortion + noise BW = 20 Hz to fSOUT / 2, 0-dBFS input, fIN = 1 kHz, Unweighted 44.1 kHz:48 kHz –125 dB 48 kHz:44.1 kHz –125 48 kHz:96 kHz –125 44.1 kHz:192 kHz –125 96 kHz:48 kHz –125 192 kHz:12 kHz –125 192 kHz:32 kHz –125 192 kHz:48 kHz –125 32 kHz:48 kHz –125 12 kHz:192 kHz –125 Interchannel gain mismatch 0 dB Interchannel phase deviation 0 ° Mute attenuation 24-bit word length, A-weighted –128 dB DIGITAL INTERPOLATION FILTER Passband 0.4535 × fSIN Hz Passband ripple ±0.007 dB Transition band 0.4535 × fSIN 0.5465 × fSIN Hz Stop band 0.5465 × fSIN Hz Stop band attenuation –125 dB Normal group delay (LGRP = 0) 102.53125 / fSIN s Low group delay (LGRP = 1) 70.53125 / fSIN s DIGITAL DECIMATION FILTER Passband 0.4535 × fSOUT Hz Passband ripple ±0.008 dB Transition band 0.4535 × fSOUT 0.5465 × fSOUT Hz Stop band 0.5465 × fSOUT Hz Stop band attenuation –125 dB Group delay 36.46875 / fSOUT s DIGITAL I/O VIH High-level input voltage 0.7 × VIO VIO V VIL Low-level input voltage 0 0.3 × VIO V IIH High-level input current 0.5 10 µA IIL Low-level input current 0.5 10 µA

SBFS023C –JUNE 2003–REVISED DECEMBER 2016 www.ti.com Product Folder Links: SRC4190 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Electrical Characteristics (continued) TA = 25°C, VDD = 3.3 V = VIO = 3.3 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IO = –4 mA 0.8 × VIO VIO V VOL Low-level output voltage IO = 4 mA 0 0.2 × VIO V CIN Input capacitance 3 pF POWER SUPPLY VDD VDD operating voltage 3 3.3 3.6 V VIO VIO operating voltage 1.65 3.3 3.6 IDD VDD supply current VDD = VIO = 3.3 V, RST = 0, No clocks, fSIN = 192 kHz, fSOUT = 192 kHz Power down 100 µA Dynamic 66 mA IIO VIO supply current VDD = VIO = 3.3 V, RST = 0, No clocks, fSIN = 192 kHz, fSOUT = 192 kHz Power down 100 µA Dynamic 2 mA PD Power dissipation VDD = VIO = 3.3 V, RST = 0, No clocks, fSIN = 192 kHz, fSOUT = 192 kHz Power down 660 µW Dynamic 225 mW (1) fSMIN = minimum (fSIN, fSOUT). (2) fSMAX = maximum (fSIN, fSOUT).

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT REFERENCE CLOCK TIMING RCKI frequency(1)(2) 128 × fSMIN 50 MHz tRCKIP RCKI period 20 1 / (128 × fSMIN) ns tRCKIH RCKI pulse width HIGH 0.4 × tRCKIP ns tRCKIL RCKI pulse width LOW 0.4 × tRCKIP ns RESET TIMING tRSTL RST pulse width LOW 500 ns INPUT SERIAL PORT TIMING tLRIS LRCKI to BCKI setup time 10 ns tSIH BCKI pulse width HIGH 10 ns tSIL BCKI pulse width LOW 10 ns tLDIS SDIN data setup time 10 ns tLDIH SDIN data hold time 10 ns OUTPUT SERIAL PORT TIMING tDOPD SDOUT data delay time 10 ns tDOH SDOUT data hold time 2 ns tSOH BCKO pulsewidth HIGH 10 ns tSOL BCKO pulse width LOW 5 ns TDM MODE TIMING tLROS LRCKO setup time 10 ns tLROH LRCKO hold time 10 ns tTDMS TDMI data setup time 10 ns tTDMH TDMI data hold time 10 ns

6.7 Typical Characteristics

TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted). Figure 1. FFT With 1 kHz Input Tone at 0 dBFS Figure 2. FFT With 1 kHz Input Tone at –60 dBFS Figure 3. FFT With 1 kHz Input Tone at 0 dBFS Figure 4. FFT With 1 kHz Input Tone at –60 dBFS Figure 5. FFT With 1 kHz Input Tone at 0 dBFS Figure 6. FFT With 1 kHz Input Tone at –60 dBFS

MODE [2:0] IFMT [2:0] OFMT [1:0] OWL [1:0] MUTE BYPAS LGRP RST Control Logic Rate Estimator LRCKI LRCKO REFCLK RDY LRCKO BCKO SDOUT TDMI Audio Output Port RCKI REFCLKReference Clock LRCKI BCKI SDIN Audio Input Port Interpolation Filters 16fSINfSIN fSOUT VDD DGND VIO DGND Re-Sampler 16fSOUT Decimation Filters Power Copyright © 2016, Texas Instruments Incorporated SRC4190 www.ti.com SBFS023C –JUNE 2003–REVISED DECEMBER 2016 Product Folder Links: SRC4190 Submit Documentation FeedbackCopyright © 2003–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The SRC4190 device is an asynchronous sample rate converter (ASRC) designed for professional audio applications. Operation at input and output sampling frequencies up to 212 kHz is supported, with an input-to- output sampling ratio from 16:1 to 1:16. Excellent dynamic range and total harmonic distortion plus noise (THD+N) are achieved by employing high performance and linear phase digital filtering. Digital filtering options allow for lower group delay processing. The audio input and output ports support standard audio data formats, as well as a TDM interface mode. 24-, 20-, 18-, and 16-bit word lengths are supported. Both ports may operate in slave mode, deriving their word and bit clocks from external input and output devices. Alternatively, one port may operate in master mode while the other remains in slave mode. In master mode, the LRCK and BCK clocks are derived from the reference clock input (RCKI). The flexible configuration of the input and output ports allows connection to a wide variety of audio data converters, interface devices, digital signal processors, and programmable logic. A bypass mode is included, which allows audio data to be passed directly from the input port to the output port, bypassing the ASRC function. The bypass option is useful for passing through encoded or compressed audio data, or nonaudio control or status data. A soft mute function is available providing artifact-free operation while muting the audio output signal. The mute attenuation is typically –128 dB. The output port data is clocked by either the audio data source in slave mode, or by the SRC4190 in master mode. The input data is passed through interpolation filters which up-sample the data, which is then passed on to the re-sampler. The rate estimator compares the input and output sampling frequencies by comparing LRCKI, LRCKO, and a reference clock. The results include an offset for the FIFO pointer and the coefficients needed for re-sampling function. The output of the re-sampler is then passed on to the decimation filter. The decimation filter performs down-sampling and anti-alias filtering functions.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Soft Mute Function

muting of the audio output port.

7.3.2 Ready Output

auto-mute function, so that the output port is muted when the rate estimator is in transition.

7.4 Device Functional Modes

7.4.1 Bypass Mode

the BYPAS pin must be set to 0.

7.4.2 Audio Port Modes

MODE0, MODE1, and MODE2 pins. reference clock input (RCKI). Only one port can be set to master mode at any given time, as indicated in Table 1. Table 1. Setting the Serial Port Modes

7.4.3 Input Port Operation

The audio input port is a three-wire synchronous serial interface that may operate in either slave or master mode. operates at a fixed rate of 64 fS.

Table 2. Input Port Data Format Selection

7.4.4 Output Port Operation

included in Application and Implementation. Figure 61. Output Data Formats

Figure 62. Output Port Timing mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in master mode. utilized to set the output port data format and word length. Table 3. Output Port Data Format Selection

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

input and output can operate in slave mode, or one can operate as a master while the other operates as a slave. A 16:1 or 1:16 ratio is the maximum supported between the input and output audio sampling rates.

8.2 Typical Application

Figure 63. Typical Connection Diagram for the SRC4190

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 4 as the input parameters. Table 4. Design Parameters

8.2.2 Detailed Design Procedure

bypass capacitors are included. These capacitors must be placed as close to the IC package as possible.

8.2.2.1 Reference Clock

The SRC4190 requires a reference clock for operation. The reference clock is applied at the RCKI input. reference clock input frequency is 50 MHz. Figure 64. Reference Clock Input Connections and Timing Requirements

8.2.2.2 Interfacing to Digital Audio Receivers and Transmitters

transmitters to address these applications. 3.3‑V supply, which requires the VIO supply for the SRC4190 to be set to 3.3-V for interface compatibility. Figure 65. Interfacing the SRC4190 to the DIR1703 Digital Audio Interface Receiver Figure 66 shows the interface between the SRC4190 output port and the DIT4096 or DIT4192 audio serial port. Once again, the VIO supplies for both the SRC4190, DIT4096, and DIT4192 are set to 3.3 V for compatibility.

Figure 66. Interfacing the SRC4190 to the DIT4096 and DIT4192 Digital Audio Interface Transmitter synchronized to the SRC4190 output port data.

8.2.2.3 TDM Applications

format, while Figure 68 shows the TDM input timing parameters, which are listed in Switching Characteristics. One Sub-Frame contains 64 bits, with 32 bits per channel. For each channel, the audio data is Left Justified, MSB first format, with the word length determined by OWL[1:0]. Figure 67. TDM Frame Format

Figure 70. TDM Interface With One Device as Master to Multiple Slaves

8.2.2.4 Pin Compatibility With the Analog Devices AD1895 and AD1896

indicated in the following paragraphs.

8.2.2.4.1 Power Supplies

while the VIO and VDD supplies of the SRC4190 must be set to 3.3 V.

8.2.2.4.2 Pin 1 Connection

supply, dependent upon the desired group delay.

8.2.2.4.3 Crystal Oscillator

8.2.2.4.4 Reference Clock Frequency

768-fS reference clock rate.

8.2.2.4.5 Master Mode Maximum Sampling Frequency

into his or her design to support the higher sampling frequency of the SRC4190.

8.2.2.4.6 Matched Phase Mode

source, the devices is phase matched.

8.2.3 Application Curves

Figure 71. FFT With 1 kHz Input Tone at –60 dBFS Figure 72. FFT With 1 kHz Input Tone at –60 dBFS

9 Power Supply Recommendations

for each supply pin placed as close to the pin as possible.

10 Layout

10.1 Layout Guidelines

10.1.1 Power Supply Pins

supplies. TI recommends values of 10 µF and 0.1 µF for these capacitors.

10.1.2 Digital Interface

causing system noise. A series resistor in the tens of ohms can be placed on each trace to minimize reflections.

10.2 Layout Example

Figure 73. Diagram of an Example Layout

www.ti.com SBFS023C –JUNE 2003–REVISED DECEMBER 2016 Product Folder Links: SRC4190 Submit Documentation FeedbackCopyright © 2003–2016, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• DIT4096 96-kHz Digital Audio Transmitter (SBOS225)
• DIT4192 192-kHz Digital Audio Transmitter (SBOS229)
• SRC4190/92/93EVM, User's Guide (SBAU088)

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SRC4190IDB Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4190I SRC4190IDB.A Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4190I SRC4190IDBR Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4190I SRC4190IDBR.A Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4190I SRC4190IDBR1G4 Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4190I SRC4190IDBR1G4.A Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4190I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 7-Oct-2025 OTHER QUALIFIED VERSIONS OF SRC4190 :

• Automotive : SRC4190-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SRC4190IDBR SSOP DB 28 2000 350.0 350.0 43.0 SRC4190IDBR1G4 SSOP DB 28 2000 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) SRC4190IDB DB SSOP 28 50 530 10.5 4000 4.1 SRC4190IDB.A DB SSOP 28 50 530 10.5 4000 4.1 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 26X 0.65 8.45 28X 0.38 0.22 8.2

7.4 TYP

0.05 MIN

0.25 GAGE PLANE 0 -8

2 MAX

B 5.6 5.0 NOTE 4 A 10.5 9.9 NOTE 3 0.95 0.55 (0.15) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018

0.15 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 14 15 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 14 15

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