SRC0CS25D

SRC0 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Description
• 2 Pin descriptions
• 3 Operation
• 4 Waveforms
• 5 Typical operating characteristics
• 6 Maximum ratings
• 7 DC and AC characteristics
• 8 Package mechanical data
• 9 Product selector
• 10 Revision history

Features

 Operating voltage 1.6 V to 5.5 V  Low standby current of 0.6 µA  Adjustable Smart Reset™ assertion delay time driven by external CSRD  Power-up duration determined primarily by push-button press  Debounced PB and SR inputs  PB and SR ESD inputs withstand voltage up to ±15 kV (air discharge) ±8 kV (contact discharge)  Active high or active low enable output option (EN or EN) provides control of MOSFET, DC- DC converter, regulator, etc.  Secure startup, interrupt, Smart Reset™ or power-down driven by push-button  Precise 1.5 V voltage reference with 1% accuracy  Industrial operating temperature -40 to +85 °C  Available in TDFN12 2 x 3 mm package

Applications

 Wearable  Activity tracker  Smartwatch  Smartglasses TDFN12 Table 1. Device summary

1. External pull-up resistor needs to be connected to open drain outputs.
2. For a successful startup, the PS HOLD (Power Supply Hold) needs to be pulled high within specific time, tON_BLANK.

1 Description

for distinguishing between interrupt by push-button or undervoltage. features such as selectable threshold, hysteresis, timeouts, output types, etc. Figure 1. Application hookup

1. A resistor is required for open drain output type only. A 10 k  pull-up is sufficient in most applications.
2. Capacitor C REF is mandatory on VREF output (even if VREF is not used). Capacitor value of 1 µF is
3. For the SRC0 the processor has to confirm the proper power-on during the fixed time period, t ON_BLANK.

unresponsive microprocessor.

Figure 5. TDFN12 pin connections Table 2. Pin descriptions

10 RST Reset output

11 INT Interrupt output

12 GND Ground

Figure 6. Block diagram

1. Internal pull-up resistor connected to PB input (see Table 5 for precise specifications).
2. Optional internal pull-up resistor connected to SR input (see Table 5 for precise specifications).
3. Internal pull-down resist or is connected to PSHOLD input only during startup (see Figure 7, 8, 9, 10, 11, 12,

2 Pin descriptions

VCC is monitored during startup and normal operation for sufficient voltage level. Decouple the VCC pin from ground by placing a 0.1 µF capacitor as close to the device as possible. SR - Smart Reset™ button input This input is equipped with voltage detector with a factory-trimmed threshold and has ±8 kV HBM ESD protection. Both PB and SR buttons have to be pressed and held for tSRD period so the long push is recognized and the reset is asserted (or the enable output is deasserted depending on the option) - see Figure 13, 14, and 15. Active low SR input is usually connected to GND through the momentary push-button (see Figure 1) and it has an optional 100 k pull-up resistor. It is also possible to drive this input using an external device with either open drain (recommended) or push-pull output. Open drain output can be connected in parallel with push-button or other open drain outputs, which is not possible with push-pull output. SR input is monitored for falling edge after power-up and must not be grounded permanently. VREF - external precise 1.5 V voltage reference This 1.5 V voltage reference is specified with very tight accuracy of 1% (see Table 5). It has proper output voltage as soon as the reset output is deasserted (i.e. after tREC expires) and it is disabled when the device enters standby mode. A mandatory capacitor needs to be connected to VREF output (even if VREF is not used). Capacitor value of 1 µF is recommended. PSHOLD input This input is equipped with a voltage detector with a factory-trimmed threshold. It is used to confirm correct power-up of the device (if EN or EN is not asserted) or to initiate a shutdown (if EN or EN is asserted). Forcing PSHOLD high during power-up confirms the proper start of the application and keeps enable output asserted. Because most processors have outputs in high-Z state before initialization, an internal pull-down resistor is connected to PSHOLD input during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18). Forcing the PSHOLD signal low during normal operation deasserts the enable output (see Figure 12). Input voltage on this pin is compared to an accurate voltage reference. CSRD - Smart Reset™ delay time input A capacitor to ground determines the additional time (tSRD) that PB with SR must be pressed and held before a long push is recognized. The connected CSRD capacitor is charged with ISRD current. Additional Smart Reset™ delay time tSRD ends when voltage on the CSRD capacitor reaches the VSRD voltage threshold. It is recommended to use a low ESR capacitor (e.g. ceramic). If the capacitor is not used, leave the CSRD pin open. If no capacitor is connected, there is no tSRD and a long push is recognized right after tINT_Min expires (see Figure 18 and 19).

This input is equipped with a voltage detector with a factory-trimmed threshold and has ± 8 kV HBM ESD protection. When the PB button is pressed and held, the battery voltage is detected and EN (or EN) is asserted if the battery voltage is above the threshold VTH+ during the whole tDEBOUNCE period (see Figure 13). A short push of the push-button during normal operation can initiate an interrupt through debounced INT output (see Figure 14) and a long push of PB and SR simultaneously can either assert reset output RST (see Figure 18) or deassert the EN or EN output (see Figure 19) based on the option used. Note: A switch to GND must be connected to this input (e.g. mechanical push-button, open drain output of external circuitry, etc.), see Figure 1. This ensures a proper startup signal on PB (i.e. a transition from full VCC below specified VIL). PB input has an internal 100 k pull-up resistor connected. VCCLO - high threshold detection output During power-up, VCCLO is low when VCC supply voltage is below the VTH+ threshold. After successful power-up (i.e. during normal operation) VCCLO is low anytime undervoltage is detected (see Figure 13). Output type is active low and open drain by default. Open drain output type requires a pull- up resistor. A 10 k is sufficient in most applications. VCCLO is floating when SRC0 is in standby mode. PBOUT - PB input state If the push-button PB is pressed, the pin stays low during the tDEBOUNCE time period. If PB is asserted for the entire tDEBOUNCE period, PBOUT will then stay low for at least tINT_Min. If PB is asserted after tINT_Min expires, PBOUT will return high as soon as PB is deasserted (see Figure 22). PBOUT ignores PB assertion during an undervoltage condition. At startup on the SRC0 PBOUT will respond only to the first PB assertion and any other assertion will be ignored until tON_BLANK expires. This output is active low and open drain by default. Open drain output type requires a pull-up resistor. A 10 k is sufficient in most applications.

This output is intended to enable system power (see Figure 1). EN is asserted high after a valid turn-on event has been detected and confirmed (i.e. push-button has been pressed and held for t DEBOUNCE or more and VCC > VTH+ voltage level has been detected - see Figure 13). EN is released low if any of the conditions below occur: a) the push-button is released before PS HOLD is driven high. b) PS HOLD is driven low during normal operation (see Figure 14). c) an undervoltage condition is detected for more than tSRD + tINT_Min + tDEBOUNCE (see Figure 21). d) a long push of the buttons is detec ted (only for the device with option “EN deasserted by long push” - see Figure 19) or PSHOLD is not driven high during tON_BLANK after a long push of the buttons (only for the device with option “RST asserted by long push” - see Figure 18). Described logic levels are inverted in case of EN output. Output type is push-pull by default. RST - reset output This output pulls low for tREC: a) during startup. PB has been pressed (falling edge on the PB detected) and held for at least tDEBOUNCE and VCC > VTH+ (see Figure 7, 8, 9, 10, 11, 12 and 13 for more details). b) after long push detection (valid only for the device with option “RST asserted by long push”). PB has been pressed (falling edge on the PB detected) and held for more than tDEBOUNCE + tSRD (additional Smart Reset™ delay time can be adjusted by the external capacitor CSRD) - see Figure 18. Output type is active low and open drain by default. Open drain output type requires a pull- up resistor. A 10 k is sufficient in most applications. INT - interrupt output While the system is under normal operation (PSHOLD is driven high, power for application is asserted), the INT is driven low if: a) V CC falls below VTH- threshold (i.e. undervoltage is detected - see Figure 20 and 21). b) the falling edge on the PB is detected and the push-button is held for tDEBOUNCE or more. INT is driven low after tDEBOUNCE and stays low as long as PB is held. The INT signal is held high during power-up. The state of the PBOUT output can be used to determine if the interrupt was caused by either the assertion of the PB input, or was due to the detection of an undervoltage condition on VCC. INT output is asserted low for at least tINT_Min. Output type is active low and open drain by default. Open drain output type requires a pull- up resistor. A 10 k is sufficient in most applications. GND - ground

3 Operation

The SRC0 simplified smart push-button on/off controller with Smart Reset and power-on lockout enables and disables power for the application depending on push-button states, signals from the processor, and battery voltage. Power-on Because most of the processors have outputs in high-Z state before initialization, an internal pull-down resistor is connected to PS HOLD input during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18). To power up the device the push-button PB has to be pressed for at least tDEBOUNCE and VCC has to be above VTH+ for the whole tDEBOUNCE period. If the battery voltage drops below VTH+ during the tDEBOUNCE, the counter is reset and starts to count again when VCC > VTH+ (see Figure 13). After tDEBOUNCE the enable signal is asserted (EN goes high, EN goes low), reset output RST is asserted for tREC and then the startup routine is performed by the processor. During initialization, the processor sets the PSHOLD signal high. On the SRC0 the PSHOLD signal has to be set high prior to push-button release and tON_BLANK expiration, otherwise the enable signal is deasserted (EN goes low, EN goes high) - see Figure 7, 8, 9, and 10. The time up to push-button release represents the maximum time allowed for the system to power up and initialize the circuits driving the PSHOLD input. If the PSHOLD signal is low at push-button release, the enable output is deasserted immediately, thus turning off the system power. If tON_BLANK expires prior to push-button release, the PSHOLD state is checked at its expiration. This safety feature disables the power and prevents discharging the battery if the push-button is stuck or it is held for an unreasonable period of time and the application is not responding (see Figure 8 and 10). PB status, INT status and VCC undervoltage detection are not monitored until power-up is completed. Push-button interrupt If the device works under normal operation (i.e. PS HOLD is high) and the push-button PB is pressed for more than tDEBOUNCE, a negative pulse with minimum tINT_Min width is generated on the INT output. By connecting INT to the processor interrupt input (INT or NMI) a safeguard routine can be performed and the power can be shut down by setting PSHOLD low - see Figure 14. Forced power-down mode The PS HOLD output can be forced low anytime during normal operation by the processor and can deassert the enable signal - see Figure 14. Undervoltage detection If V CC voltage drops below VTH- voltage threshold during normal operation, the INT output is driven low (see Figure 20 and Figure 21). If an undervoltage condition is detected for tDEBOUNCE + tINT_Min + tSRD, the enable output is deasserted (see Figure 21). Hardware reset or power-down while system not responding

If the system is not responding and the system hangs, the PB and SR push-button can be pressed simultaneously longer than tDEBOUNCE + tINT_Min + tSRD, and then a) either the reset output RST is asserted for tREC and the processor is reset (valid only for the device with option “RST asserted by long push”) – see Figure 18 b) or the power is disabled by EN or EN signal (valid only for the device with option “EN deasserted by long push”) – see Figure 19 The tSRD is set by the external capacitor connected to the CSRD pin. SR input is monitored for falling edge after power-up and must not be grounded permanently. Standby If the enable output is deasserted (i.e. EN is low or EN is high), the STM660x device enters standby mode with low current consumption (see Table 5). In standby mode PB input is only monitored for the falling edge. The external 1.5 V voltage reference is also disabled in standby mode.

4 Waveforms

Figure 7. Successful power-up on SRC0 (PB released prior to tON_BLANK expiration)

1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 k  is connected to PSHOLD input during power-up.
3. EN signal is high even after PB release, because processor sets PSHOLD signal high before PB is

INT signal is held high during power-up (i.e. until PB release in this case). VCC is considered VCC > VTH+.

Figure 8. Successful power-up on SRC0 (tON_BLANK expires prior to PB release)

1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 k  is connected to PSHOLD input during power-up.
3. t ON_BLANK expires prior to PB release so PSHOLD is checked at its expiration.

INT signal is held high during power-up (i.e. until tON_BLANK expires in this case). VCC is considered VCC > VTH+.

Figure 9. Unsuccessful power-up on SRC0 (PB released prior to tON_BLANK)

1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 k  is connected to PSHOLD input during power-up.
3. EN signal goes low with PB release, because processor did not force PSHOLD signal high.

INT signal is held high during power-up (i.e. until PB release in this case). VCC is considered VCC > VTH+.

Figure 10. Unsuccessful power-up on SRC0 (tON_BLANK expires prior to PB release)

1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 k  is connected to PSHOLD input during power-up.
3. t ON_BLANK expires prior to PB release so PSHOLD is checked at its expiration.

INT signal is held high during power-up (i.e. until tON_BLANK expires in this case). VCC is considered VCC > VTH+.

Figure 11. Successful power-up on SRC0

1. PB detection on falling edge.
2. Internal pull-down resistor 300 k  is connected to PSHOLD input during power-up.
3. PS HOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is high

therefore the EN signal remains asserted. INT signal is held high during power-up (i.e. until tON_BLANK expires in the case of the STM6601). VCC is considered VCC > VTH+.

Figure 12. Unsuccessful power-up on SRC0

1. PB detection on falling edge.
2. Internal pull-down resistor 300 k  is connected to PSHOLD input during power-up.
3. PS HOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is not

INT signal is held high during power-up (i.e. until tON_BLANK expires in the case of the STM6601). VCC is considered VCC > VTH+.

Figure 13. Power-up on STM660x with voltage dropout

1. PB detection on falling and rising edges.
2. Internal pull-down resistor 300 k  is connected to PSHOLD input during power-up.
3. INT signal is held high during power-up.

Figure 14. PB interrupt

1. PB detection on falling edge.

Note: VCC is considered VCC > VTH+.

Figure 17. Invalid long push

Figure 18. Long push (option with RST assertion)

1. t SRD period is set by external capacitor CSRD.
2. PB ignored during tINT_Min.
3. PS HOLD signal is ignored during tON_BLANK. Its level is checked after tON_BLANK expires and if it is high the

EN signal remains asserted, otherwise EN goes low.

1. Internal pull-down resistor 300 k  is connected to PSHOLD input during startup when device is reset.

Figure 19. Long push (option with enable deassertion)

1. t SRD period is set by external capacitor CSRD.
2. PB ignored during tINT_Min.
3. After t SRD expires EN is forced low.

Figure 22. PBOUT output waveform

1. Pulses on PB shorter than glitch immunity are ignored.
2. Pulses on PB shorter than tDEBOUNCE are not recognized by PBOUT.
3. Minimum pulse width on PB OUT is tINT_Min.
4. If push-button is held longer than t DEBOUNCE + tINT_Min, PBOUT goes high when the push-button is

5 Typical operating characteristics

Figure 23. Supply current vs. temperature, normal state Figure 24. Supply current vs. temperature, standby state

Figure 39. Reference response to steps on supply voltage, IREF = 15 µA, TA = 25 °C Note: 1 Supply voltage goes from 3.6 V to 5.5 V and back to 3.6 V, ramp 1 V / 100 ns. 2 1 µF capacitor is connected to the V REF pin.

Figure 40. Reference response to steps in load current, VCC = 3.6 V, TA = 25 °C Note: 1 Supply voltage goes from 0 µA to 15 µA and back to 0 µA, ramp 1 µA / 100 ns. 2 1 µF capacitor is connected to the V REF pin.

6 Maximum ratings

absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute maximum ratings

1. Reflow at peak temperature of 260 °C. T he time above 255 °C must not exceed 30 seconds.

7 DC and AC characteristics

relying on the quoted parameters. Table 4. Operating and AC measurement conditions Table 5. DC and AC characteristics

Table 5. DC and AC characteristics (continued)

1. Valid for ambient operating temperature: T A = –40 to 85 °C; VCC = 1.6 V to 5.5 V (except where noted).
2. Typical values are at T A = +25 °C.
3. This blanking time allows the pr ocessor to start up correctly (see Figure 7, 8, 9, 10, 11, 12).
4. The internal pull-up resistor connected to the SR input is optional.
5. Valid for push-pull only.
6. Minimum delay time between enable deas sertion and enable reassertion, allowing the application to complete the power-

down properly. PB is ignored during this period.

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Figure 41. TDFN12 (2 x 3 mm) package outline Table 6. TDFN12 (2 x 3 mm) package mechanical data

0.10 C A B

Figure 42. TDFN12 (2 x 3 mm) recommended footprint

Figure 43. Carrier tape for TDFN12 (2 x 3 mm) package Table 7. Carrier tape dimensions for TDFN12 (2 x 3 mm) package

9 Product selector

Table 8. SRC0 product selector

1. EN (or EN ) output is push-pull. RST, INT, PBOUT and VCCLO outputs are open drain.
2. After t SRD expires through long push, either device reset (RST) will be activated for tREC (240 ms min.) or the EN (or EN)

connecting the external capacitor to the CSRD pin.

1. Where “p” = assembly plant, “y” = assembly year (0 to 9) and “ww” = assembly work week (01 to 52).
2. Please contact local ST sale s office for availability.

Table 9. Document revision history 04-Mar-2014 1 Initial release.