SR5E1E3

Datasheet - SR5E1E3, SR5E1E5, SR5E1E7 - SR5 E1 line of Stellar electrification MCUs — 32-bit Arm® Cortex®‑M7 automotive MCU 2x cores, 300 MHz, 2 MB flash, rich analog, 104 ps 24‑channel high‑resolution timer, HSM, and ASIL D

Document overview

• Manufacturer or author: STMICROELECTRONICS
• PDF pages: 99

Technical content

Datasheet sections

• 1 Introduction
• 1.1 Document overview
• 1.2 Description
• 1.3 Device features
• 1.4 Block diagram
• 2 Package pinouts and signal descriptions
• 3 Electrical characteristics
• 3.1 Introduction
• 3.2 Absolute maximum ratings
• 3.3 Operating conditions
• 3.3.1 Power domains and power-up/-down sequencing
• 3.4 Electrostatic discharge (ESD)
• 3.5 Electromagnetic emission characteristics
• 3.6 Temperature profile
• 3.7 Device consumption
• 3.8 I/O pad specification
• 3.8.1 I/O input DC characteristics
• 3.8.2 I/O output DC characteristics
• 3.8.3 I/O pad current specifications
• 3.9 Reset pad (RESETn) electrical characteristics
• 3.10 PLLs
• 3.10.1 PLL0
• 3.10.2 PLL1
• 3.11 Oscillators
• 3.11.1 Low-speed internal RC oscillator (LSI)
• 3.11.2 External crystal oscillator 40 MHz (XOSC)
• 3.11.3 Internal RC 16 MHz oscillator (IRCOSC)
• 3.12 Analog subsystem
• 3.12.1 ADC input description
• 3.12.2 SARADC 12-bit electrical specification
• 3.12.3 SDADC electrical specification
• 3.12.4 SDADC filter modes
• 3.12.5 Temperature sensor
• 3.12.6 Fast-DAC
• 3.12.7 Buffered-DAC

Features

• AEC-Q100 automotive qualified
• SR5 high-performance analog MCUs offering: – Digital and analog high-frequency control requested by new wide- bandgap technologies (silicon carbide and gallium nitride) – Superior real-time and functional safety performance (ASIL-D capability) – Built-in fast and cost-optimized OTA (over-the-air) reprogramming capability (with built-in dual-image storage) – High-speed security cryptographic services (HSM) Cores
• 2× 32-bit Arm® Cortex®‑M7 with double-precision FPU, L1 cache and DSP instructions running at up to 300 MHz to reach 1284 DMIPS/2.14 DMIPS/MHz/ core (Dhrystone 2.1) – Split-lock configuration, allowing either 2 cores in parallel or 1 core in lockstep configuration
• 2 DMA engines in lockstep configuration Memories
• Up to 2 MB on-chip flash memory with read while write support – 1920 KB code flash memory split in two banks allowing 960 KB OTA reprogramming – 160 KB HSM dedicated code flash memory
• 96 KB data flash memory (64 KB + 32 KB dedicated to HSM)
• 488 KB on-chip general-purpose SRAM: – 2× 32 KB instruction TCM + 2× 64 KB data TCM – 256 KB system RAM – 40 KB HSM dedicated system RAM Security: hardware security module (HSM)
• Cybersecurity ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details)
• On-chip high-performance security module with EVITA medium support with dedicated RAM and flash memory
• Based on a Cortex®‑M0+ core running at up to 150 MHz
• Hardware accelerator for symmetric cryptography eTQFP100 (14x14x1.0mm) eTQFP100 (14 × 14 × 1.0 mm) eTQFP144 (20 × 20 × 1.0 mm) eLQFP176 (24 × 24 × 1.4 mm) Product status link Part number Package SR5E1E3 eTQFP100 SR5E1E5 eTQFP144 SR5E1E7 eLQFP176 SR5 E1 line of Stellar electrification MCUs — 32-bit Arm® Cortex®‑M7 automotive MCU 2x cores, 300 MHz, 2 MB flash, rich analog, 104 ps 24‑channel high‑resolution timer, HSM, and ASIL D SR5E1E3, SR5E1E5, SR5E1E7 Datasheet DS13808 - Rev 8 - November 2025 For further information, contact your local STMicroelectronics sales office.

Safety: comprehensive new generation ASIL-D safety concept

• State-of-the-art safety measures at all levels of the architecture for the most efficient implementation of ISO

26262 ASIL-D functionalities

• FCCU for collection and reaction to failure notifications with enhanced configurability
• Memory error management unit (MEMU) for collection and reporting of error events in memories
• Cyclic redundancy check (CRC) unit Enhanced peripherals for fast control loop capability
• 12 timers: – 2× HRTIM (high-resolution and complex waveform builder) in total: 12× 16-bit counters, up to 102 ps resolution, 24 PWM – 2× 16-bit 6-channel advanced control timers in total, with up to 12× PWM – 2× 32-bit general-purpose timers in total, with up to 8× IC/OC/PWM or pulse counter and quadrature encoder input – 4× 16-bit general-purpose timers in total, with up to 11× PWM, 2 of which paired – 2× 16-bit basic timers
• Enhanced analog-to-digital converter system with: – 5 separate 12-bit SAR analog converters, 8 channels each. Sampling rate up to 2.5 MSPS in single mode, 5 MSPS in dual mode – 2 separate 16-bit sigma-delta analog converters
• 12-bit digital-to-analog converters (DAC) – 2 buffered external channels 1 MSPS – 8 unbuffered internal channels 15 MSPS
• 8 rail-to-rail analog comparators, 50 ns propagation delay
• Hardware accelerator – 1× CORDIC for trigonometric function acceleration Communication interfaces
• 4 modular controller area network (MCAN) modules, all supporting flexible data rate (ISO CAN-FD)
• 3 UART modules with LIN functionality
• 4 serial peripheral interface (SPI) modules, 2 multiplexed with I²S interfaces
• 2 I²C modules Advanced debug and trace for high-performance automotive application development
• Built around Arm® CoreSight™-600
• Debug interface: Arm® CoreSight™ JTAG (IEEE 1149.1) or SWD
• 4 KB embedded trace FIFO for both on- and off-chip tracing
• Trace port for off-chip tracing: parallel trace port configurable from 1 to 8 data lines Others
• Power efficiency management, through separate power modes for any selected cores, peripherals or memories
• Boot assist flash (BAF) supports factory programming using a serial loader through CAN or UART
• Junction temperature range -40°C to 150°C
• Integrated power supply scheme: – Integrated internal SMPS regulator – 3.3 V supply & GPIOs SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 2/99

1 Introduction

1.1 Document overview

from the www.arm.com website. Note: Arm and the Arm logo are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

1.2 Description

advanced motor control like traction inverter applications. capability, security cryptographic services (HSM) and high efficiency OTA reprogramming capability.

1.3 Device features

description of the functionality provided by each on-chip module is given later in this document. Table 1. Features list

8 KB instruction (2 ways) for each core

16 KB data (4 ways) for each core

Core Cortex®‑M0 @ 150 MHz, which is half the device frequency.

Symmetric:

• AES-128/256, ECB, CBC, CMAC, GCM
• TRNG Dedicated flash memory 160 KB Dedicated system RAM 40 KB Dedicated data flash 32 KB Peripheral, IOs Timer modules High-resolution timer 2 modules, 6× 16-bit channels each, up to 102 ps resolution Up to 24× PWM signals (or 12× paired) Advance control timer 2 modules, 16-bit timer Up to 8 input capture, 12 output compare (8 of which paired) General-purpose timer 2 modules, 32-bit timer. Up to 8 input capture/output compare 4 modules, 16-bit timer. Up to 11 capture/output compare inputs (2 of which paired) Basic timer 2 modules, 16-bit timer Enhanced analog-to-digital converter system 12-bit SAR analog converters 5 modules, 8 channels each Fast conversion, up to 2.5 MSPS in single mode, 5 MSPS in dual mode 16-bit sigma-delta analog converters 2 modules, 2 channels each (available only in eLQFP176 and eTQFP144 packages) Output conversion rate of 333 ksps (OSR = 24) 12-bit analog comparators 8 modules, rail-to-rail, 50 ns propagation delay 12-bit digital-to-analog convertors 2 buffered external channels, 1 MSPS 8 unbuffered internal digital-to-analog channels, 15 MSPS Hardware accelerator CORDIC (for trigonometric function acceleration) 1 module Communication interfaces UART modules (with LIN function) 3 MCAN supporting CAN-FD according to ISO 11898-1 2015 CAN shared message RAM: 4 KB / MCAN (16 KB in total) Serial peripheral interface (SPI) 4 I²C 2 Software development/emulation features Arm® CoreSight™-600 libs CoreSight™‑600 libs for trace links, trace sink, and control components CoreSight™‑400 libs for debug and trace source components Debug interfaces Arm® CoreSight™-600 compliant
• Debug port (JTAG+SWD) Trace types Cortex®‑M7 instruction and data trace Off-chip trace Arm® CoreSight™ parallel trace port (1 to 8 data lines, shared with user pins, not available in the eTQFP100 package) Advance cross-trigger and performance measurement CoreSight™‑600 CTI & CTM Timestamp distribution Arm® CoreSight™ timestamp generator Security Arm® CoreSight™ authentication SR5E1E3, SR5E1E5, SR5E1E7 Introduction DS13808 - Rev 8 page 4/99

Password challenge with HSM Debug controller External tool-host CPU mailbox Host-based debugging Debug-under-reset Others Low power mode Clock gating management for selected cores, peripherals, and/or memories Smart wake-up mechanisms through events or interrupts Temperature sensor Yes Self-test controller Yes PLL 2 individual PLLs: 1 with a stable clock source for peripherals and 1 supporting frequency modulation for cores Power supply Single internal SMPS regulator for 3.3 V supply and GPIOs Boot assist flash (BAF) Supports factory programming using a serial loader through the asynchronous CAN or UART CRC channel(s) 1 SR5E1E3, SR5E1E5, SR5E1E7 Introduction DS13808 - Rev 8 page 5/99

Table 2. SR5E1E3, SR5E1E5, SR5E1E7 product selector

1.4 Block diagram

The figure below shows the top-level block diagram. Figure 1. Block diagram

The figure below shows the peripheral block diagram. Figure 2. Peripheral allocation

2 Package pinouts and signal descriptions

Refer to the SR5E1E3, SR5E1E5, SR5E1E7 I/O definition Excel® file attached to the “Architecture mapping tables” technical note.

• Package pinouts
• Pin descriptions: – Power supply and reference voltage pins – System pins – Generic pins SR5E1E3, SR5E1E5, SR5E1E7 Package pinouts and signal descriptions DS13808 - Rev 8 page 9/99

3 Electrical characteristics

3.1 Introduction

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (controller characteristics) is included in the “Symbol” column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” (system requirement) is included in the “Symbol” column. The electrical parameters shown in this document are classified by various methods. To give the customer a better understanding, the classifications listed in the table below are used and the parameters are tagged accordingly in the tables where appropriate. Table 3. Parameter classifications P Those parameters are tested in production on each individual device. relevant sample size across process variations. column are within this category. D Those parameters are derived mainly from simulations.

Electrical characteristics

DS13808 - Rev 8 page 10/99

3.2 Absolute maximum ratings

The table below describes the maximum ratings for the device. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. Table 4. Absolute maximum ratings DS13808 - Rev 8 page 11/99

Symbol C Parameter Conditions Value Unit Min Typ Max TXRAY dose SR T Maximum cumulated XRAY dose Typical range for X-rays source during inspection:80 - 130 KV; 20 - 50 μA — — 1 gray hours cumulative time at the given temperature profile. Remaining time as defined in Section 3.3: Operating conditions. 2. VDD_HV_*: allowed 3.45 V - 3.8 V (a maximum of 3.6 V for VDD_HV_OSC) for 1 hour cumulative time at the given temperature profile, for 10 hours cumulative time with the device in reset at the given temperature profile. Remaining time as defined in Section 3.3: Operating conditions. 3. The maximum input voltage on an I/O pin depends on the maximum associated I/O supply voltage. For the injection current condition on a pin, the voltage is equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations. 4. The relative value can be exceeded if design measures are taken to ensure the injection current limitation (parameter IINJ). 5. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time. 6. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 3.8.3: I/O pad current specifications. It is important to ensure that the sum of the injected currents does not exceed the current induced by the application on this supply domain. Exceeding such a value can cause the voltage on the supply domain to raise above the absolute maximum rating of this supply domain. 7. Solder profile per IPC/JEDEC J-STD-020D. 8. Moisture sensitivity per JDEC test method A112. Related links

3.3 Operating conditions on page 12

3.8.3 I/O pad current specifications on page 24

3.8.1 I/O input DC characteristics on page 18

3.12.1 ADC input description on page 35

3.12.2 SARADC 12-bit electrical specification on page 36

3.3 Operating conditions

The table below describes the operating conditions for the device, and for which all the specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed. Table 5. Operating conditions DS13808 - Rev 8 page 12/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max VDD_HV_SD_DAC_COMP SR P High voltage power supply for SDADC, DAC and comparator — 3.15(6) — 3.45(7) V VDD_HV_FLA SR P High voltage power supply for HV_REFH_SD SR P SDADC supply reference voltage(8) — 2.9 — 3.45 V HV_REFH_SD - VDD_HV_SD_DAC_COMP SR D SDADC reference differential voltage — — — 0 (Not allowed) mV HV_REFL_SD SR P SDADC ground reference voltage — — 0 — V HV_REFL_SD - VSS SR D SDADC ground differential voltage — –25 — 25 mV HV_REFH_SAR SR P SARADC supply reference voltage(9) — 2.7 — 3.45 V HV_REFH_SAR - VDD_HV_SAR SR D SARADC reference differential voltage — — — 0 (Not allowed) mV HV_REFL_SAR SR P SARADC ground reference voltage and SARADC analog ground — 0 — 0.1 V HV_REFL_SAR - VSS SR D SARADC ground differential voltage — –25 — 25 mV HV_REFL_DAC_COMP SR P Ground reference for DAC and comparator — — 0 — V HV_REFH_DAC_COMP SR P Voltage reference for DAC and comparator Reference to HV_REFL_DAC_COMP 3.0 — 3.45 V HV_REFL_DAC_COMP - VSS SR D DAC and comparator ground reference differential voltage — –25 — 25 mV VRAMP_HV SR D Slew rate on HV power supply — 33 — 100 V/ms VIN SR P I/O input voltage range and high voltage power supply for internal power management unit — 0 — VDD_HV_IO V IINJ1 SR T Injection current (per pin) without performance degradation (10)(11)(12) Digital pins and analog pins –3 — 3 mA IINJ2 SR D Dynamic injection current (per pin) with performance degradation(10)(13) Digital pins and analog pins –10 — 10 mA 1. The ranges in this table are design targets and actual data may vary in the given range. 2. Maximum operating frequency is applicable to the cores and platform of the device. Refer to the device reference manual, Clocking chapter, for more information on the clock limitations for the various IP blocks on the device. 3. Core voltage is measured on device pin to ensure published silicon performance. This value is provided as information, but it is controlled internally by PMU. External low voltage supply is not supported in functional mode. 4. In the range [1.265-1.225] V the device functionality and specifications are ensured, but this interval is to be considered as a transient, in accordance with the mission profile, to ensure the product reliability. In the range [1.225-1.222] V, the device functionality is ensured, but this interval is to be considered as a transient. In the range [1.222-1.188] V, the device functionality is granted and the device is expected to receive a flag by the internal LVD119 monitors to warn that the regulator providing the VDD_LV supply, exited the expected operating conditions. If the internal LVD119 monitors are disabled by the application, then an external voltage monitor with minimum threshold of VDD_LV(min) = 1.19 V measured at the device pad, has to be implemented. Refer to Section 3.13.3: Voltage monitors for the list of available internal monitors and to the device reference manual for the configurability of the monitors. SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 13/99

1. In the range [1.31-1.345] V the device functionality and specifications are ensured, but this interval is to be considered as a transient, in accordance with the mission profile, to ensure the product reliability. In the range [1.345-1.361] V, the device functionality is ensured, but this interval is to be considered as a transient. In the range [1.361-1.399] V, the device functionality is granted and the device is expected to receive a flag by the internal HVD140 monitors to warn that the regulator providing the VDD_LV supply, exited the expected operating conditions. Refer to Section 3.13.3: Voltage monitors for the list of available internal monitors and to the device reference manual for the configurability of the monitors. Possible permanent failure over 1.4 V. 6. In the range [3.012-3.15] V, the device functionality is ensured, but this interval is to be considered as a transient, in accordance with the mission profile, to ensure the product reliability. In the range [3.012-2.898] the device functionality is granted and the device is expected to receive a flag by the internal LVD290 monitors . Refer to Section 3.13.3: Voltage monitors for the list of available internal monitors and to the Reference Manual for the configurability of the monitors. 7. In the range [3.45-3.651] V, the device functionality is ensured, but this interval is to be considered as a transient, in accordance with the mission profile, to ensure the product reliability. In the range [3.651-3.799] the device functionality is granted and the device is expected to receive a flag by the internal UVD380 monitors . Refer to Section 3.13.3: Voltage monitors for the list of available internal monitors and to the Reference Manual for the configurability of the monitors. 8. To be always ensured VDD_HV_SD_DAC_COMP ≥ HV_REFH_SD. 9. To be always ensured VDD_HV_SAR ≥ HV_REFH_SAR. 10. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 3.8.3: I/O pad current specifications. 11. The I/O pins on the device are clamped to the I/O supply rails by ESD protection. When the voltage of the input pins is above the supply rail, the current is injected through the clamp diode to the supply rails, with diode voltage drop varying across the temperature. 12. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. Refer to Section 3.2: Absolute maximum ratings for maximum input current for reliability requirements. 13. Positive and negative dynamic current injection pulses are allowed up to this limit, with different specifications for I/O, ADC accuracy and analog input. Refer to the dedicated chapters for the different specification limits. See the Table 4. Absolute maximum ratings for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011), Pulse 2a(ISO 7637-2:2011

Table 6. TCM wait state configuration Table 7. PRAM wait state configuration

3.2 Absolute maximum ratings on page 11

3.13.3 Voltage monitors on page 57

DS13808 - Rev 8 page 14/99

3.3.1 Power domains and power-up/-down sequencing

The following table shows the constraints and relationships for the different power domains. Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as well as during normal device operation. Table 8. Device supply relation during power-up/-down sequence SR5E1E5, SR5E1E7 I/O definition Excel® file attached to the “Architecture mapping tables” technical note.

3.4 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device. Table 9. ESD ratings

1. The device does not meet the device specification requirements after exposure to ESD pulses. This includes the complete DC parametrics
2. All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits.
3. This parameter tested in conformity with ANSI/ESD STM5.1-2007 electrostatic discharge sensitivity testing.
4. This parameter tested in conformity with ANSI/ESD STM5.3-1990 charged device model - component level.

DS13808 - Rev 8 page 15/99

3.5 Electromagnetic emission characteristics

EMC measurements at integrated circuit level IEC standards can be requested to STMicroelectronics. The 300 MHz nominal frequency is not suggested as the operating frequency due to possible EMC emissions in the GNSS band. The suggested (max) operating frequency is 306.7 MHz, refer to the "Clock tree" and PLL divider registers (PLL0DV and PLL1DV) in the reference manual.

3.6 Temperature profile

The device is qualified in accordance to AEC-Q100 Grade1 and customers’ requirements.

3.7 Device consumption

The total device consumption seen from the HV domain is the sum of the total dynamic current on the high- voltage supply and the leakage current seen on the high-voltage domain (from LV domain through SMPS) for the selected temperature. So, it is: ITOT = IDD_HV + IDD_HV_SMPS_LKG. The following table reports each single contributor factor to the device consumption. Refer to Figure 3. Device consumption measurement to see where each contributor is measured. Table 10. Device consumption

1. The ranges in this table are design targets and actual data may vary in the given range.

DS13808 - Rev 8 page 16/99

1. Motor control application configured to drive single field-oriented control (FOC) 3-phase permanent magnet motors with ICS topology power stage (in open-loop). Position sensors used are encoder and sensor-less algorithms. IPs involved: Single core, 2× ADC channels, 6× timer channels (PWM generation), 2× timer channels (encoder), UART, DAC, CORDIC, xx I/O pins (yy configured as toggling output pins at different frequencies), GPIOs. 3. Full case profile - 2× M7 cores in lockstep. IPs involved: 5× SARADCs, 2× SDADCs, COMPs, 6× timer channels (PWM generation), 24× HRTIM channels (PWM generation), UART, DAC, CORDIC, 2× SPIs, CAN, 65 I/O pins (40 configured as toggling output pins at different frequencies), GPIOs. 4. IDD_HV_SMPS__LKG (leakage current) and IDD_HV_SMPS (dynamic current) are reported as separate parameters, to give an indication of the consumption contributors. The tests used in validation, characterization and production are verifying that the total consumption (leakage+dynamic) is lower than or equal to the sum of the maximum values provided (IDD_HV_SMPS__LKG + IDD_HV_SMPS ). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and the software profile used. 5. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and it is computed in the dynamic IDD_LV and IDD_HV parameters. 6. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the consumption contributors. The tests used in validation, characterization and production verify that the total consumption (leakage+dynamic) is lower than or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and the software profile used. 7. Main core dynamic consumption contribution based on motor control profile. Dedicated I/D-caches and I/D-TCMs contribution are not included. 8. Dynamic current reduction with the main core in CSleep, based on the full case profile. 9. The current spike can occur during a normal operation that is above the average current, measured on the application-specific pattern. Internal schemes must be used (for example frequency ramping, feature enable) to ensure that incremental demands are made on the external power supply. Refer to Section 3.13: Power management for the details and the external component requirements. 10. This specification is the maximum value and is a boundary for the dl specification. 11. Condition 1: for power, on period from 0 V up to normal operation with reset asserted. Condition 2: from reset asserted until PLL running free. Condition 3: increasing PLL from free frequency to full frequency. Condition 4: reverse order for power down to 0 V. 12. IDDOFF is the minimum ensured consumption of the device during power-up.

Figure 3. Device consumption measurement DS13808 - Rev 8 page 17/99

3.8 I/O pad specification

The following table describes the different pad type configurations. Table 11. I/O pad specification descriptions controlled current to reduce electromagnetic emission. Fast configuration Provides fast transition speed; used for fast interface. Used for fast interface requiring fine control of rising/falling edge jitter. Input only pads These low input leakage pads are associated with the ADC channels. device reference manual for the available drive configurations for each I/O pin.

3.8.1 I/O input DC characteristics

The following table provides input DC electrical characteristics, as described in the following figure. Figure 4. I/O input electrical characteristics Table 12. I/O input electrical characteristics DS13808 - Rev 8 page 18/99

Symbol C Parameter Conditions Value Unit Min Typ Max Automotive Vihaut(2) SR P Input high level AUTO VDD_HV_IO = 3.3 V ± 5% 0.75 * VDD_HV_IO — VDD_HV_IO + 0.3 V Vilaut(3) SR P Input low level AUTO VDD_HV_IO = 3.3 V ± 5% -0.3 — 0.35 * VDD_HV_IO V Vhysaut(4) CC C Input hysteresis AUTO VDD_HV_IO = 3.3 V ± 5% 0.11 * VDD_HV_IO — — V CMOS Vihcmos SR P Input high level CMOS(1) — 0.65 * VDD_HV_IO — VDD_HV_IO + 0.3 V Vilcmos SR P Input low level CMOS(1) — -0.3 — 0.35 * VDD_HV_IO V Vhyscmos CC C Input hysteresis CMOS(1) — 0.10 * VDD_HV_IO — — V Common ILKG CC P Pad input leakage(1) Input-only pads, static leakage characteristics VDD_HV_IO = 3.3 V ± 5% TJ = 150°C — — 200 nAP Fast pads, static leakage characteristics VDD_HV_IO = 3.3 V ± 5% TJ = 150°C — — 800 P Very fast pads, static leakage characteristics VDD_HV_IO = 3.3 V ± 5% TJ = 150°C — — 1000 CP1 CC D Pad capacitance — — — 3.5 pF Vdrift CC D Input Vil/Vih temperature drift In a 1 ms period, with a temperature variation <30°C -50 — +50 mV 1. In the case of current injection pulses on one pad under the conditions and limits described in the parameter IINJ2 in Section 3.2: Absolute maximum ratings, other pads of the same supply segment have a drift of 4 % above the maximum Vil and 4 % below the minimum Vih limits. Similarly the parameter Vhys is decreased by 4 %. 2. A good approximation of the variation of the minimum value with the supply is given by the formula: 3.3 V range: VIHAUT = 0.75 × VDD_HV_IO 3. A good approximation of the variation of the maximum value with the supply is given by the formula: 3.3 V range: VILAUT = 0.35 × VDD_HV_IO 4. A good approximation of the variation of the minimum value with the supply is given by the formula: 3.3 V range: VHYSAUT = 0.11 × VDD_HV_IO Table 13. I/O pull-up/pull-down electrical characteristics

1. Maximum current when forcing a change in the pin level opposite to the pull configuration.
2. Minimum current when keeping the same pin level state as the pull configuration.

DS13808 - Rev 8 page 19/99

3.8.2 I/O output DC characteristics

The figure below describes the output DC electrical characteristics. Figure 5. I/O output DC electrical characteristics definition The following tables provide DC characteristics for bidirectional pads.

3.15.1.2 JTAG interface timing on page 64

DS13808 - Rev 8 page 20/99

3.8.2.1 Slow I/O output characteristics

The following table provides output driver characteristics for I/O pads in slow configuration. Table 14. Slow I/O output characteristics DS13808 - Rev 8 page 21/99

3.8.2.2 Medium I/O output characteristics

The following table provides output driver characteristics for I/O pads in medium configuration. Table 15. Medium I/O output characteristics DS13808 - Rev 8 page 22/99

3.8.2.3 Fast I/O output characteristics

The following table provides output driver characteristics for I/O pads in fast configuration. Table 16. Fast I/O output characteristics DS13808 - Rev 8 page 23/99

3.8.2.4 Very fast I/O output characteristics

The following table provides output driver characteristics for I/O pads in very fast configuration. Table 17. Very fast I/O output characteristics

3.8.3 I/O pad current specifications

“Architecture mapping tables” technical note. The table below provides I/O consumption figures. remain below the IDYNSEG maximum value. DS13808 - Rev 8 page 24/99

Table 18. I/O consumption

1. Average consumption in one pad toggling cycle.

DS13808 - Rev 8 page 25/99

1. The I/O supplies are well distributed around the device to sustain the different drive capability of each pad. The only limitation is related (for all packages) to the Very Fast configuration for the segment including the JTAG pads untill PAD_PG[5..12]: PAD_PG[5..12] can be configured in very fast mode, toggling at the same time, but JTAG pads must not be used, or vice versa. 3. The stated maximum values represent the peak consumption that lasts only a few ns during the I/O transition. When possible (timed output) it is recommended to delay the transition between pads by a few cycles to reduce noise and consumption. Related links

3.9 Reset pad (RESETn) electrical characteristics

The device implements a reset pin pad: RESETn is configured as a reset input/output. The configuration is read during the boot initialization process as described in the device reference manual, Reset and boot chapter. When samples are delivered, in the default configuration, RESETn pin does not require active control. The following figure describes RESETn behavior during the power-up sequence. Figure 6. RESETn behavior during power-up sequence

1. The amplitude of the low pulse is too low: it is filtered by input buffer hysteresis. The device remains in current
2. The duration of the low pulse is too short: it is filtered by low-pass filter. The device remains in current state.
3. Low pulse is generating a reset:

a. Signal is low but initially filtered during at least WFRST. The device remains initially in the current state. previous mode depending on extra conditions (temperature, voltage, device). c. Signal asserted for longer than WNFRST. The device is under reset. DS13808 - Rev 8 page 26/99

Figure 7. Input reset filter Table 19. Reset pad electrical characteristics

1. IOl_R applies to RESETn: strong pull-down is active until the DCF containing the RESETn configuration is read. Refer to the device

reference manual, Reset and boot chapter.

1. Maximum current when forcing a change in the pin level opposite to the pull configuration.
2. Minimum current when keeping the same pin level state as the pull configuration.

DS13808 - Rev 8 page 27/99

Table 20. RESETn settings with an external pull-up to ensure correct reset exit sequence. The recommended value is 4.7 kΩ. DS13808 - Rev 8 page 28/99

3.10 PLLs

Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary clocks on the device. The figure below depicts the integration of the two PLLs. Refer to the device reference manual for more detailed schematic. Figure 8. PLLs integration DS13808 - Rev 8 page 29/99

3.10.1 PLL0

Table 21. PLL0 electrical characteristics

1. PLL0IN clock retrieved directly from either internal IRCOSC or external XOSC clock. Input characteristics are granted when the internal

oscillator or external oscillator is used in functional mode.

1. Since XOSC the max frequency is 40 MHz, the 40-56 MHz range can only be reached with external reference clock (XOSC bypass).
2. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency obeys the maximum input frequency limit set for PLL1 (refer

to fPLL1IN in Table 22. PLL1 electrical characteristics).

3.10.2 PLL1 on page 31

DS13808 - Rev 8 page 30/99

3.10.2 PLL1

PLL1 is a frequency modulated PLL with spread spectrum clock generation (SSCG) support. Table 22. PLL1 electrical characteristics

1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when using internal

PPL0 or external oscillator is used in functional mode.

1. The device maximum operating frequency FSYS (max) includes the frequency modulation. If center modulation is selected, the FSYS must

manual for the PLL programming details.

3.10.1 PLL0 on page 30

DS13808 - Rev 8 page 31/99

3.11 Oscillators

3.11.1 Low-speed internal RC oscillator (LSI)

Table 23. 1024 kHz internal RC oscillator electrical characteristics

3.11.2 External crystal oscillator 40 MHz (XOSC)

Table 24. External 40 MHz oscillator electrical specifications DS13808 - Rev 8 page 32/99

Symbol C Parameter Conditions Value Unit Min Typ Max gm CC P Oscillator transconductance mA/V TJ = –40°C to 150°C fXTAL = 30 - 40 MHz XOSC_freq_sel[1:0]= 11 12.70 — 46.15 VXTAL CC T Oscillation amplitude on the XTAL pin after startup(9) TJ = –40°C to 150°C, pk-pk @40MHz 0.5 — VDD_HV_OSC V 1. The range is selectable by UTEST miscellaneous DCF clients XOSC_FREQUENCY [1:0]. 2. Refer to Table 25. Crystal parameters and load conditions for supported crystal parameters and load conditions. 3. The XTAL frequency, if used to feed the PLL0 (or PLL1), has to obey the minimum input frequency limit set for PLL0 (or PLL1). 4. Proper PC board layout procedures must be followed to achieve these specifications. 5. This value is determined by the crystal manufacturer and board design. 6. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value. 7. Applies to an external clock input and not to crystal mode. 8. See the crystal manufacturer’s specification for recommended load capacitor (CL) values. Total capacitance on XTAL net must be 2*CL. On- chip stray capacitance (CS_EXTAL/CS_XTAL) and PCB capacitance must be accounted when selecting a load capacitor value. External capacitance or integrated load capacitor value can be used. Integrated load capacitance can be selected via software to match the crystal manufacturer’s specification. The stray capacitance (Cpar) on chip value here reported, takes into account the sum of total parasitic capacitance inside the SOC (IP, routing inside SOC, IO pad) + package. 9. Amplitude on the XTAL pin after startup is determined by the automatic level control circuit (ALC) block. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation to reduce power, distortion, and RFI, and to avoid over driving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions. Figure 9. Equivalent mode of crystal

• C0 is the shunt or static capacitance of the crystal. The parameter equals the sum of capacitance measured from pin to pin, including the electrode and the mounting structure. This capacitance is usually specified as a maximum value, for example, 2 pF maximum.
• Lm, Rm, and Cm are in the motional arm of the crystal. Their circuit affects only exist when the crystal is oscillating. – Lm, the motional inductance, is determined by the mechanical mass of quartz in motion. – Cm is determined by the stiffness of the quartz (constant), the area of the electrode, and the thickness and shape of the quartz wafer. Cm is dependent on the specified frequency of the crystal. Cm is usually less than 0.02 pF. – Rm is the equivalent series resistance when oscillating. It is a function of mechanical losses during vibration. Low resistance indicates low mechanical losses. The lower the resistance is, the more easily the crystal oscillates. Rm is usually specified as a maximum value, for example, 50 maximum. Internal trimmable capacitance Two capacitance blocks are connected between A and AGND and ZO and AGND inside the oscillator. For the internal capacitance array to be selected, ext_cload_en should be low. Capacitance is implemented using metal fringe. The capacitance offered by this array is decided by load_cap_sel[4:0]. The formula to calculate the capacitance offered is C_var = n.Cu SR5E1E3, SR5E1E5, SR5E1E7

DS13808 - Rev 8 page 33/99

Where,

• Cu = unit capacitance (for a typical corner, Cu = 0.48 pF. Across the process, the variation is ± 10%)
• n = load_cap_sel[4] × 24 + load_cap_sel[3] × 23 + load_cap_sel[2] × 22 + load_cap_sel[1] × 21 + load_cap_sel[0] × 20 For example:
• For load_cap_sel[4:0]=00000, C_var = 0 pF at A & ZO each.
• For load_cap_sel[4:0]=10000, C_var = 7.68 pF at A & ZO each.
• For load_cap_sel[4:0]=11111, C_var = 14.88 pF at A & ZO each. Refer to the UTEST miscellaneous DCF client described in the device reference manual (chapter Device configuration format DCF records).

Table 25. Crystal parameters and load conditions

1. Crystal frequency range values are related to FXTAL defined by freq_sel[1:0] settings (refer to Table 24. External 40 MHz

• E SR = R m × 1 + C 0 C L
• CL is the load capacitance.
• C0 is the shunt capacitance.
• CA = CB = 2 × CL. 3. CA, CB, and C0 include the parasitic capacitance due to the crystal, PCB board traces, package parasitics etc.

3.11.3 Internal RC 16 MHz oscillator (IRCOSC)

Table 26. Internal RC oscillator electrical specifications DS13808 - Rev 8 page 34/99

1. The additional contribution of the core logic clocked by the RCOSC16M affects the RCOSC16M consumption. This core logic cannot be turned off during the measurement at device level. In any case, the design specifies the parameter at 1200 µA.

3.12 Analog subsystem

The SR5E1E3, SR5E1E5, SR5E1E7 analog subsystem contains:

• 5 SARADC modules with up to eight channels coming from pads,
• 2 SDADC modules,
• 8 Fast-DACs,
• 8 analog comparators,
• 2 buffered-DACs that is with buffer to bring analog output on pads,
• 1 temperature sensor,
• 1 ADCBIAS_COMP module to generate 4 reference voltages for runtime diagnosis of comparators,
• 1 ADCBIAS_SAR module to generate 4 reference voltages for runtime diagnosis of SAR_ADCs in single ended mode.

3.12.1 ADC input description

The figure below shows the input equivalent circuit for SARn channels. Figure 10. Input equivalent circuit (Fast SARn channels) The above figure can be used as approximation circuitry for external filtering definition.

• For injection current 1, refer to IINJ1 in Section 3.3: Operating conditions,
• For pad capacitance 1, refer to CP1 in Section 3.8.1: I/O input DC characteristics. SR5E1E3, SR5E1E5, SR5E1E7

DS13808 - Rev 8 page 35/99

Table 27. ADC pin specification

1. All specifications in this table valid for the full input voltage range for the analog inputs.

3.13.1 Power management integration on page 52

3.12.2 SARADC 12-bit electrical specification

DAC. The SARn architecture allows input channel multiplexing. Table 28. SARn ADC electrical specification DS13808 - Rev 8 page 36/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max tADCEVAL(5) SR D ADC evaluation time 10-bit configuration 10.5/fADCK µs— — IADV_S CC P VDD_HV_SAR power supply current Run mode (for each ADC) — — 0.46 mA D Power down mode (for each ADC) — — 0.01 TUE12(6) CC P Total unadjusted error in 12-bit configuration(7) TJ < 150°C in all conditions -7 — 7 LSB (12b) TUE10(6) CC D Total unadjusted error in 10-bit configuration(7) TJ < 150°C in all conditions -4 — 4 LSB (10b) TUEINJ2 CC T TUE degradation addition, due to current injection in IINJ2 range(8) See Table 4. Absolute maximum ratings, IINJ2 parameter. +10 LSB DNL(7) CC P Differential non- linearity In all VDD_HV_SAR voltage range. -1 — 2 LSB (12b) 1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. All specifications in this table are valid for one ADC operating at a time. 2. Max frequency can be reached under specific device clocks configuration. Refer to the device reference manual, Clocking chapter for details. 3. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Refer to Figure 10. Input equivalent circuit (Fast SARn channels) for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

1. The minimum sampling time of 2.5 ADC clock cycles requires the setting of the ADC_SMPR1.SMPPLUS bit to 1. The overal minimum

sampling time is 3.5/fADCK µs.

1. It is referring to the "successive approximation time (Tsar)" defined in the device reference manual, ADC timing chapter.
2. TUE and DNL are granted with injection current within the range defined in Table 27. ADC pin specification for parameters classified as T
3. All channels of all 12-bit SARADCs are impacted with the same degradation, independently of the ADC and the channel subject to current

DS13808 - Rev 8 page 37/99

3.12.3 SDADC electrical specification

The SDn ADCs are sigma delta 16-bit analog-to-digital converters with up to 300 Ksps output rate. Note: The SDADCs are not available in the eTQFP100 package. Table 29. SDn ADC electrical specification DS13808 - Rev 8 page 38/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max SNRDIFF150 CC C Signal-to-noise ratio in differential mode 150 ksps output rate In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 2 TJ < 150°C dBFS 77 — — C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 4 TJ < 150°C 74 — — C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 8 TJ < 150°C 71 — — D In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 16 TJ < 150°C 68 — — SNRDIFF333 CC P Signal-to-noise ratio in differential mode 333 ksps output rate In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 1 TJ < 150°C 71(11) — — dBFS C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 2 TJ < 150°C 68 — — C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 4 TJ < 150°C 65 — — C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 8 TJ < 150°C 62 — — D In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 16 TJ < 150°C 60 — — SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 39/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max SNRSE333 CC P Signal-to-noise ratio in single-ended mode 333 ksps output rate In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 1 TJ < 150°C 65(11) — — dBFS C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 2 TJ < 150°C 62 — — C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 4 TJ < 150°C 59 — — C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 8 TJ < 150°C 56 — — D In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 16 TJ < 150°C 54 — — SNRSE150 CC P Signal-to-noise ratio in single-ended mode 150 ksps output rate In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 1 TJ < 150°C 74(11) — — dBFS C In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 2 TJ < 150 °C 71 — — In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 4 TJ < 150 °C 68 — — In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 8 TJ < 150 °C 65 — — SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 40/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max SNRSE150 CC D Signal-to-noise ratio in single-ended mode 150 ksps output rate dBFS In all VDD_HV_SD_DAC_COMP supply range. HV_REFH_SD = VDD_HV_SD_DAC_COMP GAIN = 16 TJ < 150 °C 62 — — SFDR CC P Spurious free dynamic range GAIN = 1 60 — — dBc C GAIN = 2 60 — — C GAIN = 4 60 — — C GAIN = 8 60 — — D GAIN = 16 60 — — ZDIFF CC D Differential input impedance (fADCD_M = 8 MHz) GAIN = 1 360 450 540 kΩ D GAIN = 2 224 280 336 D GAIN = 4 128 160 192 D GAIN = 8 65 85 105 D GAIN = 16 65 85 105 ZCM CC D Common mode input impedance (fADCD_M = 8 MHz) GAIN = 1 450 560 670 kΩ D GAIN = 2 340 430 520 D GAIN = 4 250 310 370 D GAIN = 8 170 210 250 D GAIN = 16 170 210 250 RBIAS CC D Bias resistance — 120 160 200 kΩ ΔRBIAS CC D RBIAS positive/negative terminal impedance mismatch — -5 — +5 % VBIAS CC D Bias voltage — — (VDD_HV_SD_DAC_COMP – VSS)/2 — V ΔVINTCM CC D Common mode input reference voltage — –12 (VDD_HV_SD_DAC_COMP + VSS)/2 +12 % δVBIAS CC D Bias voltage accuracy — –2.5 — +2.5 % Vcmrr CC T Common mode rejection ratio — 40 — — dB RCaaf SR D Anti-aliasing filter External series resistance — — 20 kΩ CC D Filter capacitances 180 — — pF fPASSBAND CC D Pass band(13) Default filter mode Bypass FIR mode 0.01 — 0.333 * fADCD_S kHz Modified bandwidth mode — 0.166 * fADCD_S External filter mode (OSR = 75) — 0.066 * fADCD_S External filter mode (All OSR, expect 75) — 0.083 * fADCD_S δRIPPLE CC D Pass band ripple(14) 0.333 * fADCD_S –1 — 1 % Frolloff CC D Stop band attenuation Default filter mode(15) [0.5 * fADCD_S, 1.0 * fADCD_S] 1 — — dB SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 41/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max Frolloff CC D Stop band attenuation Default filter mode(15) [1.0 * fADCD_S, 1.5 * fADCD_S] dB 40 — — [1.5 * fADCD_S, 2.0 * fADCD_S] 47 — — [2.0 * fADCD_S, 2.5 * fADCD_S] 54 — — [2.5 * fADCD_S, fADCD_M/2] 64 — — Frolloff CC D Stop band attenuation Modified bandwidth mode(15) [0.25 * fADCD_S, 0.5 * fADCD_S] 40 — — dB [0.5 * fADCD_S, 0.75 * fADCD_S] 55 — — [0.75 * fADCD_S, 1.0 * fADCD_S] 86 — — [1.0 * fADCD_S, 1.25 * fADCD_S] 109 — — [1.25 * fADCD_S, fADCD_M/2] 99 — — Frolloff CC D Stop band attenuation External filter mode(15) [0.5 * fADCD_S, 1.0 * fADCD_S] 2 — — dB [1.0 * fADCD_S, 1.5 * fADCD_S] 11 — — [1.5 * fADCD_S, 2.0 * fADCD_S] 31 — — [2.0 * fADCD_S, 2.5 * fADCD_S] 44 — — [2.5 * fADCD_S, fADCD_M/2] 39 — — Frolloff CC D Stop band attenuation Bypass FIR mode(15) [0.5 * fADCD_S, 1.0 * fADCD_S] 3 — — dB [1.0 * fADCD_S, 1.5 * fADCD_S] 15 — — [1.5 * fADCD_S, 2.0 * fADCD_S] 41 — — [2.0 * fADCD_S, 2.5 * fADCD_S] 59 — — [2.5 * fADCD_S, fADCD_M/2] 52 — — δGROUP CC D Group delay Default filter mode(15) Within pass band – Tclk is time period of fADCD_M /2 freq. = 2/ fADCD_M — — — — OSR = 24 — — 197.9 Tclk OSR = 28 — — 230 OSR = 32 — — 262.1 OSR = 36 — — 294.2 OSR = 40 — — 326.3 OSR = 44 — — 358.4 OSR = 48 — — 390.4 OSR = 56 — — 454.6 OSR = 64 — — 518.8 OSR = 72 — — 582.9 OSR = 75 — — 509.1 OSR = 80 — — 647.1 OSR = 88 — — 711.3 OSR = 96 — — 775.4 OSR = 112 — — 903.8 OSR = 128 — — 1032.1 OSR = 144 — — 1160.4 SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 42/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max δGROUP CC D Group delay Default filter mode(15) OSR = 160 Tclk — — 1288.8 OSR = 176 — — 1417.1 OSR = 192 — — 1545.4 OSR = 224 — — 1802.1 OSR = 256 — — 2058.8 OSR = 512 — — 4112.1 OSR = 1024 — — 8218.7 δGROUP CC D Group delay Modified bandwidth mode(15) Within pass band – Tclk is time period of fADCD_M /2 freq. = 2/ fADCD_M — — — — OSR = 24 — — 217.3 Tclk OSR = 28 — — 252 OSR = 32 — — 286.6 OSR = 36 — — 321.3 OSR = 40 — — 355.9 OSR = 44 — — 390.6 OSR = 48 — — 425.3 OSR = 56 — — 494.6 OSR = 64 — — 563.9 OSR = 72 — — 633.3 OSR = 75 — — 589 OSR = 80 — — 702.6 OSR = 88 — — 771.9 OSR = 96 — — 841.3 OSR = 112 — — 979.9 OSR = 128 — — 1118.6 OSR = 144 — — 1257.3 OSR = 160 — — 1395.9 OSR = 176 — — 1534.6 OSR = 192 — — 1673.2 OSR = 224 — — 1950.6 OSR = 256 — — 2227.9 OSR = 512 — — 4446.5 OSR = 1024 — — 8883.7 δGROUP CC D Group delay Bypass FIR mode(15) Within pass band – Tclk is time period of fADCD_M /2 freq. = 2/ fADCD_M — — — — OSR = 24 — — 73.7 Tclk OSR = 28 — — 85.2 OSR = 32 — — 96.8 OSR = 36 — — 108.4 SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 43/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max δGROUP CC D Group delay Bypass FIR mode(15) OSR = 40 Tclk — — 119.9 OSR = 44 — — 131.5 OSR = 48 — — 143.1 OSR = 56 — — 166.2 OSR = 64 — — 189.3 OSR = 72 — — 212.4 OSR = 75 — — 198.2 OSR = 80 — — 235.6 OSR = 88 — — 258.7 OSR = 96 — — 281.8 OSR = 112 — — 328.1 OSR = 128 — — 374.4 OSR = 144 — — 420.6 OSR = 160 — — 466.9 OSR = 176 — — 513.1 OSR = 192 — — 559.4 OSR = 224 — — 651.9 OSR = 256 — — 744.4 OSR = 512 — — 1484.6 OSR = 1024 — — 2964 δGROUP CC D Group delay External filter mode(15) Within pass band – Tclk is time period of fADCD_M /2 freq. = 2/ fADCD_M — — — — OSR = 24 — — 31.25 Tclk OSR = 28 — — 36.25 OSR = 32 — — 41.25 OSR = 36 — — 46.25 OSR = 40 — — 51.25 OSR = 44 — — 56.25 OSR = 48 — — 61.25 OSR = 56 — — 71.25 OSR = 64 — — 81.25 OSR = 72 — — 91.25 OSR = 75 — — 76.25 OSR = 80 — — 101.25 OSR = 88 — — 111.25 OSR = 96 — — 121.25 OSR = 112 — — 141.25 OSR = 128 — — 161.25 OSR = 144 — — 181.25 OSR = 160 — — 201.25 SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 44/99

Symbol (1) C Parameter Conditions Value Unit Min Typ Max δGROUP CC D Group delay External filter mode(15) OSR = 176 Tclk — — 221.25 OSR = 192 — — 241.25 OSR = 224 — — 281.25 OSR = 256 — — 321.25 OSR = 512 — — 641.25 OSR = 1024 — — 1281.25 fHIGH CC D High pass filter 3dB frequency Enabled — — 16e-5*fA DCD_S tSTARTUP CC D Start-up time from power down state — — — 100 µs tLATENCY CC D Latency between input data and converted data (input mux not changed)(16) HPF = ON — — δGROUP + 2/ fADCD_S HPF = OFF — — δGROUP + 1/ fADCD_S tSETTLING CC D Settling time after mux change Analog inputs are muxed HPF = ON — — 2*δ GROUP + 3*1/ fADCD_S HPF = OFF — — 2*δ GROUP + 2*1/ fADCD_S tODRECOVERY CC D Overdrive recovery time After input comes within range from saturation HPF = ON — — 2*δ GROUP + fADCD_S HPF = OFF — — 2*δ GROUP + fADCD_S CS_D CC D SDADC sampling capacitance after sampling switch(17) GAIN = 1, 2, 4, 8 — — 160*GAI N fF D GAIN = 16 — — 1280 fF IADV_BIAS CC D Bias consumption At least 1 SDADC enabled — — 1 mA IADV_D CC C VDD_HV_SD_DAC_COMP Power supply current (each ADC) SDADC enabled — — 2.5 mA IADR_BIAS CC D BIAS module current(18) — — — 4 µA IADR_SD CC T Single SD reference current — — — 2 µA 1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the signal is only ‘clipped’. 3. VINP is the input voltage applied to the positive terminal of the SDADC. 4. VINM is the input voltage applied to the negative terminal of the SDADC. 5. Sampling is generated internally fSAMPLING = fADCD_M/2. SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 45/99

1. Maximum input of 166.67 KHz supported with reduced accuracy. See SNR specifications. Tested in production till 20 kHz, covered at bench till 75 kHz (as T parameter). 7. Configured oversampling rate: SDADC_MCR[PDR] = 24. 8. Calibration of gain is possible when gain = 1. Offset calibration should be done with respect to 0.5*HV_REFH_SD for "differential mode" and "single-ended mode with negative input = 0.5*HV_REFH_SD". Offset calibration should be done with respect to 0 for "single-ended mode with negative input = 0". Both offset and gain calibration is ensured for ±10% variation of HV_REFH_SD, ±10% variation of VDD_HV_SD_DAC_COMP, on all operating temperature ranges. 9. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset error. 10. Offset and gain error due to temperature drift can occur in either direction (±) for each of the SDADCs on the device. 11. This value is tested in production on each individual device to ensure a correct screening with a tolerance of ~2 dBFS, due to the noise. This value (without tolerance) is however ensured by the measurement carried out on a small number of samples in the analog validation environment. Therefore, the performance is specified by bench, while the screening is specified by tester. 12. All channels of all SDADCs are impacted with same degradation, independently from the ADC and the channel subject to current injection. 13. SNR value ensured only if external noise on the ADC input pin is attenuated by the required SNR value in the frequency range of fADCD_M - fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and fADCD_S is the output sample frequency. A proper external input filter must be used to remove any interfering signals in this frequency range. 14. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB. 15. For details, refer to Section 3.12.4: SDADC filter modes. 16. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers. The time elapsed between data availability at pin and internal S/D module registers is given by the below formula: REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK where fADCD_S is the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and fPBRIDGEx_CLK is the frequency of the peripheral bridge clock feeds to the SDADC module. The (~+1) symbol refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the signal during clock domain crossing. Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received from the SDADC module. 17. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before sampling switch. 18. Single bias module providing reference to 2 S/D.

Figure 11. S/D impedance generic model DS13808 - Rev 8 page 46/99

3.12.4 SDADC filter modes on page 47

3.12.4 SDADC filter modes

The following table describes the 4 SDADC filter modes which are controlled by bits BANDSEL, FSEL and EXTFILTER of the module configuration register (MCR). Gain calibration must be done using the same OSR configuration, FIR filter selection mode and output data rate band selection as the target application, since full-scale values may vary slightly with these settings (normal mode and bypass FIR mode). Refer to Table 31. Digital output codes in full scale for full-scale values (with MCR[GECEN] = 1) with different OSR settings, both for normal and bypass FIR modes. Table 30. Filter modes

1. For details, refer to the device reference manual.

when input signal is full range. Table 31. Digital output codes in full scale DS13808 - Rev 8 page 47/99

MCR[FSEL] = 1 MCR[GECEN] = 1 MCR[FSEL] = 0 MCR[BANDSEL] = 0 MCR[GECEN] = 1 MCR[FSEL] = 0 MCR[BANDSEL] = 1 MCR[GECEN] = 1 176 29121 31040 31054 192 29160 31081 31095 224 29157 31078 31092 256 29158 31079 31093 512 29158 31079 31093 1024 29158 31079 31093 Related links

3.12.3 SDADC electrical specification on page 38

3.12.5 Temperature sensor

The following table describes the temperature sensor electrical characteristics. Table 32. Temperature sensor electrical characteristics DS13808 - Rev 8 page 48/99

3.12.6 Fast-DAC

This block is a 12-bit digital to analog converter (DAC) and is used to drive internal SoC cells. It can drive capacitive load at high speed. The input digital word is latched at the rising edge of the clock signal. Table 33. Fast-DAC electrical specification

1. Difference between two consecutive codes - 1 LSB. These values are related to Fast-DAC with 12-bit resolution (for 11-bit resolutions, a /2

modules, which use the output of Fast-DAC modules.

1. Difference between measured value at code "i" and the value at code "i" on a line drawn between code 0 and last code 4095. Offset error is

included. Parameter specified by design on entire temperature range and measured at cold temperature by design characterization.

1. Difference between expected value and measured value at code "i". Parameter specified by design on entire temperature range and

measured at cold temperature by design characterization.

1. Difference between ideal slope of the transfer function and measured slope computed from code 0 to code 4095.
2. Full scale: 12-bit code transition between the lowest and the highest input codes (from code 0 to code 4095) when DAC output reaches final
3. Time taken for ±0.5 LSB settling (code: 2047 to 2048).
4. Wakeup time from off state (setting the ENx bit in the DAC Control register) until final value ±1 LSB taken on DAC output.
5. Code transition between the lowest input code and the highest input code when DAC output reaches final value ±1 LSB.

DS13808 - Rev 8 page 49/99

3.12.7 Buffered-DAC

This block is a 12-bit resistive ladder based on a digital-to-analog converter (DAC) to drive the resistive load up to 5 kΩ and the capacitive load up to 50 pF. The input digital word is latched at the rising edge of the clock signal. Table 34. Buffered-DAC electrical specification DS13808 - Rev 8 page 50/99

Symbol C Parameter Conditions Value Unit Min Typ Max Tupdate CC D Update rate(7) Capacitance load: CL <50 pF; Twakeup CC D Wake-up time(8) Capacitance load: CL <50 pF; Tsamp — D Sampling time in sample and hold mode(9) DAC_MCR_MODEx=<101> — — 100 μs Ttrim CC D Waiting time between two trimming code changes DAC output buffer ON, with DAC_MCR_MODEx=000, 001, 100, 101 100 — — μs Vdrift_hold CC D Voltage decay rate in sample and hold mode, during hold phase (dV/dt during hold phase) — — — 12 mV/ms PSRR CC D Analog supply rejection ratio @100kHz — 25 — dB SNR CC C Signal to noise ratio(10) — — 69 — dB THD CC C Total harmonic distortion (10) — — -67 — db Ion — T Current consumption In normal operation mode DAC_MCR_MODEx=<011> — — 1200 μA Ioff — D Current consumption In power down mode — — 0.5 μA 1. Difference between two consecutive codes - 1 LSB. 2. Difference between the measured value at code ‘i’ and the value at code ‘i’ on a line drawn between code 0 and last code 4095. Offset error is included. 3. Difference between expected value and measured value at code ‘i’. 4. Difference between ideal slope of the transfer function and measured slope computed from code 0 to code 4095. 5. The calibration must be adjusted in the user application when temperature and supply/reference conditions change. 6. Full scale: 12-bit code transition between the lowest and the highest input codes (from code 0 to code 4095) when DAC output reaches final value. 7. Time taken for ±0.5LSB settling (code: 2047 to 2048). 8. Wake-up time from off state (setting the ENx bit in the DAC control register) until final value ±1 LSB taken on DAC output. 9. Code transition between the lowest input code and the highest input code when DAC output reaches final value ±1LSB. 10. To be measured at 1 kHz. 11. In case of Buffer ON, the parameter specifies the maximum allowable output range of the buffer to maintain the digital-to-analog converter (DAC) linearity. If the output voltage exceeds these limits, the linearity of the converter degrades.

3.12.8 Comparator

This block is a reconfigurable rail-to-rail comparator. This takes input from the DAC. Table 35. Comparator electrical specification DS13808 - Rev 8 page 51/99

Symbol C Parameter Conditions Value Unit Min Typ Max VOFF Comparator offset voltage TRIMOFF<3:0> = 1010; 3 sigma mV CC C Full supply voltage range, full temperature range TRIMOFF<3:0> = 1010; 3 sigma — — ±12 IDDA CC D Static current consumption In power down mode (temperature = 150 °C) — — 1 μA T In functional mode (temperature = 150 °C) — — 920 Vhys CC C Comparator hysteresis(1) HYST[2:0] = 0 –5 0 5 mV C HYST[2:0] = 1 2 10 20 C HYST[2:0] = 2 8 19 40 C HYST[2:0] = 3 12 28 60 C HYST[2:0] = 4 16 38 80 C HYST[2:0] = 5 20 47 100 C HYST[2:0] = 6 25 57 120 C HYST[2:0] = 7 30 67 142 TP CC D Propagation delay(2) Step response, with 200 mV step with 100 mV overdrive, rising time for 1 ns slope — 20 50 ns Tstart CC D Comparator startup time Comparator startup time to reach propagation delay specification — — 5 μs 1. Hysteresis voltage defined when COMPOUT goes from high to low state, threshold voltage at INP = INM-VHYST. 2. With full supply voltage range (VDD_HV_SD_DAC_COMP = 3 to 3.45 V).

3.13 Power management

The power management module monitors the different power supplies and generates the required internal supplies. The regulator is based on an internal switching mode power supply (SMPS) regulator, using external MOSFETs to generate the low voltage supply (VDD_LV for core logic).

3.13.1 Power management integration

Use the integration scheme provided here after to ensure the proper device function. Place capacitances on the board as near as possible to the associated pins and limit the serial inductance of the board to less than 5 nH. SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 52/99

Figure 12. SMPS regulator mode Refer to the device pinout IO definition excel file for the list of available PMU control pins for each device and package. DS13808 - Rev 8 page 53/99

Table 36. External component integration DS13808 - Rev 8 page 54/99

Symbol C Parameter Conditions Value Unit Min Typ Max Rth SR D Thermal resistance (Junction to ambient) In free air — — 80 k/W V(BR)DSS SR D Drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25°C 10 — — V ID SR D Drain current VGS = 4.5 V; Tamb = 100°C — — 2.25 A Schottky diode for SMPS regular mode(10)(11)(12) IF(AV) SR D Average forward current f = 20 kHz; square wave; Tamb ≤ 85°C — — 3 A VF SR D Forward voltage IF = 1 A; Tj = 25°C — — 300 mV Tamb SR D Junction temperature range — -55 — 150 °C Rth(j-a) SR D Thermal resistance (Junction to Ambient) In free air — — 80 k/W 2. For noise filtering, add a high frequency bypass capacitance of 10 nF, as close as possible to the terminal. 3. Recommended X7R capacitors. 4. For optimal EMC performance, consider adding a 10 nF on every supply rail. The intention is to have a decoupling scheme covering the wider possible frequency range. 5. To sustain the high voltage of the SMPS external MOSFET, add a 10 μF on VDD_HV_IO. 6. External capacitance is required both in internal and external (test) regulator modes. 7. For noise filtering, add a high frequency bypass capacitance of 47 nF as close as possible to the terminal. 8. For noise filtering, add a high frequency bypass capacitance of 100 nF as close as possible to the terminal. 9. For noise filtering, add a high frequency bypass capacitance of 1 nF as close as possible to the terminal. 10. The parameters of the selected external components of the SMPS must be equal to or greater than the recommended specifications. The selected components must comply with ESD protection requirements. 11. Based on the device power dissipation, the customer must ensure adequate heat dissipation to prevent overheating. Overheating may lead to performance issues, device failure, and reduced lifespan and reliability. 12. The final selection of components must be reviewed with ST. 13. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging. 14. The value of the capacitance on the high voltage supply reported in this datasheet is a general recommendation. The application can select a different number, based on the external regulator and EMC requirements. 15. Recommended current saturation greater than or equal to 2 A with a resistance DCR less than or equal to 50 mΩ. 16. The device is mounted on an FR4 printed circuit board (PCB) with single-sided copper and tin-plated finish. The mounting pad for the drain measures 6 cm². Related links SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 55/99

3.13.2 Voltage regulators

Table 37. SMPS regulator specifications DS13808 - Rev 8 page 56/99

3.13.3 Voltage monitors

The monitors and their associated levels for the device are given in Table 38. Voltage monitor electrical characteristics. The following figure shows how the voltage monitor threshold works. Figure 13. Voltage monitor threshold definition Table 38. Voltage monitor electrical characteristics DS13808 - Rev 8 page 57/99

Symbol C Parameter Conditions Value (1) Unit Min Typ Max Low voltage detectors (LV supplies) VDD_LV CC P LVD119_C LV supply core low voltage detector VDD_LV — 1.188 1.205 1.222 V CC P LVD119_FL LV supply flash low voltage detector VDD_LV_FLA — 1.188 1.205 1.222 V CC P LVD119_PLL0 LV supply PLL0 low voltage detector VDD_LV_PLL0 — 1.188 1.205 1.222 V CC P LVD119_PLL1 LV supply PLL1 low voltage detector VDD_LV_PLL1 — 1.188 1.205 1.222 V CC P LVD119_DD LV supply DLL & DelayLanes low voltage detector VDD_LV_DD — 1.188 1.205 1.222 V CC P LVD119_RC LV supply RCOSC low voltage detector VDD_LV — 1.188 1.205 1.222 V High and upper voltage detectors (LV supplies) VDD_LV CC P HVD140_C LV supply core high voltage detector VDD_LV — 1.361 1.38 1.399 V CC P UVD145_C LV supply core upper voltage detector VDD_LV — 1.411 1.430 1.449 V CC P UVD145_RC LV supply RCOSC upper voltage detector VDD_LV — 1.411 1.430 1.449 V Minimum and low voltage detectors (HV supplies) VDD_HV_IO CC P POR200_C High voltage supply power-on reset voltage monitor VDD_HV_PMU — 1.760 1.960 2.160 V CC P MVD240T_C HV supply core minimum voltage monitor VDD_HV_PMU — 2.456 2.525 2.594 V CC P MVD240_SMPS HV supply core minimum voltage monitor VDD_HV_SMPS — 2.456 2.525 2.594 V CC P MVD270_C HV supply core minimum voltage monitor VDD_HV_PMU — 2.794 2.850 2.906 V CC P LVD290_C HV supply core low voltage monitor VDD_HV_PMU — 2.898 2.955 3.012 V CC P LVD290_IO1 HV supply I/O low voltage monitor VDD_HV_IO1 segment — 2.898 2.955 3.012 V CC P LVD290_IO0 — 2.898 2.955 3.012 V SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 58/99

Symbol C Parameter Conditions Value (1) Unit Min Typ Max VDD_HV_IO HV supply I/O low voltage monitor VDD_HV_IO0 segment VDD_HV_FLA CC P MVD270_FL HV supply flash minimum voltage monitor VDD_HV_FLA — 2.794 2.850 2.906 V CC P LVD290_FL HV supply flash low voltage monitor VDD_HV_FLA — 2.898 2.955 3.012 V VDD_HV_SD_DAC_COMP CC P LVD290_AD HV supply SD-ADC low voltage monitor VDD_HV_SD — 2.898 2.955 3.012 V CC P LVD290_DACCMP HV supply DAC & COMP low voltage monitor VDD_HV_DAC — 2.898 2.955 3.012 V VDD_HV_SAR CC P LVD290_AS HV supply SAR-ADC low voltage monitor VDD_HV_SAR — 2.898 2.955 3.012 V VDD_HV_OSC CC P LVD290_OSC HV supply OSC low voltage monitor VDD_HV_OSC — 2.898 2.955 3.012 V Upper voltage detectors (HV supplies) VDD_HV_IO CC P UVD380_C HV supply core upper voltage monitor VDD_HV_PMU — 3.651 3.725 3.799 V CC P UVD380_IO0 HV supply I/O upper voltage monitor VDD_HV_IO0 segment — 3.651 3.725 3.799 V VDD_HV_FLA CC P UVD380_FL HV supply flash upper voltage monitor VDD_HV_FLA — 3.651 3.725 3.799 V VDD_HV_SAR CC P UVD380_AS HV supply SAR-ADC upper voltage monitor VDD_HV_SAR — 3.651 3.725 3.799 V VDD_HV_SD_DAC_COMP CC P UVD380_DACCMP HV supply DAC & COMP upper voltage monitor VDD_HV_DAC — 3.651 3.725 3.799 V TVMFILTER CC D Voltage monitor filter(2) — 3 20 µs 1. The values are trimmed during boot process. 2. See Figure 13. Voltage monitor threshold definition. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and are delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to temperature, process and voltage variations. Related links SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 59/99

3.14 Embedded flash memory

The following table shows the wait state configuration. Table 39. Wait state configuration

1. No pipeline with 1 Tclk access delay.

Table 40. Flash memory program and erase specifications DS13808 - Rev 8 page 60/99

Symbol Characteristics(1)(2) Value Unit Typ(3) C Initial max Typical end of life(4) Lifetime max(5) C 25 °C(6) All temp(7) C < 1 K cycles < 250 K cycles t16kpperase0

16 KB block pre-program and erase

time (partition 0) 230 C 495 550 P 300 600 — C ms t32kpperase0

32 KB block pre-program and erase

time (partition 0) 345 C 700 825 P 400 1000 — C ms t64kpperase0

64 KB block pre-program and erase

time (partition 0) 530 C 910 1150 P 600 1600 — C ms t64kpperase 64 KB pre-program and erase time 460 C 700 750 P 420 1200 — C ms t256kpperase

256 KB block pre-program and erase

time 1140 C 2000 2600 P 1300 2800 — C ms t16kprogram0 16 KB block program time (partition 0) 30 C 52 58 P 40 100 — C ms t32kprogram0 32 KB block program time (partition 0) 60 C 105 120 P 75 200 — C ms t64kprogram0 64 KB block program time (partition 0) 120 C 200 250 P 150 400 — C ms t64kprogram 64 KB block program time 102 C 175 200 P 150 400 — C ms t256kprogram 256 KB block program time 410 C 700 800 P 590 1000 — C ms t16kprogrameep Program 16 KB data flash - EEPROM (partition 3) 30 C 52 58 P 64 200 C ms t16keraseeep Erase 16 KB data flash - EEPROM (partition 3) 230 C 495 550 P 400 1000 C ms t16kprogramheep Program 16 KB HSM data flash - EEPROM (partition 3) 30 C 52 58 P 64 200 C ms t16keraseheep Erase 16 KB HSM data flash - EEPROM (partition 3) 230 C 495 550 P 400 1000 C ms ttr Program rate(8) 1.7 C 2.8 3.40 C 2.4 — C s/MB tpr Erase rate(8) 4.8 C 7.2 9.6 C 6.4 — C s/MB ttprfm Program rate factory mode(8) 1.12 C 1.4 1.6 C — — C s/MB terfm Erase rate factory mode(8) 4.0 C 5.2 5.8 C — — C s/MB tffprogram Full flash programming time(9) 3.4 C 5.0 6.0 P 3.8 — — C s tfferase Full flash erasing time(9) 9.9 C 17.0 20.0 P 11.0 — — C s tESRT Erase suspend request rate(10) 200 T — — — — — — µs tPSRT Program suspend request rate(10) 30 T — — — — — — µs tAMRT Array integrity check - margin read suspend request rate 15 T — — — — — — µs tPSUS Program suspend latency(11) — — — — — — 15 T µs tESUS Erase suspend latency(11) — — — — — — 30 T µs tAIC0S Array integrity check (1920 KB, sequential)(12) 11.3 T — — — — — — — ms tAIC256KS Array integrity check (256 KB, sequential)(12) 1.5 T — — — — — — — ms tAIC0P Array integrity check (1920 KB, proprietary)(12) 4.0 T — — — — — — — s tMR0S Margin read (1920 KB, sequential)(12) 30 T — — — — — — — ms tMR256KS Margin read (256 KB, sequential)(12) 4.0 T — — — — — — — ms SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 61/99

Symbol Characteristics(1)(2) Value Unit Typ(3) C Initial max Typical end of life(4) Lifetime max(5) C 25 °C(6) All temp(7) C < 1 K cycles < 250 K cycles tAABT Array integrity check abort latency — — — — — — 10 T µs tMABT Margin read abort latency — — — — — — 10 T µs 1. Actual hardware operation times; this does not include software overhead. 2. Characteristics are valid both for data flash and code flash, unless specified in the characteristics column. 3. Typical program and erase times assume nominal supply values and operation at 25 °C. 4. Typical end of life program and erase times represent the median performance and assume nominal supply values. Typical end of life program and erase values may be used for throughput calculations. These values are characteristic, but not tested. 5. Lifetime maximum program and erase times apply across the voltages and temperatures and occur after the specified number of program/ erase cycles. These maximum values are characterized but not tested or guaranteed. 6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (±5%) supply voltages. 7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (±5%) supply voltages. 8. Rate computed based on 256 KB sectors. 9. Only code sectors, not including EEPROM, neither UTEST and BAF. 10. Time between suspend resume and next suspend. Value stated actually represents min value specification. 11. Timings specified by design. 12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the table is calculated at max frequency. All the flash operations require the presence of the system clock for internal synchronization. About 50 synchronization cycles are needed: this means that the timings of the previous table can be longer if a low frequency system clock is used. Table 41. Flash memory life specification

256 KB code flash endurance 1 — 100 — Kcycles

256 KB code flash endurance(3) 10 — 100 — Kcycles

1. It is recommended that the application enables the core cache memory.
2. Program and erase cycles supported across specified temperature specifications.
3. 10 Kcycles on 4-256 KB blocks are not intended for production. Reduced reliability and degraded erase time are possible.

DS13808 - Rev 8 page 62/99

3.15 AC specifications

All AC timing specifications are valid at up to 150°C.

3.15.1 Debug and calibration interface timing

3.15.1.1 SWD interface timing

Table 42. SWD timings and delay adjustment Figure 14. SWD timings DS13808 - Rev 8 page 63/99

3.15.1.2 JTAG interface timing

Table 43. JTAG pin test and debug timings

1. These specifications apply to JTAG boundary scan only.
2. JTAG timing specified at VDD_HV_IO = 3.15 to 3.45 V and maximum loading per pad type as specified in the I/O section of the datasheet.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

Figure 15. JTAG test clock input timing DS13808 - Rev 8 page 64/99

Figure 18. JTAG boundary scan timing

3.8.2 I/O output DC characteristics on page 20

3.15.2 Extended interrupt and event controller input (EXTI)

Table 44. External interrupt timing

1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

DS13808 - Rev 8 page 66/99

3.15.3 SPI timing

3.15.3.1 SPI — Single ended operation

Table 45. SPI single-ended mode AC specifications — Very Fast IO output characteristics

1. All timing values for output signals in this table are measured to 50% of the output voltage.
2. All output timing is the worst case and includes the mismatching of rise and fall times of the output pads.
3. All timing values are valid for VDD_HV_IO = 3.3 V.
4. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / automotive voltage thresholds.
5. Very Fast IO output characteristics
6. Capacitive Load CL = 25pF
7. Max frequency can be reached under specific device clocks configuration. Refer to the device reference manual, Clocking chapter for

DS13808 - Rev 8 page 67/99

Figure 19. SPI timing diagram — slave mode and CPHA = 1 Figure 20. SPI timing diagram — master mode

3.15.4 I2S timing

The instances SPI2 and SPI3 support the inter-IC sound (I2S) protocol. Table 46. I2S dynamic characteristics DS13808 - Rev 8 page 68/99

Symbol C Parameter Conditions (1)(2)(3)(4)(5)(6) Value Unit Min Typ Max tv(WS) CC D WS valid time Master mode — — 4 ns th(WS) CC D WS hold time Master mode -3 — — ns tsu(WS) CC D WS setup time Slave mode 2 — — ns th(WS) CC D WS hold time Slave mode 3 — — ns tsu(SD_MR) CC D Data input setup time Master receiver 2 — — ns tsu(SD_SR) CC D Slave receiver 3 — — ns th(SD_MR) CC D Data input hold time Master receiver 4 — — ns th(SD_SR) CC D Slave receiver 3 — — ns tv(SD_ST) CC D Data output valid time Slave transmitter (after enable edge) — — 15 ns tv(SD_MT) CC D Master transmitter (after enable edge) — — 4 ns th(SD_ST) CC D Data output hold time Slave transmitter (after enable edge) 4 — — ns th(SD_MT) CC D Master transmitter (after enable edge) -2 — — ns 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. All output timing is the worst case and includes the mismatching of rise and fall times of the output pads. 3. All timing values are valid for VDD_HV_IO = 3.3 V. 4. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / automotive voltage thresholds. 5. Very Fast IO output characteristics. 6. Capacitive Load CL = 25 pF. 7. Fs is the audio sampling frequency. Figure 21. I2S slave timing diagram DS13808 - Rev 8 page 69/99

Figure 22. I2S master timing diagram

3.15.5 CAN timing

The following table describes the CAN timing. Table 47. CAN timing

3.15.6 UART timing

UART channel frequency support is shown in the following table. Table 48. UART frequency support DS13808 - Rev 8 page 70/99

3.15.7 I²C timing

The I2C AC timing specifications are provided in the following tables. Table 49. I²C input timing specifications — SCL and SDA

1. I²C input timing is valid for automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1 ns (10% - 90%).
2. PER_CLK is the SoC peripheral clock, which drives the I²C BIU and module clock inputs. Refer to the device reference manual, Clocking

Table 50. I²C output timing specifications — SCL and SDA

1. Programming the I2C_TIMINGR register (I²C bus frequency divider) with the maximum frequency results in the minimum output timings

affected by the pre-scale and division values programmed in the I2C_TIMINGR register.

1. Timing is specified to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect
2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package capacitance is

accounted for, and does not need to be subtracted from the 25 pF value.

1. All output timing is the worst case and includes the mismatching of rise and fall times of the output pads.
2. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. Refer to the device reference manual, Clocking

DS13808 - Rev 8 page 71/99

Figure 23. I2C input/output timing

3.15.8 DLL block

appropriate code for the required delay from any DELAY block. Table 51. DLL electrical specifications

1. Typical power consumption is at the typical process, typical temperature (25 °C) and typical voltage (1.26 V).
2. Test mode power consumption is based on the testing at the mid-code of the calibration delay line (TEST_CMD_IN<10:0> = 111010 0000;

TEST_MODE_DELAY_0=H and TEST_MODE_DELAY_CMD=H. DS13808 - Rev 8 page 72/99

3.15.9 Delay block

The delay block is used to generate the desired pulse width modulation. When the command which allowed the DLL to be locked is applied, the global duration of this delay block is 1 clock period. The HRTimer calculates from this value the command to be applied to obtain a delay equal to a fraction (1/32 to 31/32) of the clock period. One delay block is used for one PWM output. Table 52. Delay electrical specifications

1. Typical power consumption is at the typical process, typical temperature (25 °C) and typical voltage (1.26 V).
2. Power down mode power consumption mentioned is for DELAY_IN=L, TEST_MODE=L.
3. Test mode power consumption is at the mid-code of the delay line (DLL_CMD<10:0> = 111010 0000; Natural code = 704). DELAY_IN=H

DS13808 - Rev 8 page 73/99

4 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark. SR5E1E3, SR5E1E5, SR5E1E7

Package information

DS13808 - Rev 8 page 74/99

4.1 eTQPF100 package information Figure 24. eTQPF100 package outline 2.The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3.Datums A-B and D to be determined at datum plane H.

1. To be determined at seating datum plane C.
2. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions
3. Details of pin 1 identifier are optional but must be located within the zone indicated.
4. The exact shape of each corner is optional.
5. A1 is defined as the distance from the seating plane to the lowest point on the package body.
6. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from the

dimensions according to the specific device application.

1. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of the exposed pad, which is ensured to be free from resin flashes/bleeds, bordered by an

internal edge of the inner groove.

1. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.
2. “N” is the number of terminal positions for the specified body size.
3. Notch may be present in this area (max 2.0 mm square) if center top gate molding technology is applied. Resin gate residual not protruding out of package top surface.

DS13808 - Rev 8 page 75/99

Table 53. eTQPF100 package mechanical data

1. All Dimensions are in millimeters.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. No intrusion is allowed inwards the leads.
5. Dimension “b” does not include a dambar protrusion. Allowable dambar protrusion does not cause the lead width to exceed

minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

1. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
2. To be determined at seating datum plane C.

DS13808 - Rev 8 page 77/99

1. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 10. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 11. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from the exposed pad itself. The type of exposed pad is variable depending on leadframe pad design (T1, T2, T3), as shown in the figure below. The end user has to verify D2 and E2 dimensions according to the specific device application. 12. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of the exposed pad, which is ensured to be free from resin flashes/bleeds, bordered by an internal edge of the inner groove. 13. “N” is the number of terminal positions for the specified body size. 14. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 15. For Symbols, recommended values and tolerances see "Package symbol definition" table.

Figure 27. eTQPF100 leadframe pad design Table 54. eTQPF100 symbol definitions protrusions, aaa does not apply to those protrusions. “coplanarity” of the package terminals. zones are defined by basic dimension e. tolerance zone defined by “b”. DS13808 - Rev 8 page 78/99

4.2 eTQFP144 package information Figure 28. eTQFP144 package outline 2.The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3.Datums A-B and D to be determined at datum plane H.

1. To be determined at seating datum plane C.
2. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions
3. Details of pin 1 identifier are optional but must be located within the zone indicated.
4. The exact shape of each corner is optional.
5. A1 is defined as the distance from the seating plane to the lowest point on the package body.
6. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from the

dimensions according to the specific device application.

1. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of the exposed pad, which is ensured to be free from resin flashes/bleeds, bordered by an

internal edge of the inner groove.

1. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.
2. “N” is the number of terminal positions for the specified body size.
3. Notch may be present in this area (max 2.0 mm square) if center top gate molding technology is applied. Resin gate residual not protruding out of package top surface.

DS13808 - Rev 8 page 79/99

Table 55. eTQFP144 package mechanical data

1. All Dimensions are in millimeters.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. No intrusion is allowed inwards the leads.
5. Dimension “b” does not include a dambar protrusion. Allowable dambar protrusion does not cause the lead width to exceed the maximum

protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

1. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
2. To be determined at seating datum plane C.

DS13808 - Rev 8 page 81/99

1. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 10. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 11. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from the exposed pad itself. The type of exposed pad is variable depending on leadframe pad design (T1, T2, T3), as shown in the figure below. The end user has to verify D2 and E2 dimensions according to the specific device application. 12. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of the exposed pad, which is ensured to be free from resin flashes/bleeds, bordered by an internal edge of the inner groove. 13. “N” is the number of terminal positions for the specified body size. 14. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 15. For Symbols, recommended values and tolerances see "Package symbol definition" table.

Figure 31. eTQFP144 leadframe pad design Table 56. eTQFP144 symbol definitions protrusions, aaa does not apply to those protrusions. “coplanarity” of the package terminals. zones are defined by basic dimension e. tolerance zone defined by “b”. DS13808 - Rev 8 page 82/99

4.3 eLQFP176 package information Figure 32. eLQFP176 package outline 2.The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3.Datums A-B and D to be determined at datum plane H.

1. To be determined at seating datum plane C.
2. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions
3. Details of pin 1 identifier are optional but must be located within the zone indicated.
4. The exact shape of each corner is optional.
5. A1 is defined as the distance from the seating plane to the lowest point on the package body.
6. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from the

dimensions according to the specific device application.

1. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of the exposed pad, which is ensured to be free from resin flashes/bleeds, bordered by an

internal edge of the inner groove.

1. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.
2. “N” is the number of terminal positions for the specified body size.

DS13808 - Rev 8 page 83/99

Table 57. eLQFP176 package mechanical data

1. All Dimensions are in millimeters.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. No intrusion is allowed inwards the leads.
5. Dimension “b” does not include a dambar protrusion. Allowable dambar protrusion does not cause the lead width to exceed

minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

1. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
2. To be determined at seating datum plane C.

DS13808 - Rev 8 page 85/99

1. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 10. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 11. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from the exposed pad itself. The type of exposed pad is variable depending on leadframe pad design (T1, T2, T3), as shown in the figure below. The end user has to verify D2 and E2 dimensions according to the specific device application. 12. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of the exposed pad, which is ensured to be free from resin flashes/bleeds, bordered by an internal edge of the inner groove. 13. “N” is the number of terminal positions for the specified body size. 14. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 15. For Symbols, recommended values and tolerances see "Package symbol definition" table.

Figure 35. eLQFP176 leadframe pad design Table 58. eLQFP176 symbol definitions protrusions, aaa does not apply to those protrusions. “coplanarity” of the package terminals. zones are defined by basic dimension e. tolerance zone defined by “b”. DS13808 - Rev 8 page 86/99

4.4 Package thermal characteristics

This section describes the thermal characteristics of the device. The parameters in this chapter have been evaluated by considering the device consumption configuration reported in the Section 3.7: Device consumption. 4.4.1 eTQFP100 thermal characteristics Table 59. eTQPF100 thermal characteristics

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,

ambient temperature, power dissipation of other components on the board, and board thermal resistance.

1. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
2. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface

of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
2. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface
3. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC

Table 60. eTQFP144 thermal characteristics

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,

ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

1. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
2. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface

of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
2. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface
3. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC

DS13808 - Rev 8 page 87/99

4.4.3 eLQFP176 thermal characteristics Table 61. eLQFP176 thermal characteristics

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,

ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

1. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
2. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface

of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
2. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface
3. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC

4.4.4 General notes for specifications at maximum junction temperature

• TA = ambient temperature for the package (°C)
• RϴJA = junction-to-ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The differences between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power, and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:
• Construction of the application board (number of planes)
• Effective size of the board, which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leaves the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2 SR5E1E3, SR5E1E5, SR5E1E7

DS13808 - Rev 8 page 88/99

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. Very often, for natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: T J = T B + R θ J B × P D (4) Where:

• TB = board temperature for the package perimeter (°C)
• RϴJB= junction-to-board thermal resistance (°C/W) per JESD51-8
• PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition: with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of the junction-to-case thermal resistance plus the case-to- ambient thermal resistance: R θ J A = R θ JC + R θC A (5) Where:
• RϴJA= junction-to-ambient thermal resistance (°C/W)
• RϴJC= junction-to-case thermal resistance (°C/W)
• RϴCA= case-to-ambient thermal resistance (°C/W) RϴJC is device-related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RϴCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to the heat sink to the ambient environment. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be generated upon request. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (ΨJT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: T J = T T + ψ J T × P D (6) Where:
• TT = thermocouple temperature on the top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40- gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and on approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. SR5E1E3, SR5E1E5, SR5E1E7

DS13808 - Rev 8 page 89/99

When the board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter (ΨJPB) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed pad) using the following equation: T J = T B + ψ J PB × P D (7) Where:

• TB = board temperature for the package perimeter (°C)
• ΨJPB = junction temperature parameter (°C/W)
• PD = power dissipation in the package (W) SR5E1E3, SR5E1E5, SR5E1E7

DS13808 - Rev 8 page 90/99

5 Ordering information

Figure 36. Ordering information scheme Default: C30F0Other: Reserved for future use.

Ordering information

DS13808 - Rev 8 page 91/99

Revision history

Table 62. Document revision history 07-Apr-2022 1 Initial internal release. 02-Jan-2023 2 Second internal release. 02-Feb-2023 3 Third internal release. 24-Oct-2023 4 Fourth internal release.

• Changed the confidentiality level of the document
• In the whole document: – replaced SR5E1x with part numbers – minor editorial changes
• Table 5. Operating conditions: IINJ2, updated Min, Typ, and Max values
• Table 12. I/O input electrical characteristics: – ILKG, updated the Max value of "INPUT-ONLY pads" – CP1, updated the Max value
• Table 14. Slow I/O output characteristics: IDCMAX_S, updated Max value
• Table 15. Medium I/O output characteristics: IDCMAX_M, updated Max value
• Table 16. Fast I/O output characteristics: IDCMAX_F, updated Max value
• Table 17. Very fast I/O output characteristics: IDCMAX_V, updated Max value
• Table 27. ADC pin specification: CP2, updated Max value
• Table 32. Temperature sensor electrical characteristics: – Temperature monitoring range, updated "C" column – Tflagm40, updated "C" column – Tflagm150, updated "C" column
• Table 34. Buffered-DAC electrical specification: – DNL, updated Max value – TUE, updated Min and Max values. Removed the note – GAIN_err, updated Max value
• Table 38. Voltage monitor electrical characteristics: VDD_LV, updated Max value of parameter "POR031_C" 19-Dec-2023 6 • Section 5: Ordering information: pin specifier, added the option “5: 144 pins” 02-Oct-2024 7 In the whole document:
• minor editorial changes
• replaced master/slave by inclusive terms
• Cover page:
• – added package TQFP144 – added a title to the table – added product SR5E1E5
• Section Features: AEC-Q100 automotive indicated as qualified
• Security: hardware security module (HSM): added "Cybersecurity ISO/SAE 21434..." bullet
• Section 1.1: Document overview: removed "This device is a preliminary..."
• Section 3.1: Introduction: removed note
• Table 4. Absolute maximum ratings: – in VDD_HV_OSC, VDD_HV_FLA, VDD_HV_SAR and VDD_HV_SD_DAC_COMP, – in TTRIN, updated max value and unit columns – footnote 1, 2 and 3 reformulated – in footnote 2, added content between parenthesis and replaced VDD_HV_IO with VDD_HV_* – in footnote 6, added content "It is important to ensure that..." SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 92/99

• Table 5. Operating conditions: – in note 4, 5, 6 and 7, updated range values and removed "to reduce the false LVD triggers recurrence" – added range [1.225-1.222] in note 4 and [1.345-1.361] in note 5 – updated note 11
• Table 10. Device consumption: – in IDD_HV_SMPS, updated max value column – added a note to IDD_HV_SMPS_LKG and IDD_HV_SMPS – in ISR, updated max value and unit columns – added note to ISPIKE – added I/O pins element in notes 3 and 4
• Table 13. I/O pull-up/pull-down electrical characteristics: in IWPU and IWPD, updated C column
• Table 28. SARn ADC electrical specification: removed ΔVPRECH
• Table 29. SDn ADC electrical specification: – in VIN_PK2PK, updated Value column – in each δGROUP, added condition OSR = 75 – in Vcmrr, updated Min value – in VOFFSET, updated C and Max values – removed ΔSNRINJ2 – in IADR_SD and IADR_BIAS, updated C column – updated VOFFSET row
• Table 33. Fast-DAC electrical specification and Table 34. Buffered-DAC electrical specification: replaced DACMOD_v12 occurrences by DAC_MCR_MODEx
• Table 33. Fast-DAC electrical specification: in DNL, updated Max value
• Table 34. Buffered-DAC electrical specification: – added Ttrim parameter – added RBON and RBOFF – split CL row with CSH – in DNL, updated Min value – in Offset_err_cal, updated C column and added a note in Parameter column – updated Tsettling_buff and Tsettling_unbuff values
• Table 36. External components integration: removed note 12 from PMPB100XPEAX and instead added it for PMPB55XNEAX
• Table 37. SMPS regulator specifications: – removed note 1 – updated min value and max value in VDD_HV_IO and VSMPS – updated max value in IDDCLAMP
• Table 43. JTAG pin test and debug timings: updated tJDC row
• Section 4: Package information: removed "Package case numbers" table. JEDEC specification reference specified in the respective package subsection. 07-Nov-2025 8 Following are the changes in this version of the datasheet:
• Table 5. Operating conditions: updated note 4
• Table 28. SARn ADC electrical specification: updated the min, typ, and max values of VIN_COM
• Table 34. Buffered-DAC electrical specification: added notes to min value of DACoutput_min and max value of DACoutput_max
• Table 36. External component integration: – added note to Ls – updated and added parameters for SMPS regulator mode
• Section 4.2: eTQFP144 package information: updated eLQFP144 to eTQFP144, throughout the section
• Figure 25. eTQPF100 section A-A: updated the figure
• Figure 33. eLQFP176 section A-A: updated the figure
• Section 5: Ordering information: updated package type, packing and replaced reserved with Silicon revision. SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 93/99

SR5E1E3, SR5E1E5, SR5E1E7

Contents

DS13808 - Rev 8 page 95/99

ADC Analog-to-digital converter AEC Automotive Electronics Council. Also known as CDF-AEC for Chrysler-Delco-Ford Automotive Electronics Council. Shortened to AEC. AHB Advanced high-performance bus ALC Automatic level control ANSI American National Standards Institute APB Advanced peripheral bus ASIL Automotive safety integrity level - a risk classification system defined by the ISO 26262 standard for the functional safety of road vehicles; there are four ASILs identified by ISO 26262 ― A, B, C, and D, from the lowest to the highest degree of automotive hazard AXI Advanced extensible interface CAN Controller area network CAN FD® Controller area network flexible data rate CBC Cipher block chaining CDM Charged device model CITO Controller input target output CMAC Cipher-based message authentication code CMOS Complementary metal-oxide-semiconductor COTI Controller output target input CPHA Clock phase bit. Selects the clock phase. CPOL Clock polarity bit. Selects the clock polarity. CPU Central processing unit CTI Arm® CoreSight™ cross-trigger interface CTM Cross-trigger matrix DAC Digital-to-analog converter DC Direct current DCF Device configuration format DMA Direct memory access DNL Differential nonlinearity ECB Electronic code book ECC Error correction code ECU Engine control unit eDMA Enhanced direct memory access EEPROM Electrically erasable programmable read- only memory EMC Electromagnetic compatibility ESD Electrostatic discharge ESR Equivalent series resistance EVITA e-safety vehicle intrusion protected applications EXTAL External oscillator input FCCU Fault collection and control unit FIFO First in, first out FIR Finite-impulse response FPU Floating-point unit GCM Galois/counter mode GNSS Global navigation satellite system GPIO General-purpose input/output HBM Human body model HRTIM High-resolution and complex waveform builder SR5E1E3, SR5E1E5, SR5E1E7 Glossary DS13808 - Rev 8 page 96/99

HSM Hardware security module I/O Input/output IEC International Electrotechnical Commission IEEE Institute of Electrical and Electronics Engineers IP Intellectual property IPC Institute of Printed Circuits IRCOSC Internal RC oscillator IRQ Interrupt request ISO International Organization for Standardization I²C Inter-integrated circuit I²S Integrated interchip sound JCOMP JTAG compliance (pin) JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group KB Kilobyte LIN Local interconnect network LSB Least significant byte LV Low voltage LVD Low-voltage detector MB Megabyte MCR Module configuration register MCU Microcontroller unit MD Modulation depth MEMU Memory error management unit MOSFET Metal-oxide-semiconductor field-effect transistor NMOS N-type metal–oxide–semiconductor NVM Nonvolatile memory - a memory that retains its contents even when powered down, such as flash memory or EEPROM OSR Oversampling ratio OTA Over the air PC Printed circuit PCB Printed-circuit board PHI PLL output clock PLL Phase-locked loop PWM Pulse-width modulation RAM Random access memory RC Resistor-capacitor SAR Successive approximation register SARADC Successive-approximation register analog- to-digital converter SAR SV SAR supervisor SCK SPI clock (SPI and other SPI-related specifications such as queued SPI) SCL Serial clock line (I²C signal) SD Secure digital SDADC Sigma-delta analog-to-digital converter SDIO Secure digital input/output SoC System on chip SPI Serial peripheral interface SRAM Static random-access memory SSCG Spread-spectrum clock generation SWD Serial wire debug SR5E1E3, SR5E1E5, SR5E1E7 Glossary DS13808 - Rev 8 page 97/99

TCK Test clock (JTAG standard) TCM Tightly coupled memory TMS Test mode select TRNG True random number generator TTL Transistor-to-transistor logic TUE Total unadjusted error UART Universal asynchronous receiver/transmitter UTEST User-programmed DCF records. Some UTEST DCF records are written at the factory during production testing. Others are written by the end user and programmed at the same time as the application code. UVD Maximum-voltage detector VCO Voltage-controlled oscillator WS Wait state XOSC Crystal oscillator XTAL External oscillator output SR5E1E3, SR5E1E5, SR5E1E7 Glossary DS13808 - Rev 8 page 98/99

IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. In the event of any conflict between the provisions of this document and the provisions of any contractual arrangement in force between the purchasers and ST, the provisions of such contractual arrangement shall prevail. The purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. The purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of the purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. If the purchasers identify an ST product that meets their functional and performance requirements but that is not designated for the purchasers' market segment, the purchasers shall contact ST for more information. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2025 STMicroelectronics – All rights reserved SR5E1E3, SR5E1E5, SR5E1E7 DS13808 - Rev 8 page 99/99