SR2 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 22
Technical content
Datasheet sections
- 1 Description
- 1.1 Test mode
- 2 Pin descriptions
- 2.1 Power supply (V CC)
- 2.2 Ground (V SS)
- 2.3 Smart Reset™ input (SR0 )
- 2.4 Smart Reset™ input (SR1 )
- 2.5 Reset output (RST )
- 3 Typical application diagram
- 4 Timing waveforms
- 5 Typical operating characteristics
- 6 Maximum ratings
- 7 DC and AC parameters
- 8 Package information
- 9 Part numbering
- 10 Package marking information
- 11 Revision history
Features
Operating voltage 1.65 V to 5.5 V Low supply current 1.5 µA Integrated test mode Dual Smart Reset™ push- button inputs with fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal pull-up resistor Push-button controlled reset pulse duration – Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed – Option 2: defined output reset pulse duration (t REC), factory-programmed No power-on reset Single reset output – Active low or active high – Push-pull or open drain with optional pull- up resistor Fixed Smart Reset™ inpu t logic voltage levels Operating temperature: - 40 °C to +85 °C UDFN6 package: 1.6 mm x 1.3 mm ECOPACK ®2 (RoHS compliant, Halogen- Free)
Applications
Wearable Activity tracker Smartwatch Smartglasses UDFN6 (1.6 x 1.3 mm)
1 Description
The Smart Reset™ devices provide a useful fe ature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset™ input delay time (t SRC) and combined push-button inputs, which together ensures a safe reset and eliminates the need for a specific dedicated reset button. This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input push- button are connected to microcontroller interrupt inputs, and are closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-button closed for the extended setup time t SRC causes a hard reset of the processor through the reset output. The SR2 has two combined delayed Smart Reset™ inputs (SR0 , SR1) with preset delayed Smart Reset™ setup time (t SRC). The reset output is asserted after both of the Smart Reset™ inputs were held ac tive for the selected tSRC delay time. Depending on selected option the RST output remains asserted either until at least one SR input goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for tREC (i.e. factory-programmed). The reset output, RST, is active low or active high, push-pull or open drain with optional pull-up resistor. The device fully operates outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 V.
1.1 Test mode
After pull of SR0 up to VTEST or more (VCC + 1.4 V, max.) we start counting initial shorten tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for tREC (if tREC option is used) or stays low as long as overvoltage on SR0 in detected (if tREC option is not used). This is a feedback and a user knows that the device is locked in the test mode. Each time both SR inputs are connected to ground in test mode a shorten tSRC-SHORT (21 ms, typ.) is used instead of long tSRC (0.5 s -10 s). Return from to normal mode is possible by a new startup of the device (i.e. VCC goes to 0 V and back to its original state). In this way the device can be quickly tested without repeating test mode triggering. Advantage of this solution is pretty high glitch immunity, feedback to user about entry to the test mode and testability within full V CC range.
Figure 3. Block diagram Table 1. Signal names
1 V SS Supply ground Ground
3 RST Output
4 NC - Not connected (not bon ded; should be connected to V
6 V CC Supply voltage
2 Pin descriptions
2.1 Power supply (V CC)
This pin is used to provide power to the Smart Reset™ device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the SR2 device as possible.
2.2 Ground (V SS)
Ground pin for the device.
2.3 Smart Reset™ input (SR0 )
Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR inputs need to be asserted simultaneously for at least tSRC to assert the reset output (RST). By connecting a voltage higher than VCC to the SR0 the device enters a test mode (see Section 1: Description on page 3 for more information).
2.4 Smart Reset™ input (SR1 )
Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR inputs need to be asserted simultaneously for at least tSRC to assert the reset output (RST).
2.5 Reset output (RST )
RST is active low or active high, push-pull or open drain reset output with optional internal pull-up resistor. Output reset pulse width is optional as follows: Neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to deassert); Fixed, factory-programmed output reset pulse duration for tREC independent on Smart Reset™ input state. If VCC drops below 1.575 V, the RST output is deasserted and its state is guaranteed down to 1 V (see Figure 8).
3 Typical application diagram
Figure 4. Single-button Smart Reset™ typical hookup
- External pull-up resistor requested if the reset output (RST ) is open drain type without internal pull-up.
- External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up.
- When only one Smart Reset™ input push-button is used, tie both the SR inputs together.
Figure 5. Dual-button Smart Reset™ typical hookup
- External pull-up resistor requested if the reset output (RST ) is open drain type without internal pull-up.
- External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up.
4 Timing waveforms
Figure 6. Option without tREC Figure 7. Option with tREC
Figure 8. Undervoltage condition
- If undervoltage occurs (V CC drops below 1.575 V typ.) while reset output is active, the reset output is
5 Typical operating characteristics
Figure 9. Supply current (ICC) vs. temperature (TA) Figure 10. Smart Reset™ delay (t SRC) vs. temperature (TA), tSRC = 7.5 s (typ.)
6 Maximum ratings
STMicroelectronics™ SURE program and other relevant quality documents. Table 2. Absolute maximum ratings
- Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
- For push-pull RST output type only from -0.3 V to VCC +0.3 V.
7 DC and AC parameters
Table 3. Operating and measurement conditions
Table 4. DC and AC characteristic
- Valid for ambient operating temperature T A = -40 to +85 °C, VCC = 1.65 to 5.5 V.
- Typical values are at 25 °C and V CC = 3.3 V unless otherwise noted.
- Reset outputs are deasserted below 1.575 V typ. and remain deasserted down to V CC = 1 V.
- Input glitch immunity is equal to t SRC, when both inputs (SR0 and SR1) are low. Otherwise infinite.
8 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
9 Part numbering
Table 6. Ordering information scheme may apply. Contact local sales office for availability.
Figure 17. Package marking (top view) Table 7. Package marking
- OD = open drain, AL = active low.
- No t REC = push-button controlled reset pulse width.
Table 8. Document revision history