SR2.8 SEMTECH | Alldatasheet
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1 www.semtech.com PROTECTION PRODUCTS SR2.8 Low Capacitance TVS Diode Array Description Features Circuit Diagram Schematic & PIN Configuration Revision 01/17/08 RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The SR series has been specifically designed to protect sensitive compo- nents which are connected to data and transmission lines from overvoltage caused by electrostatic dis- charge (ESD), electrical fast transients (EFT), and tertiary lightning. The unique design of the SR series devices incorpo- rates four surge rated, low capacitance steering diodes, and a TVS diode in a single package. The TVS diode is constructed using Semtech’s proprietary low voltage EPD technology for superior electrical charac- teristics at 2.8 volts. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The internal TVS diode pre- vents over-voltage on the power line, protecting any downstream components. The low capacitance array configuration allows the user to protect two high-speed data or transmission lines. The low inductance construction minimizes voltage overshoot during high current surges.
Applications
Mechanical Characteristics Firewire Sensitive Analog Inputs Video Line Protection Portable Electronics Microcontroller Input Protection WAN/LAN Equipment ESD protection to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20µs) Array of surge rated diodes with internal EPD TVS diode Protects two I/O lines Low capacitance (<10pF) for high-speed interfaces Low leakage current (< 1µA) Low operating voltage: 2.8V Solid-state technology JEDEC SOT-143 package Molding compound flammability rating: UL 94V-0 Marking : R2.8 Packaging : Tape and Reel Pin 4 Pin 2 Pin 3 Pin 1 2 3 SOT-143 (Top View)
2 2008 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SR2.8 Absolute Maximum Rating
Electrical Characteristics
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3 2008 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SR2.8 Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 0.01 0.1 0.1 1 10 100 1000 Pulse Duration - tp (µs) Peak Pulse Power - Ppk (kW) 100 110 0 25 50 75 100 125 150 Ambient Temperature - T A (oC) % of Rated Power or IPP Clamping Voltage vs. Peak Pulse Current 100 110 0 5 10 15 20 25 30 Time (µs) Percent of IPP e-t td = I PP /2 Wa v e f o r m Parameters: tr = 8µs td = 20µs Pulse Waveform Forward Voltage vs. Forward Current 0 5 10 15 20 Peak Pulse Current - IPP (A) Clamping Voltage - VC (V) Waveform Parameters: tr = 8µs td = 20µs 0 5 10 15 20 25 30 35 40 45 50 Forward Current - I F (A) Forward Voltage - VF (V) Waveform Parameters: tr = 8µs td = 20µs
4 2008 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SR2.8 Applications Information Data Line PrData Line PrData Line PrData Line PrData Line Pr oooootttttection Using Intection Using Intection Using Intection Using Intection Using Int ernal Ternal Ternal Ternal Ternal T VVVVVS DiodeS DiodeS DiodeS DiodeS Diode as Referenceas Referenceas Referenceas Referenceas Reference IPP ISB IPT IR VRWM VV PT VC VBRR IBRR SB Figure 1 - EPD TVS IV Characteristic Curve Device Connection Options for Protection ofDevice Connection Options for Protection ofDevice Connection Options for Protection ofDevice Connection Options for Protection ofDevice Connection Options for Protection of TTTTTwwwwwo High-Speed Data Lineso High-Speed Data Lineso High-Speed Data Lineso High-Speed Data Lineso High-Speed Data Lines The SR2.8 TVS is designed to protect two data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode V F) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 2 and 3. The nega- tive reference (REF1) is connected at pin 1. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (REF2) is connected at pin 4. The options for connecting the positive reference are as follows: Note that pins 4 is connected internally to the cathode of the low voltage TVS. It is not recommended that this pin be directly connected to a DC source greater than the snap-back votlage (V SB) as the device can latch on as described below. EPD TVS Characteristics These devices are constructed using Semtech’s proprietary EPD technology. By utilizing the EPD tech- nology, the SR2.8 can effectively operate at 2.8V while maintaining excellent electrical characteristics. The EPD TVS employs a complex nppn structure in contrast to the pn structure normally found in tradi- tional silicon-avalanche TVS diodes. Since the EPD TVS devices use a 4-layer structure, they exhibit a slightly different IV characteristic curve when compared to conventional devices. During normal operation, the device represents a high-impedance to the circuit up to the device working voltage (V RWM). During an ESD event, the device will begin to conduct and will enter a low impedance state when the punch through voltage PT) is exceeded. Unlike a conventional device, the low voltage TVS will exhibit a slight negative resistance characteristic as it conducts current. This characteris- tic aids in lowering the clamping voltage of the device, but must be considered in applications where DC voltages are present. When the TVS is conducting current, it will exhibit a slight “snap-back” or negative resistance characteristics due to its structure. This point is defined on the curve by the snap-back voltage (V SB) and snap-back current (I SB). To return to a non- conducting state, the current through the device must fall below the I SB (approximately <50mA) and the voltage must fall below the V SB (normally 2.8 volts for a 3.3V device). If a 3.3V TVS is connected to 3.3V DC source, it will never fall below the snap-back voltage of 2.8V and will therefore stay in a conducting state.
5 2008 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SR2.8 PIN Descriptions Applications Information (continued) Board Layout Considerations for ESD ProtectionBoard Layout Considerations for ESD ProtectionBoard Layout Considerations for ESD ProtectionBoard Layout Considerations for ESD ProtectionBoard Layout Considerations for ESD Protection Board layout plays an important role in the suppression of extremely fast rise-time ESD transients. Recall that the voltage developed across an inductive load is proportional to the time rate of change of current through the load (V = L di/dt). The total clamping voltage seen by the protected load will be the sum of the TVS clamping voltage and the voltage due to the parasitic inductance (V C(TOT) = V C + L di/dt) . Parasitic inductance in the protection path can result in signifi- cant voltage overshoot, reducing the effectiveness of the suppression circuit. An ESD induced transient for example reaches a peak in approximately 1ns. For a 30A pulse (per IEC 61000-4-2 Level 4), 1nH of series inductance will increase the effective clamping voltage by 30V (V = 1x10 -9 (30/1x10-9)). For maximum effectiveness, the following board layout guidelines are recom- mended: z Minimize the path length between the SR3.3 and the protected line. z Place the SR2.8 near the connector to restrict transient coupling in nearby traces. z Minimize the path length (inductance) between the RJ45 connector and the SR2.8. Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small com- pared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint.
6 2008 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SR2.8 Outline Drawing - SOT-143 Land Pattern - SOT-143 A e e/2 e1 bxN bbb C A B B aaa C A B CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). NOTES: OR GATE BURRS. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS3. DATUMS AND TO BE DETERMINED AT DATUM PLANE REFERENCE JEDEC STD TO-253, VARIATION D.4. -A- -B-2. -H- SIDE VIEW SEE DETAIL A H 0.25C SEATING PLANE GAUGE PLANE 0 c L DETAIL A D E A C SEATING PLANE ccc C4X INCHES .114 E D b e c .011 .003 .082 DIM A MIN .000 .031 0.51 0.20 2.64 0.30 0.08 2.10 (.021) .075 .093 .020 .008 .104 (0.54)
1.92 BSC
2.37 2.90 MILLIMETERS MAX 0.15 1.22 MIN DIMENSIONS 0.013 MAXNOM - .006 .048 NOM 0.80 3.042.80.110 .120 e1 .008 0.20 BSC E1 .051 1.30 0.940.76.037.029 1.401.20 N4 4 0 - 8°0°8°0° - .055.047 aaa .006 0.15 bbb .008 0.20 ccc .004 0.10 C Y Y REFERENCE IPC-SM-782A.2. GZ NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. DIM Y Z G C MILLIMETERSINCHES (2.20) .055 .141 .076 .039 .031 .068 (.087) 1.40 3.60 1.72 1.00 0.80 1.92 DIMENSIONS X2 .047 1.20 X1 X1
7 2008 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SR2.8 Contact Information Semtech Corporation Protection Products Division
200 Flynn Road, Camarillo, CA 93012
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