SR1 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
Datasheet sections
- 1 Description
- 1.1 Test mode
- 1.2 Logic diagram
- 1.3 Pin connections
- 2 Device overview
- 3 Pin descriptions
- 3.1 Power supply (V CC)
- 3.2 Power-up sequence
- 3.3 Ground (V SS)
- 3.4 Smart Reset input (SR )
- 3.5 Reset output (RST )
- 3.6 RST output undervoltage behavior (for open-drain option)
- 4 Typical application diagrams
- 5 Timing diagrams
- 6 Typical operating characteristics
- 7 Maximum ratings
- 8 DC and AC parameters
- 9 Package information
- 10 Tape and reel information
- 11 Part numbering
- 12 Package marking information
- 13 Revision history
Features
Operating voltage range 2 V to 5.5 V Low supply current 1 µA Integrated test mode Single Smart Reset™ push-button input with fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal input pull-up resistor Push-button controlled reset pulse duration – Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed – Option 2: defined output reset pulse duration (t REC), factory-programmed Single reset output – Active low or active high – Push-pull or open drain with optional pull- up resistor Fixed Smart Reset input logic voltage levels Operating temperature: -40 °C to +85 °C UDFN6 package 1.00 mm x 1.45 mm ECOPACK ®2 (RoHS compliant, Halogen- Free)
Applications
Wearable Activity tracker Smartwatch Smartglasses UDFN6 (1.00 x 1.45 mm)
1 Description
The Smart ResetTM devices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset input delay time (tSRC), which ensures a safe reset and eliminates the need for a specific dedicated reset button. This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input push- button is connected to the microcontroller interrupt input, and is closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-button closed for the extended setup time t SRC causes a hard reset of the processor through the reset output. The SR1 has one Smart Reset input (SR) with preset delayed Smart Reset setup time (tSRC). The reset output (RST) is asserted after the Smart Reset input is held active for the selected tSRC delay time. The RST output remains asserted either until the SR input goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for tREC (i.e. factory-programmed). The device fully operates over a broad VCC range from 2.0 V to 5.5 V.
1.1 Test mode
After pulling SR up to VTEST (VCC + 1.4 V) or above, the counter starts to count the initial shortened tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for tREC (if tREC option is used) or stays low as long as overvoltage on SR is detected (if tREC option is not used). This is feedback, and the user only knows that the device is locked in test mode. Each time the SR input is connected to ground in test mode, a shortened tSRC-SHORT (tSRC/128) is used instead of regular tSRC (0.5 s - 10 s). In this way the device can be quickly tested without repeating test mode triggering. Return to normal mode is possible by performing a new startup of the device (i.e. VCC goes to 0 V and back to its original state). The advantages of this solution are its high glitch immunity, user feedback regarding entry into test mode, and testability within the full VCC range.
1.2 Logic diagram
Figure 1. SR1 logic diagram
1.3 Pin connections
Figure 2. UDFN6 pin connections (top view)
- Not connected (not bonded); should be connected to V SS.
2 Device overview
Figure 3. SR1 block diagram Table 1. Signal names 1R S T Output Reset output, active low, open drain. 3S R Input Smart Reset input, active low. 5 NC - Not connected (not bonded); should be connected to V SS. 6 NC - Not connected (not bonded); should be connected to V SS.
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3 Pin descriptions
3.1 Power supply (V CC)
This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the SR1 device as possible.
3.2 Power-up sequence
In normal mode, if different input side (SR) and VCC voltage domains are used, power-on sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode entry: there should not be logic high present on the SR input before the VCC power-up. However VCC and V(SR) rising at the same time is OK (e.g. if both are in the same voltage domain), the device will then safely start into normal operating mode, with RST output inactive (in High-Z mode for open-drain option).
3.3 Ground (V SS)
This is the ground pin for the device.
3.4 Smart Reset input (SR )
Push-button Smart Reset input, active low with optional pull-up resistor. SR input needs to be asserted for at least tSRC to assert the reset output (RST). By connecting a voltage higher than VCC + 1.4 V to the SR input the device enters test mode (see Section 1: Description on page 3 for more information).
3.5 Reset output (RST )
RST is active low or active high, open drain or push-pull reset output with optional internal pull-up resistor. Output reset pulse width is optional as follows: Neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to de-assert) Fixed, factory-programmed output reset pulse duration for tREC independent on Smart Reset input state.
3.6 RST output undervoltage behavior (for open-drain option)
High-Z on RST output below the specified operating voltage range is guaranteed at VCC power-on or in case that valid VCC dropped while the device was idle, i.e. while both output and input were inactive.
4 Typical application diagrams
Figure 4. Typical application diagram - input, output and SR1 device in one voltage Figure 5. Typical application diagram - SR1 device in a different voltage domain than
- Open-drain RST output type and fixed SR input logic threshold allows to use the device in different voltage
powered up before or together with voltage on the SR input.
Figure 6. Typical application diagram in different voltage domains - SR input in VBAT
5 Timing diagrams
Figure 7. RST output without tREC option
- V CC should be powered up before or together with voltage on the SR input to prevent entering test mode
Figure 8. RST output with tREC option
- V CC should be powered up before or together with voltage on the SR input to prevent entering test mode
a condition V(SR) > VCC +1.1 V typ.
6 Typical operating characteristics
Figure 9. Supply current (ICC) vs. temperature (TA) Figure 10. Smart Reset delay (tSRC) vs. temperature (TA), tSRC = 4.0 s (typ.)
7 Maximum ratings
STMicroelectronics™ SURE program and other relevant quality documents. Table 2. Absolute maximum ratings
- Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
8 DC and AC parameters
Table 3. Operating and measurement conditions
Table 4. DC and AC characteristics
- Valid for ambient operating temperature T A = -40 to +85 °C, VCC = 2.0 to 5.5 V.
- Typical values are at 25 °C and V CC = 3.3 V unless otherwise noted.
9 Package information
specifications, grade definitions and product status are available at: www.st.com.
- Package outline exclusive of any mold flashes dimensions and metal burrs.
10 Tape and reel information
Figure 15. Carrier tape
- 10-sprocket hole pitch cu mulative tolerance ±0.20.
Figure 16. Pin 1 orientation
11 Part numbering
Table 6. Ordering information scheme apply. Contact local sales office for availability.
- Push-pull reset output type also avail able (active low or active high). SR input and open drain reset output
Figure 17. Package marking (top view) Table 7. Package marking
- OD = open drain, AL = active low.
- No t REC = push-button controlled reset pulse width, any other value represents typical value of tREC.
Table 8. Document revision history