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Data Sheet: Technical Data Document Number: PXR40 Rev. 1, 09/2011 © Freescale Semiconductor, Inc., 2011. All rights reserved. PXR40 TEPBGA–416 27mm x 27mm
- Dual issue, 32-bit CPU core complex (e200z7) – Compliant with the Powe r Architecture embedded category – 16 KB I-Cache and 16 KB D-Cache – Includes an instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction – Includes signal processing extension (SPE2) instruction support for digital signal processing (DSP) and single-precision floating point operations
- 4 MB on-chip flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
- 256 KB on-chip general-purpose SRAM including 32 KB of standby RAM
- Two direct memory access controller (eDMA2) blocks – One supporting 64 channels – One supporting 32 channels
- Interrupt controller (INTC)
- Frequency modulated phase-locked loop (FMPLL)
- Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters
- External bus interface (EBI) fo r calibration and application development (not available on all packages)
- System integration unit (SIU)
- Error correction status module (ECSM)
- Boot assist module (BAM) supports serial bootload via CAN or SCI
- Two second-generation enha nced time processor units (eTPU2) that share code and data RAM. – 32 standard channels per eTPU2 – 24 KB code RAM – 6 KB parameter (data) RAM
- Enhanced modular input output system supporting 32 unified channels (eMIOS) with each channel capable of single action, double action, pulse width modulation (PWM) and modulus counter operation
- Four enhanced queued anal og-to-digital converters (eQADC) – Support for 64 analog channels – Includes one absolute reference ADC channel – Includes eight decimation filters
- Four deserial serial peri pheral interface (SPI) modules
- Three enhanced serial communication interface (UART) modules
- Four controller area network (CAN) modules
- Dual-channel FlexRay controller
- Nexus development inte rface (NDI) per IEEE-ISTO 5001-2003/5001-2008 standard
- Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
- On-chip voltage regulator controller regulates supply voltage down to 1.2 V for core logic PXR40 Microcontroller Data Sheet
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor2 Table of Contents
5.2.1 General notes for specifications at maximum junction
5.3 EMI (Electromagnetic Interfer ence) characteristics . . .55
5.6.3 Power sequencing and POR dependent on V DDA60
1 PXR40 features
Table 1 displays the PXR40 feature set. Table 1. PXR40 feature set
4 SWT
1 Watchdog
Table 1. PXR40 feature set (continued)
2 PXR40 block diagram
Figure 1 shows a top-level block diagram of the PXR40 microcontrollers. Figure 1. Block diagram
3 Pin assignments
The figures in this section show the primary pin function. For the full signal properties and muxing table, see Table 4. Figure 2. PXR40 416-ball TEPBGA (full diagram)
Figure 3. PXR40 416-ball TEPBGA (1 of 4)
Figure 4. PXR40 416-ball TEPBGA (2 of 4)
Figure 5. PXR40 416-ball TEPBGA (3 of 4)
Figure 6. PXR40 416-ball TEPBGA (4 of 4)
4 Signal properties and muxing
SIU_PCRn[PA] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 7. Figure 7. Supported functions example
113 TCRCLKA_IRQ7_GPIO113 P TCRCLKA eTPU A TCR clock I 5V M
Table 2. Signal Properties Summary
12 Freescale Semiconductor
Table 2. Signal Properties and Muxing Summary
113 TCRCLKA_IRQ7_
114 ETPUA0_ETPUA12_
115 ETPUA1_ETPUA13_
116 ETPUA2_ETPUA14_
117 ETPUA3_ETPUA15_
118 ETPUA4_ETPUA16_
119 ETPUA5_ETPUA17_
120 ETPUA6_ETPUA18_
121 ETPUA7_ETPUA19_
122 ETPUA8_ETPUA20_
123 ETPUA9_ETPUA21_
124 ETPUA10_ETPUA22_
Table 2. Signal Properties and Muxing Summary (continued)
14 Freescale Semiconductor
125 ETPUA11_ETPUA23_
126 ETPUA12_PCSB1_
127 ETPUA13_PCSB3_
128 ETPUA14_PCSB4_
129 ETPUA15_PCSB5_
130 ETPUA16_PCSD1_
131 ETPUA17_PCSD2_
132 ETPUA18_PCSD3_
133 ETPUA19_PCSD4_
134 ETPUA20_IRQ8_
135 ETPUA21_IRQ9_
136 ETPUA22_IRQ10_
16 Freescale Semiconductor
137 ETPUA23_IRQ11_
138 ETPUA24_IRQ12_
139 ETPUA25_IRQ13_
140 ETPUA26_IRQ14_
141 ETPUA27_IRQ15_
142 ETPUA28_PCSC1_
143 ETPUA29_PCSC2_
144 ETPUA30_PCSC3_
145 ETPUA31_PCSC4_
146 TCRCLKB_IRQ6_
147 ETPUB0_ETPUB16_
148 ETPUB1_ETPUB17_
18 Freescale Semiconductor
149 ETPUB2_ETPUB18_
150 ETPUB3_ETPUB19_
151 ETPUB4_ETPUB20_
152 ETPUB5_ETPUB21_
153 ETPUB6_ETPUB22_
154 ETPUB7_ETPUB23_
155 ETPUB8_ETPUB24_
156 ETPUB9_ETPUB25_
157 ETPUB10_ETPUB26_
158 ETPUB11_ETPUB27_
159 ETPUB12_ETPUB28_
160 ETPUB13_ETPUB29_
20 Freescale Semiconductor
161 ETPUB14_ETPUB30_
162 ETPUB15_ETPUB31_
163 ETPUB16_PCSA1_
164 ETPUB17_PCSA2_
165 ETPUB18_PCSA3_
166 ETPUB19_PCSA4_
167 ETPUB20_
168 ETPUB21_
169 ETPUB22_
170 ETPUB23_
171 ETPUB24_
172 ETPUB25_
22 Freescale Semiconductor
173 ETPUB26_
174 ETPUB27_
175 ETPUB28_
176 ETPUB29_
177 ETPUB30_
178 ETPUB31_
440 TCRCLKC_
441 ETPUC0_
442 ETPUC1_
443 ETPUC2_
444 ETPUC3_
445 ETPUC4_
24 Freescale Semiconductor
446 ETPUC5_
447 ETPUC6_
448 ETPUC7_
449 ETPUC8_
450 ETPUC9_IRQ0_
451 ETPUC10__IRQ1_
452 ETPUC11_IRQ2_
453 ETPUC12_IRQ3_
454 ETPUC13_3_IRQ4_
455 ETPUC14_4_IRQ5_
456 ETPUC15__
457 ETPUC16_FR_A_TX_
26 Freescale Semiconductor
458 ETPUC17_FR_A_RX_
460 ETPUC19_TXDA_
461 ETPUC20_RXDA _
462 ETPUC21_TXDB_
463 ETPUC22_RXDB_
464 ETPUC23_PCSD5_
465 ETPUC24_PCSD4_
466 ETPUC25_PCSD3_
467 ETPUC26_PCSD2_
468 ETPUC27_PCSD1_
28 Freescale Semiconductor
469 ETPUC28_PCSD0_
470 ETPUC29_SCKD_
471 ETPUC30_SOUTD_
472 ETPUC31_SIND_
179 EMIOS0_ETPUA0_
180 EMIOS1_ETPUA1_
181 EMIOS2_ETPUA2_
182 EMIOS3_ETPUA3_
183 EMIOS4_ETPUA4_
184 EMIOS5_ETPUA5_
185 EMIOS6_ETPUA6_
186 EMIOS7_ETPUA7_
30 Freescale Semiconductor
187 EMIOS8_ETPUA8_
188 EMIOS9_ETPUA9_
189 EMIOS10_SCKD_
190 EMIOS11_SIND_
191 EMIOS12_SOUTC_
192 EMIOS13_SOUTD_
193 EMIOS14_IRQ0_
194 EMIOS15_IRQ1_
195 EMIOS16_ETPUB0_
196 EMIOS17_ETPUB1_
197 EMIOS18_ETPUB2_
198 EMIOS19_ETPUB3_
32 Freescale Semiconductor
199 EMIOS20_ETPUB4_
200 EMIOS21_ETPUB5_
201 EMIOS22_ETPUB6_
202 EMIOS23_ETPUB7_
203 EMIOS24_PCSB0_
204 EMIOS25_PCSB1_
432 EMIOS26_PCSB2_
433 EMIOS27_PCSB3_
434 EMIOS28_PCSC0_
435 EMIOS29_PCSC1_
436 EMIOS30_PCSC2_
437 EMIOS31_PCSC5_
34 Freescale Semiconductor
36 Freescale Semiconductor
248 FR_A_TX_
249 FR_A_RX_
38 Freescale Semiconductor
250 FR_A_TX_EN_
251 FR_B_TX_
252 FR_B_RX_
253 FR_B_TX_EN_
83 CNTXA_TXDA_
84 CNRXA_RXDA_
85 CNTXB_PCSC3_
86 CNRXB_PCSC4_
87 CNTXC_PCSD3_
88 CNRXC_PCSD4_
246 CNTXD_
247 CNRXD_
40 Freescale Semiconductor
89 TXDA_
90 RXDA _
91 TXDB_PCSD1_
92 RXDB_PCSD5_
244 TXDC_ETRIG0_
245 RXDC_
93 SCKA_PCSC1_
94 SINA_PCSC2_
95 SOUTA_PCSC5_
96 PCSA0_PCSD2_
97 PCSA1_
98 PCSA2_
42 Freescale Semiconductor
99 PCSA3_
100 PCSA4_
101 PCSA5_ETRIG1_
102 SCKB_
103 SINB_
104 SOUTB_
105 PCSB0_PCSD2_
106 PCSB1_PCSD0_
107 PCSB2_SOUTC_
108 PCSB3_SINC_
109 PCSB4_SCKC_
110 PCSB5_PCSC0_
44 Freescale Semiconductor
235 SCKC_SCK_C_LVDSP_
236 SINC_SCK_C_LVDSM_
237 SOUTC_SOUT_C_LVDSP_
238 PCSC0_SOUT_C_LVDSM_
239 PCSC1_
240 PCSC2_GPIO240 P PCSC2 DSPI C peripheral chip select O MH V DDEH5 —/Up —/Up AE23
241 PCSC3_GPIO241 P PCSC3 DSPI C peripheral chip select O MH V DDEH5 —/Up —/Up AD23
242 PCSC4_GPIO242 P PCSC4 DSPI C peripheral chip select O MH V DDEH5 —/Up —/Up AF24
243 PCSC5_GPIO243 P PCSC5 DSPI C peripheral chip select O MH V DDEH5 —/Up —/Up AE24
230 RSTOUT P RSTOUT External reset output O MH V DDEH1 RSTOUT/Low RSTOUT/
212 BOOTCFG1_IRQ3_
46 Freescale Semiconductor
213 WKPCFG_NMI_
208 PLLCFG0_IRQ4_
209 PLLCFG1_IRQ5_
214 ENGCLK P ENGCLK EBI engineering clock output
227 EVTO
219 MCKO –13 MCKO Nexus message clock out O F V DDE2 O/Low Disabled 14 T2
220 MDO0_GPIO220
221 MDO1_GPIO221
222 MDO2_GPIO222
223 MDO3_GPIO223
75 MDO4_GPIO75
76 MDO5_GPIO76
48 Freescale Semiconductor
77 MDO6_GPIO77
78 MDO7_GPIO78
79 MDO8_GPIO79
80 MDO9_GPIO80
81 MDO10_GPIO81
82 MDO11_GPIO82
231 MDO12_GPIO231 –13 MDO1215 Nexus message data out O F V DDE2 O/Low —/Down AA1
232 MDO13_GPIO232 –13 MDO1315 Nexus message data out O F V DDE2 O/Low —/Down AA2
233 MDO14_GPIO233 –13 MDO1415 Nexus message data out O F V DDE2 O/Low —/Down AA3
234 MDO15_GPIO234 –13 MDO1515 Nexus message data out O F V DDE2 O/Low —/Down Y4
224 MSEO0 –13 MSEO015 Nexus message start/end out O F V DDE2 O/Low MSEO/HI U2
225 MSEO1 –13 MSEO115 Nexus message start/end out O F V DDE2 O/Low MSEO/HI T3
226 RDY –13 RDY Nexus ready output O F V DDE2 O/Low RDY/HI R4
228 TDO –13 TDO JTAG test data output O F V DDE2 TDO/Up TDO/Up AB1
50 Freescale Semiconductor
have GPIO functionality, this number is the PCR number. and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type. 3 P/A/G stands for Primary/Alternate/GPIO. This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO. are designated in the PA field of the SIU_PCRn registers except where explicitly noted.
5 MH = High voltage, medium speed
(+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply. pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 51 9 This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C. 10 During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device. 11 NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers. 12 Nexus reset is different than system reset; MDO 1-11 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO and MCKO are also dependent on trace (RPM or FPM) being enabled. 13 The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU values have no effect on the function of these pins once enabled. 14 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register). 15 Do not connect pin directly to a power supply or ground.
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
5 Electrical characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the PXR40. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.
5.1 Maximum ratings
Table 3. Absolute maximum ratings1
5 Analog Supply Voltage (reference to V SSA
9 Analog Reference High Voltage (reference to V RL
10 V SS to VSSA
15 Maximum Digital Input Current 10 (per pin, applies to all
16 Maximum Analog Input Current 12 (per pin, applies to all
17 Maximum Operating Temperature Range 13 – Die Junction
19 Maximum Solder Temperature 14
20 Moisture Sensitivity Level 15 MSL — 3 —
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 53
5.2 Thermal characteristics
1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 2.0 V for 10 hours cumulative time, 1.32 V +10% for time remaining. 3 6.4 V for 10 hours cumulative time, 5.25 V +10% for time remaining. 4 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 5.3 V for 10 hours cumulative time, 3.60 V +10% for time remaining. 6 PXR40 has two analog power supply pins on the pinout: VDDA_A and VDDA_B. 7 PXR40 has two analog ground supply pins on the pinout: VSSA_A and VSSA_B. 8 PXR40 has two analog low reference voltage pins on the pinout: VRL_A and VRL_B. 9 PXR40 has two analog high reference voltage pins on the pinout: VRH_A and VRH_B. 10 Total injection current for all pins must not exceed 25 mA at maximum operating voltage. 11 Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under this stress condition. 12 Total injection current for all analog input pins must not exceed 15 mA. 13 Lifetime operation at these specification limits is not guaranteed. 14 Solder profile per CDF-AEC-Q100. 15 Moisture sensitivity per JEDEC test method A112. Table 4. Thermal characteristics, 416-pin TEPBGA package1
1 Thermal characteristics are targets based on simulation that are subject to change per device
characterization. This data is PRELIMINARY based on similar package used on other devices.
2 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
board, and board thermal resistance. 3 Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 4 Per JEDEC JESD51-6 with the board horizontal. temperature is measured on the top surface of the board near the package.
6 Indicates the average thermal resistance between the die and the case top surface as measured by the
7 Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
PXR40 Microcontroller Data Sheet, Rev. 1
5.2.1 General notes for specification s at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ =T A + (RJA * PD) Eqn. 1 where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R JA =R JC + RCA Eqn. 2 where: RJA = junction to ambient thermal resistance (oC/W) RJC = junction to case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ =T T + (JT x PD) Eqn. 3 where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International
3081 Zanker Road
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 55 San Jose, CA 95134 (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org.
- C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
- G . Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53-58, March 1998.
- B. Joiner and V . Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
5.3 EMI (Electromagnetic Interference) characteristics
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for “radiated emissions.” The following tables list the values of the device's radiated emissions operating behaviors. Table 5. EMC radiated emissions operating behaviors: 416 BGA
416 BGA
40 MHz crystal
264 MHz
2 I = 36 dBV
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5 K = 30 dBV
PXR40 Microcontroller Data Sheet, Rev. 1
5.4 ESD characteristics
5.5 PMC/POR/LVI electrical specifications
Note: For ADC internal resource measurements, see Table 18 in Section 5.9.1 ADC internal resource measurements. NOTE In the following table, “untrimmed” means “at reset” and “trimmed” means “after reset”. Table 6. ESD ratings 1,2
1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade
1 ESD for Human Body Model (HBM) V
2 ESD for Charged Device Model (CDM) VCDM 750 (corners)
Table 7. PMC operating conditions
1 Voltage should be higher than maximum VLVDREG to avoid LVD event
3 Voltage should be higher than maximum VLVD12 to avoid LVD event
Table 8. PMC electrical specifications
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 57 2a — Untrimmed VRC 1.2V output variation before band gap trim (unloaded) Note: Voltage should be higher than maximum VLVD12 to avoid LVD event VDD12OUT – 8% V DD12OUT VDD12OUT + 17% V 2b — Trimmed VRC 1.2V out put variation after band gap trim (REGCTL load max. 20mA, VDD load max. 1A) VDD12OUT – 5% V DD12OUT VDD12OUT + 10% V 2c V STEPV12 Trimming step VDD12OUT —1 0— m V 3V PORC POR rising VDD 1.2V — 0.7 — V 3a — POR VDD 1.2V variation V PORC – 30% V PORC VPORC + 30% 3b — POR 1.2V hysteresis — 75 — mV LVD12 Nominal rising LVD 1.2V Note: ~VDD12OUT × 0.87 — 1.100 — V 4a — Untrimmed LVD 1.2V variation before band gap trim Note: Rising VDD V LVD12 – 6% V LVD12 VLVD12 + 6% V 4b — Trimmed LVD 1.2V variation after band gap trim Rising VDD VLVD12 – 3% V LVD12 VLVD12 + 3% V 4c — LVD 1.2V Hysteresis 15 20 25 mV 4d V LVDSTEP12 Trimming step LVD 1.2V — 10 — mV 5I REGCTL VRC DC current output on REGCTL — — 20 mA 6 — Voltage regulator 1.2V current consumption VDDREG —3— m A 7V DD33OUT Nominal VREG 3.3V output — 3.3 — V 7a — Untrimmed V REG 3.3V output variation before band gap trim (unloaded) Note: Rising VDDSYN VDD33OUT – 6% V DD33OUT VDD33OUT + 10% V 7b — Trimmed V REG 3.3V output variation after band gap trim (max. load 80mA) VDD33OUT – 5% V DD33OUT VDD33OUT + 10% V 7c V STEPV33 Trimming step VDDSYN — 30 — mV 8V LVD33 Nominal rising LVD 3.3V Note: ~VDD33OUT × 0.872 — 2.950 — V 8a — Untrimmed LVD 3.3V variation before band gap trim Note: Rising VDDSYN VLVD33 – 5% V LVD33 VLVD33 + 5% V 8b — Trimmed LVD 3.3V variation after bad gap trim Note: Rising VDDSYN VLVD33 – 3% V LVD33 VLVD33 + 3% V 8c — LVD 3.3V Hysteresis — 30 — mV 8d V LVDSTEP33 Trimming step LVD 3.3V — 30 — mV Table 8. PMC electrical specifications (continued)
PXR40 Microcontroller Data Sheet, Rev. 1 9I DD33 VREG = 4.5 V, max DC output current VREG = 4.25 V, max DC output current, crank condition Note: Max current supplied by VDDSYN that does not cause it to drop below V LVD33 mA mA 10 — Voltage regulator 3.3V current consumption VDDREG Note: Except I DD33 —2— m A 11 V PORREG POR rising on VDDREG — 2.00 — V 11a — POR VDDREG variation V PORREG – 30% V PORREG VPORREG + 30% V 11b — POR VDDREG hysteresis — 250 — mV 12 V LVDREG Nominal rising LVD VDDREG (LDO3V / LDO5V mode) — 2.950 — V 12a — Untrimmed LVD VDDREG variation before band gap trim Note: Rising VDDREG VLVDREG – 5% V LVDREG VLVDREG + 5% V 12b — Trimmed LVD VDDREG variation after band gap trim Note: Rising VDDREG V LVDREG – 3% V LVDREG VLVDREG + 3% V 12c — LVD VDDREG Hysteresis (LDO3V / LDO5V mode) —3 0— m V 12d V LVDSTEPREG Trimming step LVD VDDREG (LDO3V / LDO5V mode) —3 0— m V
13 V LVDREG Nominal rising LVD VDDREG
(SMPS5V mode) — 4.360 — V 13a — Untrimmed LVD VDDREG variation before band gap trim Note: Rising VDDREG VLVDREG – 5% V LVDREG VLVDREG + 5% V 13b — Trimmed LVD VDDREG variation after band gap trim Note: Rising VDDREG VLVDREG – 3% V LVDREG VLVDREG + 3% V 13c — LVD VDDREG Hysteresis (SMPS5V mode) —5 0— m V 13d V LVDSTEPREG Trimming step LVD VDDREG (SMPS5V mode) —5 0— m V 14 V LVDA Nominal rising LVD VDDA — 4.60 — V 14a — Untrimmed LVD VDDA variation before band gap trim VLVDA – 5% V LVDA VLVDA + 5% V 14b — Trimmed LVD VDDA variation after band gap trim VLVDA – 3% V LVDA VLVDA + 3% V 14c — LVD VDDA Hysteresis — 150 — mV
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 59
5.6 Power up/down sequencing
There is no power sequencing required among power sources during power up and power down in order to operate within specification as long as the following two rules are met:
- When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG .
- When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the internal 3.3V regulator. The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V first, and then drop all VDDE/VDDEH supplies. There is no limit on the fall time for the power supplies. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies according to Table 9 and Table 10. 14d V LVDASTEP Trimming step LVD VDDA — 20 — mV 15 — SMPS regulator output resistance Note: Pullup to VDDREG when high, pulldown to VSSREG when low. —1 52 5 O h m 16 — SMPS regulator clock frequency (after reset) 1.0 1.5 2.4 MHz 17 — SMPS regulator overshoot at start-up 2 —1 . 3 2 1 . 4 V 18 — SMPS maximum output current — 1.0 — A 19 — Voltage variation on current step 2 (20% to 80% of maximum current with 4 µsec constant time) —— 0 . 1 V 1 VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 µA. When using the recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core voltage is up to 1A. 2 Parameter cannot be tested; this value is based on simulation and characterization.
Table 9. Power sequence pin states for MH and AE pads 1 MH+LVDS pads are output-only.
PXR40 Microcontroller Data Sheet, Rev. 1
5.6.1 Power-up
If VDDE/VDDEH is powered up first, then a threshold detector tristates all drivers connected to VDDE/VDDEH. There is no limit to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit the characteristics described in the next paragraph. If VDD is powered up first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDD powers up before VDDE/VDDEH must power up. The rise times on the power supplies are to be no faster than 25 V/millisecond.
5.6.2 Power-down
If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD powers down before VDDE/VDDEH must power down. If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must power down. There are no limits on the fall times for the power supplies.
5.6.3 Power sequencing and POR dependent on V DDA
During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between VDDA and VDDEH is more than 1 V , the following will result:
- Triggers POR (ADC monitors on V DDEH1 segment which powers the RESET pin) if the leakage current path created, when VDDA is sufficiently low, causes sufficient voltage drop on VDDEH1 node monitored crosses low-voltage detect level.
- I f V DDA is between 0–2 V , powering all the other segments (especially VDDEH1) will not be sufficient to get the part out of reset.
- Each V DDEH will have a leakage current to VDDA of a magnitude of ((VDDEH –V DDA – 1 V(diode drop)/200 KOhms) up to (VDDEH/2 = VDDA +1V ) .
Table 10. Power sequence pin states for F and FS pads
1 The pad pre-drive circuitry will function normally but since VDDE is unpowered
the outputs will not drive high even though the output pmos can be enabled.
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 61
- Each V DD has the same behavior; however, the leakage will be small even though there is no current limiting resistor since VDD = 1.32 V max.
5.7 DC electrical specifications
Table 11. DC electrical specifications
9 Fast I/O Input High Voltage
10 Fast I/O Input Low Voltage
11 Medium I/O Input High Voltage
12 Medium I/O Input Low Voltage
20 Load Capacitance (Fast I/O) 12
PXR40 Microcontroller Data Sheet, Rev. 1
21 Input Capacitance (Digital Pins) C IN —7 p F
22 Input Capacitance (Analog Pins) C IN_A —1 0 p F
24 Operating Current 1.2 V Supplies @ f sys = 264 MHz VDD @1.32 V VSTBY 13 @1.2 V and 85oC VSTBY @6.0 V and 85oC IDD IDDSTBY IDDSTBY6 1.014 0.10 0.15 A mA mA 25 Operating Current 3.3 V Supplies @ f sys = 264 MHz VDD33 VDDSYN IDD33 IDDSYN note15 716 mA mA 26 Operating Current 5.0 V Supplies @ f sys = 264 MHz VDDA Analog Reference Supply Current (Transient) VDDREG IDDA IREF IREG 5017 1.0 mA mA mA
27 Operating Current V DDE/VDDEH
18 Supplies
28 Fast I/O Weak Pull Up/Down Current
3.0 V–3.6 V I ACT_F 42 158 A
29 Medium I/O Weak Pull Up/Down Current 20
3.0 V–3.6 V 4.5 V–5.5 V I ACT_S 200 30 I/O Input Leakage Current 21 IINACT_D –2.5 2.5 A 31 DC Injection Current (per pin) I IC –1.0 1.0 mA
32 Analog Input Current, Channel Off 22, AN[0:7], AN38,
Analog Input Current, Channel Off, all other analog inputs AN[x] IINACT_A –250 –150 250 150 nA nA
33 V SS Differential Voltage V SS –V SSA –100 100 mV
34 Analog Reference Low Voltage V RL V SSA V SSA +1 0 0 m V
35 V RL Differential Voltage V RL –V SSA –100 100 mV
36 Analog Reference High Voltage V RH V DDA –1 0 0 V DDA mV
37 V REF Differential Voltage V RH –V RL 4.75 5.25 V
38 V SSSYN to VSS Differential Voltage V SSSYN –V SS –100 100 mV
39 Operating Temperature Range—Ambient (Packaged) TA (TL to TH) –40.0 125.0 C
40 Slew rate on power supply pins — — 25 V/ms
Table 11. DC electrical specifications (continued)
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 63
41 Weak Pull-Up/Down Resistance 23, 200 K Option R PUPD200K 130 280 k
42 Weak Pull-Up/Down Resistance 23, 100 K Option R PUPD100K 65 140 k
43 Weak Pull-Up/Down Resistance 23, 5 K Option R PUPD5K 1.4 7.5 k
44 Pull-Up/Down Resistance Matching Ratios 24
(100K/200K) RPUPDMTCH –2.5 +2.5 % 1 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 2 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 3 Assumed with DC load. 4 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 5 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining. 6 VSTBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode. 7 Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with VDDREG = 4.5 V (min). 8 2.7 V minimum operating voltage allowed during vehicle crank for system with VDDREG = 3.0 V (min). Normal operating voltage should be either VDDREG = 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected. 9 Required to be supplied when 3.3 V regulator is disabled. See Section 5.5 PMC/POR/LVI electrical specifications. 10 IOH_F = {16,32,47,77} mA and IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V. This spec is for characterization only. 11 IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDE =4 . 5V ; 12 Applies to D_CLKOUT, external bus pins, and Nexus pins. 13 VSTBY current specified at 1.0 V at a junction temperature of 85 oC. VSTBY current is 700 µA maximum at a junction temperature of 150 oC. 14 Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization. 900 mA based on transistor count estimate at Worst Case (wcs) process and temperature condition. 15 Power requirements for the VDD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Section 5.7.2 I/O pad VDD33 current specifications, for information on both fast (F , FS) and medium (MH) pads. Also refer to Table 13 for values to calculate power dissipation for specific operation. 16 This value is a target that is subject to change. 17 This value allows a 5 V reference to supply ADC + REF . 18 Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Section 5.7.1 I/O pad current specifications, for information on I/O pad power. Also refer to Table 12 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 22 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8t o1 2 oC, in the ambient temperature range of 50 to 125oC. Applies to pad types AE and AE/up-down. See Section 4 Signal properties and muxing. 23 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics 24 Pull-up and pull-down resistances are both enabled and settings are equal.
PXR40 Microcontroller Data Sheet, Rev. 1
5.7.1 I/O pad current specifications
The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 12 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 12. The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications.
5.7.2 I/O pad V DD33 current specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be calculated from Table 13 dependent on the voltage, frequency, and load on all F type pins. The VDD33 current draw on medium pads can be calculated from Table 13 dependent on voltage and independent on the frequency and load on all MH type pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 13. The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications. Table 12. VDDE/VDDEH I/O Pad Average DC Current1 1 These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.
9 Fast w/ Slew
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 65
5.7.3 LVDS pad specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI module. Table 13. VDD33 Pad Average DC Current1 pins only for the medium pads. Table 14. DSPI LVDS pad specification # Characteristic Symbol Condition Min.
1 Data Frequency f LVDSCLK —— 5 0 — M H z
2 Differential output voltage V OD SRC=0b00 or 0b11 150 — 400 mV
3 Common mode voltage (LVDS),
4 Rise/Fall time T R/TF —— 2 — n s
5 Propagation delay (Low to High) T PLH —— 4 — n s
6 Propagation delay (High to Low) T PHL —— 4 — n s
7 Delay (H/L), sync Mode t PDSYNC —— 4 — n s
8 Delay, Z to Normal (High/Low) T DZ —— 5 0 0 — n s
PXR40 Microcontroller Data Sheet, Rev. 1
5.8 Oscillator and FMPLL electrical characteristics
9 Diff Skew Itphla-tplhbI or
TSKEW —— — 0 . 5 n s Termination 10 Trans. Line (differential Zo) — — 95 100 105 ohms
11 Temperature — — –40 — 150 C
Table 15. FMPLL Electrical Specifications1 1 All values given are initial design targets and subject to change.
1 PLL Reference Frequency Range 2 (Normal Mode)
PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz. 3 Upper tolerance of less than 1% is allowed on 40MHz crystal.
2 Loss of Reference Frequency 4
4 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
3 Self Clocked Mode Frequency 5
4 PLL Lock Time 6 tLPLL — < 400 s
5 Duty Cycle of Reference 7 tDC 40 60 %
8 D_CLKOUT Period Jitter 8, 9 Measured at fSYS Max
9 Peak-to-Peak Frequency Modulation Range Limit 10,11
11 VCO Frequency f VCO 192 600 MHz
13 Predivider output frequency range 14 fprediv 41 0 M H z
Table 14. DSPI LVDS pad specification (continued)
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 67 6 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal startup time. 7 For Flexray operation, duty cycle requirements are higher. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. D_CLKOUT divider set to divide-by-2. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter +C mod. 10 Modulation depth selected must not result in fpll value greater than the fpll maximum specified value. 11 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in control register are: 2%, 3%, and 4% peak-to-peak. 12 Depth tolerance is the programmed modulation depth ±0.25% of Fsys. Violating the VCO min/max range may prevent the system from exiting reset. 13 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz will result in reduced calibration accuracy. 14 Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset. Table 16. Oscillator electrical specifications1 1 All values given are initial design targets and subject to change.
1 Crystal Mode Differential Amplitude 2
2 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal –V xtal 400 mV criterion has to be met for oscillator’s comparator to produce output clock.
2 Crystal Mode: Internal Differential Amplifier Noise
3 EXTAL Input High Voltage
4 EXTAL Input Low Voltage
5 XTAL Current 3
3 Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
8 Crystal manufacturer’s recommended capacitive load C L See crystal spec See crystal spec pF
9 Discrete load capacitance to be connected to EXTAL C L_EXTAL — (2 × CL –C S_EXTAL
4 CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10 Discrete load capacitance to be connected to XTAL C L_XTAL — (2 × CL –C S_XTAL
PXR40 Microcontroller Data Sheet, Rev. 1 5.9 eQADC electrical characteristics Table 17. eQADC Conversion Specifications (Operating)
1 ADC Clock (ADCLK) Frequency f ADCLK 21 6 M H z
2 Conversion Cycles
conversion values listed here.
3 Stop Mode Recovery Time
the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.
4 Resolution 2
2 At VRH –V RL = 5.12 V, one count = 1.25 mV without using pregain.
5 INL: 8 MHz ADC Clock 3
(12 bit resolution selected).
44 LSB5
6 INL: 16 MHz ADC Clock 3 INL16 –8 4 84 LSB
7 DNL: 8 MHz ADC Clock 3 DNL8 –3 4 34 LSB
8 DNL: 16 MHz ADC Clock 3 DNL16 –3 4 34 LSB
9 Offset Error without Calibration OFFNC 0 4 1004 LSB
10 Offset Error with Calibration OFFWC –4 4 44 LSB
11 Full Scale Gain Error without Calibration GAINNC –120 4 04 LSB
12 Full Scale Gain Error with Calibration GAINWC –4 4,6
6 The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.
13 Non-Disruptive Input Injection Current 7, 8, 9, 10
VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions.
14 Incremental Error due to injection current 11, 12 EINJ –44 44 Counts
15 TUE value at 8 MHz 13, 14
16 TUE value at 16 MHz 13, 14 (with calibration) TUE16 –8 8 Counts
17 Maximum differential voltage 15
18 Differential input Common mode voltage
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 69
5.9.1 ADC internal re source measurements
8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP =V DDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values. 10 Condition applies to two adjacent pins at injection limits. 11 Performance expected with production silicon. 12 All channels have same 10 k <R s<1 0 0k Channel under test has Rs = 10 k, IINJ=IINJMAX,IINJMIN. 13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors. 14 TUE does not apply to differential conversions. 15 Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode voltage of the differential signal violates the Differential Input common mode voltage specification. Table 18. Power Management Control (PMC) specification
3 Vreg1p2 Feedback
5 Vreg3p3 Feedback
PXR40 Microcontroller Data Sheet, Rev. 1 Table 19. Standby RAM regulator electrical specifications
1 Standby Regulator Output
2 Standby Source Bias
3 Standby Brownout Reference
Table 20. ADC band gap reference / LVI electrical specifications
2 ADC Bandgap
Table 21. Temperature sensor electrical specifications 1 Slope is the measured voltage change per °C.
2 Accuracy
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 71
5.10 C90 flash memory electrical characteristics
Table 24 shows the Platform Flash Configuration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. Table 22. Flash program and erase specifications 1 Typical program and erase times assume nominal supply values and operation at 25oC. 2 Initial factory condition: 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency.
1 Double Word (64 bits) Program Time 4
4 Program times are actual hardware programming times and do not include software overhead.
2 Page Program Time 4,5
5 Page size is 128 bits (4 words). Table 23. Flash EEPROM module life
1 Number of program/erase cycles per block for 16 KB and 64
2 Number of program/erase cycles per block for 128 KB and 256
3 Minimum Data Retention at 85 °C ambient temperature2
2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
PXR40 Microcontroller Data Sheet, Rev. 1 Table 24. PFCPR1 settings vs. frequency of operation1 1 Illegal combinations exist. Use entries from the same row in this table. 2 This is the nominal maximum frequency of operation: platform runs at fsys/2 in Enhanced Mode . 3 For maximum flash performance, set to 0b1. 4 For maximum flash performance, set to 0b10. 5 For maximum flash performance, set to 0b1.
1 Enhanced 264 MHz 6
and 132 Mhz platform clock (fplatf)+ 2% FM.
132 MHz6 0b011 0b01 0b0
2 Enhanced/
200 MHz 100 MHz 0b010 0b01 0b0
3 Legacy 132 MHz 132 MHz 0b100 0b01 0b0
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 73
5.11 AC specifications
5.11.1 Clocking
Figure 8 shows the operating frequency domains of various blocks on PXR40. Figure 8. PXR40 block operating frequency domain diagram Table 26 and Table 27 for descriptions of bit settings). Table 25. PXR40 operating frequencies1, 2
1 The values in the table are specified at:
PXR40 Microcontroller Data Sheet, Rev. 1
5.11.2 Pad AC specifications
2 Up to the maximum frequency rating of the device (refer to Table 39). The fsys speed is the nominal maximum frequency. 270 Mhz parts allow for 264 Mhz system clock + 2% FM. 3 See the PXR40 Reference Manual for full description as not all bit combinations are valid. 4 EBI/Calibration bus is not available in all packages. 5 The EBI/Calibration Bus operating frequency, febi_cal , depends on clock divider settings of block’s max allowed frequency of operation. Normally febi_cal =f platf /2, but can be limited to < fplatf /2 in Full Mode. Table 26. IPCLKDIV settings 01 Full CPU and eTPU frequency is doubled (Max 200Mhz). Platform and peripheral clocks are 1/2 of CPU frequency.
11 Legacy CPU, eTPU, platform, and peripheral’s clocks all run at
Table 27. SYSCLKDIV settings Table 28. Pad AC specifications (vddeh = 5.0 V, VDDE =3 . 3V )1
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 75 7F a s t 6 00 2.5 1.2 80 1 2 0 91 0 3 0 10 11 50
11 Fast with Slew Rate 00 40/40 16/16 50
15 10 8/8 2.4/2.4 50 16 12/12 5/5 200 17 11 5/5 1.1/1/1 50 18 8/8 2.6 2.6 19 Pull Up/Down (3.6 V max) — — 7500 50 20 Pull Up/Down (5.25 V max) — 6000 5000/5000 50 1 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at 2 This parameter is supplied for reference and is not guaranteed by design and not tested. 3 This parameter is guaranteed by characterization before qualification rather than 100% tested. 4 Delay and rise/fall are measured to 20% or 80% of the respective signal. 5 Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock. 6 Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock. Table 29. Derated pad AC specifications (VDDEH =3 . 3V )1 2 This parameter is supplied for reference and is not guaranteed by design and not tested. 3 Delay and rise/fall are measured to 20% or 80% of the respective signal. 4 This parameter is guaranteed by characterization before qualification rather than 100% tested.
1 Medium 5
5 Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock. Table 28. Pad AC specifications (vddeh =5 . 0V , VDDE =3 . 3V )1 (continued)
PXR40 Microcontroller Data Sheet, Rev. 1 Figure 9. Pad output delay
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 77
5.12 AC timing
5.12.1 Generic timing diagrams
The generic timing diagrams in Figure 10 and Figure 11 apply to all I/O pins with pad types F and MH. See 4, Signal properties and muxing, for the pad type for each pin. Figure 10. Generic output delay/hold timing Figure 11. Generic input setup/hold timing
PXR40 Microcontroller Data Sheet, Rev. 1
5.12.2 Reset and configuration pin timing
Figure 12. Reset and configuration pin timing Table 30. Reset and configuration pin timing1
1 RESET Pulse Width t RPW 10 — t cyc
2 See Notes on tcyc on Figure 8 and Table 25 in S e c t i o n5 . 1 1 . 1C l o c k i n g.
2 RESET Glitch Detect Pulse Width t GPW 2— t cyc
3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid t RCSU 10 — t cyc
4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid t RCH 0— t cyc
Table 31. JTAG pin AC electrical characteristics1
1 TCK Cycle Time t JCYC 100 — ns
2 TCK Clock Pulse Width (Measured at V DDE / 2) t JDC 40 60 ns
3 TCK Rise and Fall Times (40%–70%) t TCKRISE —3 n s
4 TMS, TDI Data Setup Time t TMSS, tTDIS 5— n s
5 TMS, TDI Data Hold Time t TMSH, tTDIH 25 — ns
6 TCK Low to TDO Data Valid t TDOV —1 0 n s
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 79 Figure 13. JTAG test clock input timing
7 TCK Low to TDO Data Invalid t TDOI 0— n s
8 TCK Low to TDO High Impedance t TDOHZ —2 0 n s
9 JCOMP Assertion Time t JCMPPW 100 — ns
10 JCOMP Setup Time to TCK Low t JCMPS 40 — ns
11 TCK Falling Edge to Output Valid t BSDV —5 0 n s
12 TCK Falling Edge to Output Valid out of High Impedance t BSDVZ —5 0 n s
13 TCK Falling Edge to Output High Impedance t BSDHZ —5 0 n s
14 Boundary Scan Input Valid to TCK Rising Edge t BSDST 50 — ns
15 TCK Rising Edge to Boundary Scan Input Invalid t BSDHT 50 — ns
Table 31. JTAG pin AC electrical characteristics1 (continued)
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 81 Figure 16. JTAG boundary scan timing
5.12.4 Nexus timing
Table 32. Nexus debug port timing1
1 MCKO Cycle Time t MCYC 22 8t CYC
2 MCKO Duty Cycle t MDC 40 60 %
7 EVTO Pulse Width t EVTOPW 1— t MCYC
8 TCK Cycle Time t TCYC 45 —t CYC
9 TCK Duty Cycle t TDC 40 60 %
PXR40 Microcontroller Data Sheet, Rev. 1 Figure 17. Nexus timings
10 TDI, TMS Data Setup Time t NTDIS, tNTMSS 8— n s
11 TDI, TMS Data Hold Time T NTDIH, tNTMSH 5— n s
12 TCK Low to TDO Data Valid t NTDOV 01 0 n s
13 RDY Valid to MCKO6 —— ——
on the system frequency, not to exceed maximum Nexus AUX port frequency. 3 See Notes on tcyc on Figure 13 and Table 25 in Section Section 5.11.1 Clocking. 4 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 5 Lower frequency is required to be fully compliant to standard. 6 The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly. Table 32. Nexus debug port timing1 (continued)
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 83 Figure 18. Nexus TCK, TDI, TMS, TDO timing
PXR40 Microcontroller Data Sheet, Rev. 1
5.12.5 External Bus Interface (EBI) timing
Table 33. Bus operation timing 1 1 D_CLKOUT Period t C 15.2 — ns Signals are measured at 50% V DDE.
2 D_CLKOUT Duty Cycle t CDC 45% 55% t C
3 D_CLKOUT Rise Time t CRT —— 4 ns
5 D_CLKOUT Posedge to Output
6 D_CLKOUT Posedge to Output
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 85 Figure 19. D_CLKOUT timing
7 Input Signal Valid to D_CLKOUT
8 D_CLKOUT Posedge to Input
ALE is measured at 50% of VDDE. 2 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system clock + 2% FM. 3 Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency. The maximum external bus frequency is 66 MHz. 4 Refer to Fast pad timing in Table 28 and Table 29. temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit. Table 33. Bus operation timing 1 (continued)
PXR40 Microcontroller Data Sheet, Rev. 1 Figure 20. Synchronous output timing
PXR40 Microcontroller Data Sheet, Rev. 1
5.12.6 External interrupt timing (IRQ pin)
Figure 23. External interrupt timing Table 34. External interrupt timing1
1 IRQ Pulse Width Low t IPWL 3— t cyc
2 See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking.
2 IRQ Pulse Width High t IPWH 3— t cyc
3 IRQ Edge to Edge Time 3
3 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. Table 35. eTPU timing1 and CL = 200 pF with SRC = 0b00. 2 See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking. and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 89 Figure 24. eTPU timing Table 36. eMIOS timing1 and CL = 50 pF with SRC = 0b00. 2 See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking. and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
PXR40 Microcontroller Data Sheet, Rev. 1 Figure 25. eMIOS timing
5.12.9 DSPI timing
Table 37. DSPI timing1 2
1 DSPI Cycle Time 3, 4
2 PCS to SCK Delay 5 tCSC 12 — ns
3 After SCK Delay 6
5 Slave Access Time
6 Slave SOUT Disable Time
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 91 The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol. DSPI pins support 5 V logic levels or Low V oltage Differential Signalling (LVDS) for data and clock signals to improve high speed operation.
9 Data Setup Time for Inputs
Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) tSUI ns ns ns ns
10 Data Hold Ti me for Inputs
Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) tHI ns ns ns ns
11 Data Valid (after SCK edge)
Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) t SUO ns ns ns ns
12 Data Hold Ti me for Outputs
Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) t HO 2.5 ns ns ns ns 2 Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (fsys) + 2% FM. 3 The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two devices communicating over a DSPI link. 4 The actual minimum SCK cycle time is limited by pad performance. 5 The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK]. 6 The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC]. 7 For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS 8 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10. Table 38. DSPI LVDS timing1, 2 1 These are typical values that are estimated from simulation. 2 See DSPI LVDS Pad related data in Table 14. Table 37. DSPI timing1 2 (continued)
PXR40 Microcontroller Data Sheet, Rev. 1
Ordering information
6 Ordering information
6.1 Orderable parts
Figure 35 and Table 39 describe and list the orderable part numbers for the PXR40. Figure 35. PXR40 orderable part number description Table 39. PXR40 orderable part number summary Note: Not all options are available on all devices. See Table 39 for more information.
Package information
PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 97
7 Package information
7.1 416-pin package The package drawings of the 416-pin TEPBGA package are shown in Figure 36 and Figure 37. Figure 36. 416 TEPBGA package (1 of 2)
PXR40 Microcontroller Data Sheet, Rev. 1 Figure 37. 416 TEPBGA package (2 of 2)
8 Product documentation
types are available at: http://www.freescale.com.
- PXR40 Microprocessor Reference Manual (document number PXR40RM).
9 Revision history
Table 40 describes the changes made to this document between revisions. Table 40. Revision history
1 September 2011 Initial release: Technical Data
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