SPWNE555D SECOS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 5

Technical content

Features

The SPWNE555D is a highly stable timer integrated circuit. It can be operated in Astable mode and Monostable mode. With monostable operation, the time delay is controlled by one external and one capacitor. With a stable operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor. * Precistion Timing * Pulse Generation * Time Delay Generation

Applications

Description

01-Jun-2002 Rev. A Page 1 of 5 http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual R o H S C o m p l i a n t P r o d u c t L A SEATING PLANE eb ZZ E D c SECTION Z - Z b GAUGE PLANE DIP-8 A - 0.5334 c1 0.203 0.279 A1 0.381 - D 9.017 10.16 A2 2.921 4.953 E 6.096 7.112 b 0.356 0.559 E1 7.620 8.255 b1 0.356 0.508 e 2.540 BSC b2 1.143 1.778 HE - 10.92 b3 0.762 1.143 L 2.921 3.810 c 0.203 0.356 rogrammed by pacitor CT to ground .Operation 500kHz nts up to This is the reference output .It provides charging current for capacitor CT Block Diagram & Pin Configuration

http:/ 01-Jun-2002 Rev. A Page 2 of 5 /www.SeCoSGmbH.com/ Elektronische Bauelemente A ny changing of specification will not be informed individual this pin (with a 5.0uF capacitor at Pin 2) on time of the circuit is affected by the nd resistor set low frequency rolloff and input impedance. The Absolute Maximum Ratings (Ta=25::::) Parameter Symbol Value Unit Supply Voltage VCC 16 V Output Current IO 200 mA Power Dissipation Pd 600 mW Lead Temperature (10sec) Tlead 300 : Operating Temperature Topr 0 ~ 70 : Storage Temperature Tstg -65 ~ 150 : Electrical Characteristics (TA=25: VCC=5 ~ 15V) Parameter Symbol Test Conditions Min Typ. Max. Unit Supply Voltage VCC 4.5 - 16 V VCC=5V, RL= - 3 6 mA Supply Current (Note 1) ICC VCC=15V, RL= - 10 15 mA Timing Error(monostable) Initial Accurary (Note 1) ACCUR RA=1k to 100k - 1.0 - % Drift with Temperature æt/æT C=0.1F - 50 - ppm/: Drift with Supply Voltage æt/æVCC - 0.1 - %/V Timing Error(astable) Initial Accurary (Note 1) ACCUR RA=1k to 100k - 2.25 - % Drift with Temperature æt/æT C=0.1F - 150 - ppm/: Drift with Supply Voltage æt/æVCC - 0.3 - %/V Threshold Current (Note 3) ITH - 0.1 0.25 A Trigger Current Itr Vtr=0 - - 2.0 A Reset Voltage Vrst 0.4 0.7 1.0 V Reset Current Irst - 0.1 0.4 mA VCC=15V, Isink=10mA - 0.06 0.25 VCC=15V, Isink=50mA - 0.3 0.75 Low Output Voltage VOL VCC=5V, Isink=5mA - 0.05 0.35 V VCC=15V, Isink=200mA - 12.5 - VCC=15V, Isink=100mA 12.75 13.3 15 High Output Voltage VOH VCC=5V, Isink=100mA 2.75 3.3 5 V Reset Time of Output tR - 100 - nSec Fall Time of Output tF - 100 - nSec Discharge leakage Current ILKG - 20 100 nA Note1: Supply current when output is high typically 1mA less at VCC=5V. Note2: Tested at VCC=5V and VCC=15V. Note3: This will determine the maximum value of RA+RB for 15V operation, the maximum total is R=20M, and for 5V operation the maximum total is R=6.7M. SPWNE555D Single Timer

01-Jun-2002 Rev. A Page 3 of 5 ht tp://www.SeCoSGmbH.com/ A ny changing of specification will not be informed individual Elektronische Bauelemente (UVLO) VCC = 15 V Characteristics Curve SPWNE555D Single Timer

01-Jun-2002 Rev. A Page 4 of 5 http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual vs. Output Power ŁŁŁŁ Load SPWNE555D Single Timer

http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 5 of 5 Application Circuit Application Notes The application circuit shows astable mode configuration. Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1 of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of SPWNE555D, one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is connected to Pin 6. As soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is a t voltage of 1/3V CC, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop circuit is set output high. That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is 0.693RB*C1. In =0.693 T1=0.693*(RA+RB)*C1 Thus the total period time T is given by T2=0.693*RB*C1 T=T1+T2=0.693(RA+2RB)*C1. Then the frequency of astable mode is given by f = = The duty cycle is given by D.C. = = . FLIP-FLOP

3 Vcc- Vcc

T (RA+2RB)*C1 1.44 T RA+2RB RB RA+2RB T2 RB Vcc Vcc Vcc VccVcc Vcc (RA+2RB)*C1 1.44 SPWNE555D Single Timer