Datasheet - SPV1050 - Ultralow power energy harvester and battery charger
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 30
Technical content
Features
- Transformerless thermoelectric generators and PV modules energy harvester
- High efficiency for any harvesting source
- Up to 70 mA output current
- Fully integrated MOSFETs for Boost or Buck-boost configurations
- Selectable enable/disable MPPT functionality
- Programmable MPPT by external resistors
- 2.6 V to 5.3 V trimmable output overvoltage level (± 1% accuracy)
- 2.2 V to 3.6 V trimmable output undervoltage level (± 1% accuracy)
- Two fully independent LDOs (1.8 V and 3.3 V output)
- Enable/disable LDO pins
- Load disconnect function (by-pass transistor open) prior the first start-up (Cold Start) to avoid battery lifetime shortening
- Battery Connected and DC-DC switching open drain indication pins
Applications
- Internet of things
- Remote control
- Fleet and livestock tracking
- Agriculture sensors
- Toll-pay
- Electronic labels
- Smart watch and wearable.
Description
The SPV1050 is an ultra-low power and high-efficiency power manager embedding four MOSFETs for boost or buck-boost DC-DC converter and an additional transistor for the load connection/disconnection. An internal high accuracy MPPT algorithm can be used to maximize the power extracted from PV panel or TEG. The internal logic works to guarantee tight monitoring of both the end-of-charge voltage (VEOC) and the minimum battery voltage (VUVP) by opening the pass- transistor at triggering of the VEOC threshold or at triggering of the VUVP threshold to preserve the battery life. Both the VEOC and VUVP thresholds can be trimmed by external resistors connected between the STORE rail and the EOC and UVP pins, respectively. In boost configuration (CONF pin connected to the supply source), the IC requires 550 mV and 30 μA to Cold start; while after the first start-up the input voltage can range between 150 mV and VEOC. In buck-boost configuration (CONF pin connected to ground), the IC requires 2.6 V and 5 μA at Cold start; while after the first start-up input voltage can range between 150 mV up to 18 V. The STORE pin is available as unregulated voltage output (e.g. to supply by external LDO a micro-controller), while two fully independent LDOs (1.8 V and 3.3 V) are embedded for powering other companion ICs like MCU, sensors or RF transceivers. Both LDOs can be independently enabled through the related pins. Product status link SPV1050 Product label Ultralow power energy harvester and battery charger SPV1050 Datasheet DS10044 - Rev 8 - March 2024 For further information contact your local STMicroelectronics sales office.
1 Block Diagram
Figure 1. Block diagram
2 Pin configurations
Figure 2. Pin configurations
3 Pin description
Table 1. Pin description
1 MPP I
2 MPP_SET I
MPPT enable/disable and setting voltage pin. is deactivated for 400 ms (typical value) every 16 s (typical value). periodic deactivation of the embedded DC-DC.
3 MPP_REF I
can be supplied by the source. (% of the open circuit voltage of the source) VMPP_REF. 4 GND GND Signal ground pin. setting, the LDO1 is not active when the internal pass transistor is open. setting, the LDO2 is not active when the internal pass transistor is open.
7 BATT_CHG O DC-DC operation output flag pin (open drain): if low, it indicates that the
DC-DC is switching; if high, it indicates that the DC-DC is not switching.
8 BATT_CONN O
9 EOC I
Load overvoltage/battery end of charge protection pin. than the internal bandgap voltage (VBG = 1.23 V, typical value). bandgap voltage makes the internal pass transistor gets closed.
10 UVP I
Load/battery undervoltage protection pin. pin goes below the internal bandgap voltage (VBG = 1.23 V, typical value). 11 LDO1 O 1.8 V regulated output voltage pin. 12 LOD2 O 3.3 V regulated output voltage pin.
13 CONF I
DC-DC converter configuration pin. Boost configuration: CONF pin connected to the input supply source. Buck-boost configuration: CONF pin connected to ground.
Pin no. (VFQFPN 20) Name Type Description 14 BATT I/O Battery connection pin. 15 STORE I/O Tank capacitor connection pin. Application load, if any, should be connected to STORE or LDOs pins.
16 IN_LV I
Low voltage input source. It has to be connected to one side of the inductor for both boost and buck- boost configurations. 17 NC - Not connected. 18 PGND PGND Power ground pin.
19 L_HV I
Input pin for buck-boost configuration. Boost configuration: to be connected to ground. Buck-boost configuration: to be connected to one side of the inductor.
20 IN_HV I
High voltage input source. Boost configuration: to be connected to ground. Buck-boost configuration: to be connected to the input supply source. EP Exposed Pad GND Connect to ground layer of the application board. It's warmly recommended a direct connection (without any vias) between EP, GND, PGND and the ground net of the tank capacitor on STORE pin. SPV1050 Pin description DS10044 - Rev 8 page 5/30
4 Maximum ratings
Table 2. Absolute maximum ratings Table 3. Thermal data
- Measured on 2-layer application board FR4, Cu thickness = 17 um with total exposed pad area = 16 mm2
- Maximum power dissipation = 1.3W (@TAMB = 85oC; Rth(JA) = 49oC/W)
5 Electrical characteristics
VSTORE = 4 V; -40 °C < TJ < 85 °C, unless otherwise specified. Voltage with respect to GND, unless otherwise specified Table 4. Electrical characteristics
Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit ISU Cold start minimum input current Boost configuration - 30 - μA Buck-boost configuration - 5 - VEN_TH DC-DC switching enable threshold Voltage checked during TSAMPLE 0.1 0.15 V VIN_LV Input voltage range Boost configuration VEN_TH - VEOC V VIN_HV Buck-boost configuration VEN_TH - 18 R-ONB Low-side MOS resistance Boost configuration 0.5 1.0 1.5 Ω SR-ONB Synchronous rectifier MOS resistance 0.5 1.0 1.5 R-ONBB Low-side MOS resistance Buck-boost configuration 1 1.5 2 Ω SR-ONBB Synchronous rectifier MOS resistance 1 1.5 2 fSW Maximum allowed switching frequency Boost and buck-boost configurations - - 1 MHz UVLOH Undervoltage lockout activation threshold VSTORE increasing - 2.6 2.8 V UVLOL Undervoltage lockout deactivation threshold VSTORE falling 2 2.1 - V IL(PEAK) DC-DC input current high peak threshold DC-DC active and input current rising (TAMB = 25oC) 85 190 mA IL(ZC) DC-DC output current low threshold DC-DC active and input current falling (TAMB = 25oC) 0 82 mA TON(MAX) DC-DC ON Time DC-DC maximum ON time 10 μs TOFF(MIN) DC-DC OFF Time DC-DC- minimum OFF time 0.2 μs MPPT TTRACKING MPPT tracking period BATT_CHG low 12 20 s TSAMPLE MPPT sampling time BATT_CHG high 0.3 0.5 s VMPP MPP pin voltage range MPPT enabled, MPPTRATIO = 50%, VMPP(MAX) = 150mV, DC-DC switching (see Section 6.4: MPPT setting)
0.075 VUVP
-0.1 V MPPACC MPP tracking accuracy Boost and buck-boost configurations 95 % LDO VLDO1,2 LDO1,2 adjusted output voltage LDO1_EN = 1 1.8 V LDO2_EN = 1 3.3 ΔVLDO1,2 LDO1 dropout VUVP + 200 mV < VSTORE ≤ 5.3 V; ILDO1 = 100 mA 0.5 LDO2 dropout 3.3 V < VUVP + 200 mV < VSTORE ≤ 5.3 V; ILDO2 = 100 mA 0.5 tLDO LDO1,2 START-up time BATT_CONN = low; CLDO1,2 = 100 nF - - 1 ms ILDO1,2(1) IOUT max from LDO1 BATT_CONN= low - - 200 mA IOUT max from LDO2 - - 200 mA VLDO1,2_EN_H LDO1,2 enable input HIGH 1 - - V VLDO1,2_EN_L LDO1,2 enable input LOW - - 0.5 V Digital output SPV1050
Symbol Parameter Test conditions Min. Typ. Max. Unit VBATT_CONN_L BATT_CONN voltage drop 1 mA sink current; BATT_CONN = low 40 70 150 mV VBATT_CHG_L BATT_CHG voltage drop 1 mA sink current; BATT_CHG = low 40 70 150 mV 1. Guaranteed by design, not tested in production. SPV1050
6 Functional description
The SPV1050 can be used as energy harvester or normal DC-DC converter, depending on the activation or deactivation of the embedded MPPT algorithm (by MPP_SET pin setting). Also, the IC offers both output stage over-voltage and under-voltage controls, fitting with the most typical requirements of battery charger applications. The additional unregulated (STORE) and regulated (LDO1, LDO2) voltage rails makes the IC suitable to be used as power manager. Independently by the activation/deactivation of the MPPT function, the DC-DC converter stage can be configured as boost or buck-boost by tying the CONF pin to the input source or to ground, respectively. See Figure 5. Boost configuration example and Figure 13. Buck-boost configuration example. If the embedded MPPT algorithm is enabled (MPP and MPP_SET pins connected to input source by a resistor partitioning), the device periodically stops the switching of the DC-DC converter to do a sampling of the input voltage and to store it on the capacitor connected at MPP_REF pin. When the sampling time elapses, the IC restarts operating: if VMPP > VMPP_REF, then the DC-DC can switch again, provided that other limitations are not active (for example, the switching is disabled if the over-voltage threshold has been triggered on EOC pin). The selection of the resistor partitioning at the input stage depends on the electrical characteristic of the harvested source and allows the IC to maximize the extracted power: see further details in Section 6.2: Boost configuration,Section 6.3: Buck-boost configuration and Figure 20. MPPT setup circuitry. The MPPT algorithm can be disabled by shorting the MPP_SET pin to the STORE pin. In this application case the MPP_REF pin is usually connected to a voltage reference. In case of low impedance source (e.g. USB), the MPP_REF is normally connected to GND: the IC tries switching at highest duty cycle. In case of high impedance source (limited current capability, i.e. the source isn't able to sustain the continuous switching at maximum duty cycle), the MPP_REF pin can be connected to a reference voltage (VEXT_REF) such that the IC stops switching when VMPP < VEXT_REF. This voltage reference can be set through a resistor ladder connected to STORE rail or to any other voltage reference available.
6.1 Battery voltage control
The IC integrates a pass transistor between the STORE and BATT pins to implement the battery under-voltage protection function. The pass transistor status (open or closed) depends on two voltage thresholds controlled by the pins UVP and EOC (normally connected to the STORE pin by a resistor partitioning): the respective voltages (VUVP and VEOC) are compared with the IC internal voltage reference (VBG = 1.23 V, typical value). Those protection thresholds guarantee the lifetime and the safety of the battery. SPV1050 Functional description DS10044 - Rev 8 page 10/30
Figure 3. Battery management section and the DC-DC stops switching. An internal hysteresis (EOCHYS) sets the restart voltage level for the DC-DC. connected at the input stage. on the STORE pin decreases down to the under-voltage threshold VSTORE(UVP) (corresponding to VUVP < VBG).
- 10 MΩ ≤ ROUT(TOT) ≤ 20 MΩ Equation 2:
- R6 = (VBG / VEOC) × ROUT(TOT) Equation 3:
- R5 = (VBG / VUVP) × ROUT(TOT) - R6 In addition, the IC provides two open drain digital outputs to an external microcontroller:
- BATT_CONN This pin is pulled down when the pass transistor is closed. It will be released once the pass transistor will be opened. If used, this pin must be pulled up to the STORE rail by resistor (10 MΩ, typically) .
- BATT_CHG This pin is pulled down when the DC-DC converter is switching, while it's released when it is not switching, i.e. it is high after STORE triggers VSTORE(EOC) and until it drops by EOCHYS , or when the UVLOL threshold is triggered, or during the sampling period (TSAMPLE ) of the MPPT algorithm. If used, this pin must be pulled-up to the STORE rail by a resistor (10 MΩ, typically). SPV1050 Functional description DS10044 - Rev 8 page 11/30
by BATT_CONN) between STORE and BATT pins. Figure 4. Implementations examples of larger UVP hysteresis
6.2 Boost configuration
Figure 5. Boost configuration example below shows an example of boost application circuit. Figure 5. Boost configuration example charge pump, while the DC-DC converter stage remains OFF. Figure 6. Boost start-up shows the behavior of input voltage VIN (voltage supplied by the source) and VSTORE at
Figure 12. Efficiency vs. input current; VOC = 2.5 V
6.3 Buck-boost configuration
Figure 13. Buck-boost configuration example shows an example of buck-boost application circuit. Figure 13. Buck-boost configuration example voltage VIN_HV and VSTORE at the start-up.
6.4 MPPT setting
open circuit voltage (VOC) and voltage at maximum power (VMP); the MPPTRATIO is intended as VMP/VOC. irradiation, temperature), but usually the effect on MPPTRATIO remains limited. Figure 20. MPPT setup circuitry
- Electrical characteristics of the harvesting source – VOC(MAX), intended as VOC at max operating condition of the source – MPPTRATIO , intended as VMP(TYP)/VOC(TYP) at typical operating conditions of the source
- Application constraints – ILEAKAGE, intended as the acceptable leakage through the resistors at the input stage – Usually, 0.1 μA ≤ ILEAKAGE ≤ 1 μA fits for most of the applications.
- SPV1050 constraints – VEN_TH (MAX) ≤ VMPP(MAX) ≤ (VUVP(MIN) - 100 mV) ⇒ 150 mV ≤ VMPP(MAX) ≤ 2.1 V – VMPP(MAX) < VOC(MAX) SPV1050 Functional description DS10044 - Rev 8 page 20/30
maximum light irradiation VOC(MAX) = 2.2 V. value (so, VMPP(MAX) = 2.1 V). Assume that for the application ILEAKAGE < 1 μ A is acceptable.
- VOC(MAX) = 2.2 V
- VMPP(MAX) = 2.1 V RIN(TOT) > (2.2 V / 1 uA) × 0.75 > 1.65 MΩ ==> RIN(TOT) = 10 MΩ Also, the MPPT accuracy can be strongly affected by an improper selection of the input capacitor. The input capacitance CIN = 4.7 μF generally covers the most typical use cases. The energy extracted from the source, and stored on CIN, is transferred to the load by the DC-DC converter through the inductor. The energy extracted by the inductor depends by the sink current: the higher input currents cause higher voltage drop on the input capacitance and this may result a problem for low voltage (< 1 V) and high energy (> 20 mA) sources. In such application cases the input capacitance has to be increased or, alternatively the L1 inductance has to be reduced. During the TSAMPLE time frame the input capacitor CIN is charged up to VOC by the source with a time constant (T1) resulting from the capacitance and the equivalent resistance REQ of the source. In case of PV source, being IMP the minimum operating current for MPPT, the REQ can be calculated as following: Equation 8:
- REQ = (VOC - VMP) / IMP = VOC × (1 - MPPRATIO) / IMP Thus CIN is calculated by the following formula: Equation 9:
- CIN ≤ T1 /REQ The following plots (Figure 21. Energy harvester equivalent circuit, Figure 22. Voltage vs. time at different C values and fixed current) show the effect of different CIN values on the time constant. If the capacitance is too high, the capacitor may not be charged within the TSAMPLE = 400 ms time window, thus affecting the MPPT accuracy.
Figure 21. Energy harvester equivalent circuit
Figure 22. Voltage vs. time at different C values and fixed current
6.5 Power manager
output pin and ground. A 100 nF for each LDO pin is suitable for the most typical use cases. Figure 23. LDO1 turn on with 100 mA load and Figure 24. LDO2 turn on with 100 mA load show the behavior of the LDOs when a 100 mA load is connected. Figure 23. LDO1 turn on with 100 mA load
Figure 24. LDO2 turn on with 100 mA load VSTORE = VBATT - (RBATT * ILOAD). is no longer supplied until next end of charge condition is reached.
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
7.1 Package and packing information
Figure 25. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package outline
Package information
DS10044 - Rev 8 page 24/30
Table 5. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package mechanical data
- “VFQFPN” stands for “Thermally Enhanced Very thin Fine pitch Quad Packages No lead”. Very thin: 0.80 < A ≤ 1.00 mm /
Figure 26. Recommended footprint of VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 DS10044 - Rev 8 page 25/30
Figure 27. Tape and reel design DS10044 - Rev 8 page 26/30
8 Ordering information
Order code Op. temp. range [oC] Package Packing SPV1050TTR -40 to 85 VFQFPN 3 x 3 x 1 20L Tape and reel SPV1050
Ordering information
DS10044 - Rev 8 page 27/30
Figure 28. Inductor current and input voltage waveforms
- VSTORE triggers the overvoltage threshold
- The inductor current (IL) triggers the internal threshold IL(PEAK) (= 140 mA, typ.)
- TON(MAX) = 10 μs elapses In the OFF phase the energy stored in the inductor will be released to the output stage: during TOFF the IL decreases to ILZC. According to the internal controls of the IC, TOFF(MIN) = 0.2 μs: in order to prevent IL goes negative, the application must be designed such that the energy stored in the inductor during TON is always greater than, or equal to, the energy released during TOFF. This goal can be achieved through the proper selection of R2 + R3. Thus, in order to guarantee IL(MIN) > 0, it must be: Equation 10:
- IL(MIN) = IH - (VSTORE - VIN)×(TOFF(MIN)/L) > 0 Equation 11:
- IL(MIN) = (VIN/L) × TON(MAX)- (VSTORE - VIN)×(TOFF(MIN)/L) > 0 leading Equation 12:
- VIN > VSTORE × (TOFF(MIN)/(TON(MAX) + TOFF(MIN)) = VSTORE / 51 As worst case for the above equation it can be considered VSTORE at the overvoltage level. The resistor R1, part of the partitioning at the input stage, can be used purposing the DC-DC switch-off before IL(MIN) ≤ 0. VMPP = VIN *(R2+R3)/(R1+R2+R3) < VEN_TH SPV1050 Application tips DS10044 - Rev 8 page 28/30
Revision history
Table 6. Document revision history 25-Nov-2013 1 Initial release. 18-Dec-2014 3 Document status corrected to reflect current phase of product development. input resistor partitioning. Deleted Appendix A. and package information: deleted any reference to die form. Corrected editing error in Equation 1. example values in Section 6.4.
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