SPT9712BIP

SPT9712 CADEKA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 7

Technical content

12-BIT, 100 MWPS ECL D/A CONVER TER TECHNICAL D ATA FEBR UARY 15, 2001 APPLICA TIONS

• Fast frequency hopping spread spectrum radios Direct sequence spread spectrum radios Microw ave and satellite modems Test & measurement instrumentation FEA TURES 12-Bit, 100 MWPS digital-to-analog converter ECL compatibility Low pow er: 600 mW 1/2 LSB DNL 40 MHz multiplying bandwidth Industrial temperature range Superior performance over AD9712 – Improved settling time of 13 ns – Improved glitch energy 15 pV-s – Master-slave latches GENERAL DESCRIPTION The SPT9712 is a 12-bit, 100 MWPS digital-to-analog converter designed for direct digital synthesis, high reso- lution imaging, and arbitrary waveform generation applica- tions. This device is pin-for-pin compatible with the AD9712 with significantly improved performance . The only difference between the SPT9712 and the AD9712 is that the Latch Enable (LE, pin 26) for the SPT9712 is rising-edge trig- gered (see figure 1), whereas the Latch Enable (LE, pin 26) for the AD9712 functions in the transparent mode. The SPT9712 is an ECL-compatible device. It features a fast settling time of 13 ns and low glitch impulse energy of 15 pV-s, which results in excellent spurious-free dynamic range characteristics. The SPT9712 is available in a 28-lead PLCC package in the industrial temperature range (–40 to +85 °C). BLOCK DIA GRAM /MT82/MT83/MT101/MT116 /MT67/MT111/MT110/MT116/MT114/MT111/MT108/MT32/MT65/MT109/MT112/MT32/MT73/MT110 /MT40/MT77/MT83/MT66/MT41 /MT76/MT97/MT116/MT99/MT104/MT32/MT69/MT110/MT97/MT98/MT108/MT101 /MT68/MT105/MT103/MT105/MT116/MT97/MT108 /MT73/MT110/MT112/MT117/MT116/MT115 /MT68/MT49 /MT116/MT104/MT114/MT111/MT117/MT103/MT104 /MT68/MT49/MT50 /MT82/MT101/MT102/MT32/MT73/MT110 /MT73/MT79/MT117/MT116 /MT73/MT79/MT117/MT116 /MT68/MT101/MT99/MT111/MT100/MT101/MT114/MT115 /MT97/MT110/MT100 /MT68/MT114/MT105/MT118/MT101/MT114/MT115 /MT76/MT97/MT116/MT99/MT104/MT101/MT115 /MT40/MT76/MT83/MT66/MT41 /MT150 /MT67/MT111/MT110/MT116/MT114/MT111/MT108 /MT65/MT109/MT112 /MT43 /MT67/MT111/MT110/MT116/MT114/MT111/MT108 /MT65/MT109/MT112/MT32/MT79/MT117/MT116 /MT73/MT110/MT116/MT101/MT114/MT110/MT97/MT108 /MT86/MT111/MT108/MT116/MT97/MT103/MT101 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101 /MT82/MT101/MT102/MT32/MT79/MT117/MT116 /MT83/MT119/MT105/MT116/MT99/MT104 /MT78/MT101/MT116/MT119/MT111/MT114/MT107

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Supply Voltages Input Voltages Digital Input Voltage EE Reference Input Voltage Range (V Output Currents Temperature ELECTRICAL SPECIFICATIONS TA = TMIN – TMAX , VEE = –5.2 V, RSet = 7.5 kΩ , Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified. TEST TEST SPT9712A SPT9712B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS DC Performance Resolution 12 12 Bits Differential Linearity I ±0.5 ±0.75 ±1.0 ±1.25 LSB Differential Linearity Max at Full Temp. VI ±1.5 ±2.0 LSB Integral Linearity Best Fit I ±0.75 ±1.0 ±1.0 ±1.5 LSB Integral Linearity Max at Full Temp. VI ±1.75 ±2.0 LSB Output Capacitance +25 °C V 10 10 pF Gain Error 1 +25 °C I 1.0 5.0 1.0 5.0 % FS Full Temp. VI 8.0 8.0 % FS Gain Error Tempco Full T emp. V 150 150 PPM/°C Zero-Scale Offset Error +25 °C I 0.5 2.5 0.5 2.5 µA Full Temp. VI 5.0 5.0 µA Offset Drift Coefficient Full T emp. V 0.01 0.01 µA/°C Output Compliance Voltage +25 °C IV –1.2 +2.0 –1.2 +2.0 V Dynamic Performance Conversion Rate +25 °C IV 100 100 MWPS Settling Time tST 2 +25 °C V 13 13 ns Output Propagation Delay tD 3 +25 °C V 1 1 ns Glitch Energy4 +25 °C V 15 15 pV-s Full Scale Output Current5 +25 °C V 20.48 20.48 mA Spurious-Free Dynamic Range6 +25 °C

1.23 MHz; 10 MWPS 2 MHz Span V 70 70 dBc

5.055 MHz; 20 MWPS 2 MHz Span V 68 68 dBc

10.1 MHz; 50 MWPS 2 MHz Span V 68 68 dBc

16 MHz; 40 MWPS 10 MHz Span V 68 68 dBc

L = 50 Ω V2 2 n s Power Supply Requirements Negative Supply Current (–5.2 V) +25 °C I 115 140 115 140 mA Full Temp VI 148 148 mA Nominal Power Dissipation V 600 600 mW Power Supply Rejection Ratio ±5% of VEE I 30 100 30 100 µA/V External Ref, +25 °C 1Gain is measured as a ratio of the full-scale current to ISet. The ratio is nominally 128. 2Measured as voltage at mid-scale transition to ±0.024%; RL=50 Ω . 3Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band. 4Glitch is measured as the largest single transient. 5Calculated using IFS = 128 x (Control Amp In / RSet) 6SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at the fundamental frequency and covers the indicated span.

All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. ELECTRICAL SPECIFICATIONS TA = TMIN – TMAX , VEE = –5.2 V, RSET = 7.5 kΩ , Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified. TEST TEST SPT9712A SPT9712B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Voltage Input and Control Reference Input Impedance +25 °C V 3 3 k Ω Ref. Multiplying Bandwidth +25 °C V 40 40 MHz Internal Reference Voltage Drift V 50 50 ppm/°C Amplifier Input Impedance +25 °C V 3 3 M Ω Amplifier Input Bandwidth +25 °C V 1 1 MHz Digital Inputs Logic 1 Current Full Temp. VI 20 20 µA Logic 0 Current Full Temp. VI 10 10 µA Input Capacitance +25 °C V 3 3 pF Input Setup Time – t S +25 °C IV 3 2 3 2 ns Input Setup Time – tS Full Temp. IV 3.5 3.5 ns Input Hold Time – tH +25 °C IV 0.5 0 0.5 0 ns Input Hold Time – tH Full Temp. IV 0.5 0.5 ns Latch Pulse Width – tPWL , tPWH +25 °C IV 5.0 4.0 5.0 4.0 ns

The SPT9712 uses a segmented architecture incorporat- ing most significant bit (MSB) decoding. The four MSBs (D1–D4) are decoded to thermometer code lines to drive 15 discrete current sinks. For the eight least significant bits (LSBs), D5 and D6 are binary weighted and D7–D12 are applied to the R-2R network. The 12-bit decoded data is input to internal master/slave latches. The latched data is input to the switching network and is presented on the output pins as complementary current outputs. TYPICAL INTERFACE CIRCUIT The SPT9712 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT9712 in normal circuit operation. The following sec- tions provide descriptions of the pin functions and outline critical performance criteria to consider for achieving opti- mal device performance. POWER SUPPLIES AND GROUNDING The SPT9712 requires the use of a single –5.2 V supply. All supplies should be treated as analog supply sources. This means the ground returns of the device should be connected to the analog ground plane. All supply pins should be bypassed with .01 µF and 10 µF decoupling capacitors as close to the device as possible. The two grounds available on the SPT9712 are DGND and AGND. These grounds are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of the SPT9712. All ground, reference and analog output pins should be tied directly to the DAC ground plane. The DAC and system ground planes should be separate from each other and only con- nected at a single point through a ferrite bead to reduce ground noise pickup. DIGITAL INPUTS AND TIMING The SPT9712 uses single-ended, 10K ECL-compatible inputs for data inputs D1–D12 and Latch Enable. It also employs master/slave latches to simplify digital interface timing requirements and reduce glitch energy by synchro- nizing the current switches. This is an improvement over the AD9712, which typically requires external latches for digital input synchronization. Referring to figure 1, data is latched into the DAC on the rising edge of the latch enable clock with the associated setup and hold times. The output transition occurs after a typical 1 ns propagation delay and settles to within ±1 LSB in typically 13 ns. Because of the SPT9712’s rising-edge triggering, no timing changes are required when replacing an AD9712 operating in the transparent mode. VOLTAGE REFERENCE When using the internal reference, Ref Out should be con- nected to Control Amp In and decoupled with a 0.1 µF capacitor. Control Amp Out should be connected to Ref In and decoupled to the analog supply. (See figure 2.) Full-scale output current is determined by Control Amp In and R Set using the following formula: IOut (FS) = (Control Amp In / RSet) x 128 (Current Out is a constant 128 factor of the reference current) The internal reference is typically –1.20 V with a tolerance of ±0.05 V and a typical drift of 50 ppm/°C. If greater accu- racy or temperature stability is required, an external refer- ence can be utilized. OUTPUTS The output of the SPT9712 is comprised of complemen- tary current sinks, I Out and IOut. The output current levels at either IOut or IOut are based upon the digital input code. The sum of the two is always equal to the full-scale output current minus one LSB. By terminating the output current through a resistive load to ground, an associated voltage develops. The effective resistive load (R Eff) is the output resistance of the device (ROut) in parallel with the resistive load (RL). The voltage which develops can be determined using the following formulas: Control Amp Out = –1.2 V, and R Set = 7.5 kΩ IOut (FS) = (–1.2 V / 7.5 kΩ ) x 128 = –20.48 mA R L = 51 Ω R Out = 1.0 kΩ R Eff = 51 Ω || 1.0 kΩ = 48.52 Ω VOut = REff x IOut (FS) = 48.52 Ω x –20.48 mA = –0.994 V The resistive load of the SPT9712 can be modified to in- corporate a wide variety of signal levels. However, optimal device performance is achieved when the outputs are equivalently loaded.

/MT65 /MT66 /MT80/MT105/MT110/MT32/MT49 /MT67 /MT68 /MT69 /MT70 /MT71 /MT72 /MT84/MT79/MT80 /MT86/MT73/MT69/MT87 /MT80/MT105/MT110/MT32/MT49 /MT66/MT79/MT84/MT84/MT79/MT77 /MT86/MT73/MT69/MT87 /MT73 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.452 0.456 11.48 11.58 B 0.485 0.495 12.32 12.57 C 30° 30° D 0.170 0.179 4.32 4.55 E 0.020 0.025 0.51 0.64 F 0.031 0.035 0.79 0.89 G 0.013 0.021 0.33 0.53 H 0.048 0.052 1.22 1.32 I 0.410 0.430 10.41 10.92

PART NUMBER DNL/INL TEMPERATURE RANGE PACKAGE SPT9712AIP ±0.75/±1.0 –40 to +85 °C 28L PLCC SPT9712BIP ±1.25/±1.5 –40 to +85 °C 28L PLCC PIN ASSIGNMENTS PIN FUNCTIONS Name Function Out+ Analog Current Output Out– Complementary Analog Current Output D1–D12 Digital Input Bits (D12 is the LSB) Latch Enable Latch Control Line Ref In Voltage Reference Input Ref Out Internal Voltage Reference Output Normally Connected to Control Amp In Ref GND Ground Return For Internal Voltage Reference and Amplifier Control Amp In Normally Connected to Ref Out If Not Connected to External Reference Control Amp OutOutput of Internal Control Amplifier Normally Connected to Ref In R Set1 Connection for External Resistance Reference When Using Internal Amplifier Nominally 7.5 kΩ Analog Return Analog Return Ground Analog VEE Analog Negative Supply (–5.2 V) Digital VEE Digital Negative Supply (–5.2 V) DGND Digital Ground Return N/C Not Connected 1Full-Scale Current Out = 128 (Control Amp In / RSet) /MT50/MT53 /MT50/MT52 /MT50/MT51 /MT50/MT50 /MT50/MT49 /MT50/MT48 /MT49/MT57 /MT53 /MT54 /MT55 /MT56 /MT57 /MT49/MT48 /MT49/MT49 /MT49/MT56 /MT49/MT55 /MT49/MT54 /MT49/MT53 /MT49/MT52 /MT49/MT51 /MT49/MT50 /MT50/MT54 /MT50/MT55 /MT50/MT56 /MT49 /MT50 /MT51 /MT52 /MT65/MT110/MT97/MT108/MT111/MT103/MT32/MT86/MT69/MT69 /MT82/MT83/MT101/MT116 /MT78/MT47/MT67 /MT82/MT101/MT102/MT32/MT71/MT78/MT68 /MT68/MT105/MT103/MT105/MT116/MT97/MT108/MT32/MT86/MT69/MT69 /MT82/MT101/MT102/MT32/MT79/MT117/MT116 /MT67/MT111/MT110/MT116/MT114/MT111/MT108/MT32/MT65/MT109/MT112/MT32/MT73/MT110 /MT68/MT54 /MT68/MT55 /MT68/MT56 /MT68/MT57 /MT68/MT49/MT48 /MT68/MT49/MT49 /MT40/MT76/MT83/MT66/MT41/MT32/MT68/MT49/MT50 /MT76/MT97/MT116/MT99/MT104/MT32/MT69/MT110/MT97/MT98/MT108/MT101 /MT68/MT71/MT78/MT68 /MT40/MT77/MT83/MT66/MT41/MT32/MT68/MT49 /MT68/MT50 /MT68/MT51 /MT68/MT52 /MT68/MT53 /MT67/MT111/MT110/MT116/MT114/MT111/MT108/MT32/MT65/MT109/MT112/MT32/MT79/MT117/MT116 /MT82/MT101/MT102/MT32/MT73/MT110/MT65/MT110/MT97/MT108/MT111/MT103/MT32/MT86 /MT69/MT69 /MT73/MT79/MT117/MT116 /MT65/MT110/MT97/MT108/MT111/MT103/MT32/MT82/MT101/MT116/MT117/MT114/MT110 /MT68/MT105/MT103/MT105/MT116/MT97/MT108/MT32/MT86/MT69/MT69 /MT73/MT79/MT117/MT116 /MT80/MT76/MT67/MT67