SPT9691SCP

SPT9691 CADEKA | Alldatasheet

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Technical content

WIDE INPUT VOL TAGE, JFET COMP ARA TO R

APPLICATIONS

• Automated Test Equipment
• High-Speed Instrumentation
• Window Comparators
• High-Speed Timing
• Line Receivers
• High-Speed Triggers
• Threshold Detection
• Peak Detection GENERAL DESCRIPTION The SPT9691 is a high-speed, wide common mode voltage, JFET input, dual comparator. It is designed for applications that measure critical timing parameters in which wide com- mon mode input voltages of -4.0 to +8.0 V are required. Propagation delays are constant for overdrives greater than 200 mV. JFET inputs reduce the input bias currents to the nanoamp level, eliminating the need for input drivers and buffers in BLOCK DIAGRAM

FEATURES

• Common Mode Range -4.0 to +8.0 V
• Low Input Bias Current <100 pA
• Propagation Delay 2.5 ns (max)
• Low Offset ±25 mV
• Low Feedthrough and Crosstalk
• Differential Latch Control most applications. The device has differential analog inputs and complementary logic outputs compatible with ECL sys- tems. Each comparator has a complementary latch enable control that can be driven by standard ECL logic. The SPT9691 is available in 20-lead PLCC, 20-lead plastic DIP and 20-contact LCC packages over the commercial temperature range. It is also available in die form. AV CC (B) +INB -INB Q B GND BGND A LEA DV EE (A) AV EE (A) AV CC (A) +INA -INA Q A A LEA Q A BQ LE B LE B DV (B)EE AV (B)EE B

T A = +25 °C, AVCC = +10 V, AVEE =-10.0 V, DVEE =-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified. TEST TEST PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC ELECTRICAL CHARACTERISTICS Input Offset Voltage VIN,CM=0 I -25 0.0 +25 mV TMIN < TA<TMAX IV -25 0.0 +25 mV Offset Voltage Tempco V 50 µV/°C Input Bias Current I ±0.1 ±10 nA Input Bias Current TMIN <TA<TMAX IV ±2.0 ±100 nA Input Offset Current V ±1.0 nA Input Offset Current TMIN <TA<TMAX V ±10 nA Positive Supply Current (Dual) AVcc=10 V I 25 33 mA Negative Supply Current (Dual) AV EE =-10.0 V I 15 20 mA Negative Supply Current (Dual) DV EE =-5.2 V I 55 70 mA Positive Supply Voltage, AVCC IV 9.75 10.0 10.25 V Negative Supply Voltage, AVEE IV -9.75 -10.0 -10.25 V Negative Supply Voltage, DVEE IV -4.95 -5.2 -5.45 V Input Common Mode Range I -4.0 +8.0 V Latch Enable Common Mode Range IV -2.0 0 V Differential Voltage Range I ±10 V Open Loop Gain V 60 dB Differential Input Resistance V 2 G Ω Input Capacitance LCC Package 1.0 pF PDIP 2.9 pF Power Supply Sensitivity V 60 dB Common Mode Rejection Ratio I 50 60 dB TMIN < TA<TMAX IV 45 55 dB ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25°C Supply Voltages (Measured to GND) Input Voltages Output Temperature Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Application of multiple maximum rating conditions at the same time may damage the device. 2 10/6/97

T A = +25 °C, AVCC = +10 V, AVEE =-10.0 V, DVEE =-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified. TEST TEST PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC ELECTRICAL CHARACTERISTICS Power Dissipation Dual I 700 895 mW Output High Level ECL 50 Ohms to -2V I -.98 -.70 V Output Low Level ECL 50 Ohms to -2V I -1.95 -1.65 V AC ELECTRICAL CHARACTERISTICS Propagation Delay TEMPCO V 2 ps/ °C Propagation Delay Skew (A vs B) V 100 ps Propagation Delay Dispersion2 150 mV Overdrive Min. V 200 ps Latch Set-up Time V 1.7 ns Latch to Output Delay 150 mV O.D. V 0.8 ns Latch Pulse Width V 2 ns Latch Hold Time V -1.9 ns Rise Time 20% to 80% V 0.4 ns Fall Time 20% to 80% V 0.4 ns Slew Rate V 3 V/ns NOTES: 1 Valid for both high-to-low and low-to-high transitions. 2 Dispersion is the change in propagation delay due to changes in slew rate, overdrive, and common mode level. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaranteed over specified temperature range. TEST LEVEL I II III IV V VI 3 10/6/97

The timing diagram for the comparator is shown in figure 1. If LE is high and LE low in the SPT9691, the comparator tracks the input difference voltage. When LE is driven low and LE high, the comparator outputs are latched into their existing logic states. SWITCHING TERMS (Refer to figure 1) tpdH INPUT TO OUTPUT HIGH DELAY - The propagation delay measured from the time the input signal crosses the reference voltage (± the input offset voltage) to the 50% point of an output LOW to HIGH transition. tpdL INPUT TO OUTPUT LOW DELAY - The propagation delay measured from the time the input signal crosses the reference voltage (± the input offset voltage) to the 50% point of an output HIGH to LOW transition. tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to 50% point of an output LOW to HIGH transition. tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output HIGH to LOW transition. tH MINIMUM HOLD TIME - The minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. tpL MINIMUM LATCH ENABLE PULSE WIDTH - The minimum time that the Latch Enable signal must be HIGH in order to acquire an input signal change. tS MINIMUM SET-UP TIME - The minimum time before the negative transition of the Latch Enable signal that an input signal change must be present in order to be acquired and held at the outputs. VOD VOLTAGE OVERDRIVE - The difference between the differential input and reference input voltages. The set-up and hold times are a measure of the time required for an input signal to propagate through the first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected and held; those occurring after tH will not be detected. Changes between tS and tH may not be detected. 50% 50% 50% tpL Differential Input Voltage Output Q Output Q tS tH tpdL tpdH tpLOL tpLOH Latch Enable Latch Enable +=300 mV, =150 mVVODVIN VOD VRef ± VOS The leading edge of the input signal (which consists of a 150 mV overdrive voltage) changes the comparator output after a time of tpdL or tpdH (Q or Q ). The input signal must be maintained for a time ts (set-up time) before the LE falling edge and LE rising edge and held for time tH after the falling edge for the comparator to accept data. After tH , the output ignores the input status until the latch is strobed again. A minimum latch pulse width of tpL is needed for strobe opera- tion, and the output transitions occur after a time of tpLOH or tpLOL . 4 10/6/97

TYPICAL PERFORMANCE CURVES 0 50 100 150 200 250 300 350 1.8 2.0 2.2 2.4 2.6 2.8 3.0 PR OP AG ATION DELA Y TIME VS OVERDRIVE (mV) PR OP AGATION DELA Y TIME (ns) O VERDRIVE (mV) 0 +25 +50 TEMPERA TURE (°C) PR OP AGATION DELA Y TIME (ns) 1.6 1.8 2.0 2.2 1.4 2.4 (V =150 mV)OD +75 +100 PR OPOGA TION DELA Y TIME VS TEMPERA TURE INPUT BIAS CURRENT VS COMMON MODE VO LTAGE (+25 °C) COMMON MODE VO LTAGE (V) INPUT BIAS CURRENT (nA) 0.1 1.0 0.001 0.01 100 -6.0 -2.0 +2.0 +6.0 INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VO LTAGE VS COMMON MODE VO LTAGE (T=+25 °C) COMMON MODE VO LTAGE (V) +10.0 -10.0 -1.50 -1.30 -1.10 RISE AND FALL OF OUTPUTS VS TIME CR OSSO VER TIME (ns) -1.90 OUTPUT RISE AND F ALL (V) -1.70 -.90 3.5 -20 0 204 06 0 HYSTERESIS (mV) ΔLATCH = (VLE - VLE) mV HYSTERESIS VS ΔLATCH VIN (CM) = 0.0 V 5 10/6/97

The SPT9691 is an ultrahigh-speed dual voltage compara- tor. It offers tight absolute characteristics. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. The output stage is adequate for driving terminated 50 ohm transmission lines. The SPT9691 has a complementary latch enable control for each comparator. Both should be driven by standard ECL logic levels. A common mode voltage range of -4 V to +8 V is achieved by a proprietary JFET input design which requires a separate negative power supply (AVEE ). The dual comparators have separate AVCC, AVEE, DV EE, and grounds for each comparator to achieve high crosstalk rejec- tion. Single channel operation can be accomplished by float- ing all pins (including the ground and supply pins) of the unused comparator. Power dissipation during single channel operation is 50% of the dissipation during dual channel operation. Figure 2 - Internal Function Diagram CLK BUF LE LE LATCH ECL OUT REF REF DV EE VCC GND PRE AMP +IN - IN AV EE Q Q 6 10/6/97

20-Lead Plastic Leaded Chip Carrier (PLCC) A B C H D E F G INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.300 7.62 B 0.014 0.026 0.36 0.66 C .100 typ 2.54 D .010 typ 0.25 E 1.20 typ 30.48 F 0.290 0.330 7.37 8.38 G 0.246 0.254 6.25 6.45 H 1.010 1.030 25.65 26.16 A B E Pin 1 G L M N H I J K O C D F TO P VIEW Pin 1 BO TTOM VIEW INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A .045 typ 1.14 B C 0.350 0.356 8.89 9.04 D 0.385 0.395 9.78 10.03 E 0.350 0.356 8.89 9.04 F 0.385 0.395 9.78 10.03 G 0.042 0.056 1.07 1.42 H 0.165 0.180 4.19 4.57 I 0.085 0.110 2.16 2.79 J 0.025 0.040 0.64 1.02 K 0.015 0.025 0.38 0.64 L 0.026 0.032 0.66 0.81 M 0.013 0.021 0.33 0.53 N 0.050 1.27 O 0.290 0.330 7.37 8.38 8 10/6/97

20-Contact Leadless Chip Carrier (LCC) INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A .040 typ 1.02 B .050 typ 1.27 C 0.045 0.055 1.14 1.40 D 0.345 0.360 8.76 9.14 E 0.054 0.066 1.37 1.68 F .020 typ 0.51 G 0.022 0.028 0.56 0.71 H 0.075 1.91 C D F A B Pin 1Bottom View G H E 9 10/6/97

LE A Inverted Latch Enable A LEA Latch Enable A AV CC (A) Positive Supply Voltage (+10 V) AV EE (A) Negative Supply Voltage (-10 V) DV EE (A) Negative Supply Voltage (-5.2 V) AV CC (B) Positive Supply Voltage (+10 V) AV EE (B) Negative Supply Voltage (-10 V) DV EE (B) Negative Supply Voltage (-5.2 V) -INA Inverting Input A +INA Noninverting Input A +INB Noninverting Input B -INB Inverting Input B LE B Inverted Latch Enabled B LEB Latch Enable B GND B Ground B Q B Inverted Output B Q B Output B 10 11 GND LE DV (B) AV (B) AV CC (B) LE +INB -INB Q B Q B BGND A LEA DV EE (A) AV EE (A) AV CC (A) LEA +INA -INA Q A Q A B B EE EE DIP/PDIP 10 11 TOP VIEW LCC/PLCC Q B Q A GND B Q A Q B LEB LEB DV EE (B) AV EE (B) AV CC (B) -INB +INB+INA-INA AVCC (A) 5LEA LEA DV EE (A) AV EE (A) 4GND A

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT9691SCC 0 to +70 °C 20C LCC SPT9691SCN 0 to +70 °C 20L Plastic DIP SPT9691SCP 0 to +70 °C 20L Plastic Leaded Chip Carrier (PLCC) SPT9691SCU +25 °C Die* *Please see the die specification for guaranteed electrical performance. PIN ASSIGNMENTS 10 10/6/97