SPT9687 CADEKA | Alldatasheet

Document overview

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Technical content

FEATURES

  • Propagation Delay <2.3 ns
  • Propagation Delay Skew <300 ps
  • Low Power: 185 mW
  • Low Offset ±3 mV
  • Low Feedthrough and Crosstalk
  • Differential Latch Control

APPLICATIONS

  • High-Speed Instrumentation, ATE
  • High-Speed Timing
  • Window Comparators
  • Line Receivers
  • A/D Conversion
  • Threshold Detection SPT9687 DUAL ULTRAF AST VOL TAGE COMP ARA TO R GENERAL DESCRIPTION The SPT9687 is a dual, very high-speed monolithic com- parator. It is pin compatible with, and has improved perfor- mance over Analog Device's AD9687. The SPT9687 is designed for use in Automatic Test Equipment (ATE), high- speed instrumentation, and other high-speed comparator applications. Improvements over other sources include reduced power consumption, reduced propagation delays, and higher input impedance. The SPT9687 is available in 16-lead SOIC, 16-lead plastic DIP, 20-lead PLCC and 20-contact LCC packages over the industrial temperature range. It is also available in die form. BLOCK DIAGRAM A - + B Q Output Inverting Input GND A Latch Enable Q Output VCC VEE Inverting Input Latch Enable Noninverting Input Latch Enable Latch Enable Noninverting Input Q Output GND B Q Output - + B

T A = +25 °C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified. TEST TEST SPT9687 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC ELECTRICAL CHARACTERISTICS Input Offset Voltage R S = 0 Ohms1 III -3 ±.5 +3 mV Input Offset Voltage R S = 0 Ohms1 TMIN <TA<TMAX IV -3.5 +3.5 mV Offset Voltage Tempco V 4 µV/°C Input Bias Current I 6 ±20 µA Input Bias Current T MIN <TA<TMAX IV 7 ±38 µA Input Offset Current I -1.0 +1.0 µA Input Offset Current T MIN <TA<TMAX IV -1.5 +1.5 µA Input Common Mode Range I -2.5 +2.5 V Latch Enable Common Mode Range IV -2.0 0 V Open Loop Gain V 4000 V/V Input Resistance V 60 k Ω Input Capacitance V 3 pF Input Capacitance (LCC Package) V 1 pF Power Supply Sensitivity V CC and VEE IV 50 100 dB Common Mode Rejection Ratio IV 50 85 dB Positive Supply Current I 7 11 mA Negative Supply Current I 27 37 mA Positive Supply Voltage IV 4.75 5.0 5.25 V Negative Supply Voltage IV -4.95 -5.2 -5.45 V Power Dissipation I OUTPUT = 0 mA I 185 250 mW OUTPUT LOGIC LEVELS (ECL 10 KH Compatible) Output High 50 Ohms to -2 V I -.98 -.81 V Output Low 50 Ohms to -2 V I -1.95 -1.63 V AC ELECTRICAL CHARACTERISTICS 2 Propagation Delay 10 mV OD III 2.0 2.3 ns Latch Set-up Time IV 0.6 1 ns ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Supply Voltages Input Voltages EE to 0.5 V Output Temperature Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.

T A = +25 °C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified. TEST TEST SPT9687 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS 2 Latch to Output Delay 50 mV OD IV 3 ns Latch Pulse Width V 2 ns Latch Hold Time IV 0.5 ns Rise Time 20% to 80% V 1.2 ns Fall Time 20% to 80% V 1.2 ns 1R S = Source impedance. 2100 mV input step. Figure 1 - Timing Diagram 50% VREF ± VOS 50% 50% t t tpL tS tH tpdL tpdH pLOL pLOH DIFFERENTIAL INPUT VOLTAGE OUTPUT Q OUTPUT Q LATCH ENABLE LATCH ENABLE VOD VIN+ = 100 mV (p-p), VOD = 50 mV The set-up and hold times are a measure of the time required for an input signal to propagate through the first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected and held; those occurring after tH will not be detected. Changes between ts and tH may not be detected. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed tests; therefore, T J = TC = TA. TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at T A = 25 °C. Parameter is guaranteed over specified temperature range. TEST LEVEL I II III IV V VI

SWITCHING TERMS (Refer to figure 1) tpdH INPUT TO OUTPUT HIGH DELAY - The propagation delay measured from the time the input signal crosses the reference voltage (± the input offset voltage) to the 50% point of an output LOW to HIGH transition. t pdL INPUT TO OUTPUT LOW DELAY - The propagation delay measured from the time the input signal crosses the reference voltage (± the input offset voltage) to the 50% point of an output HIGH to LOW transition. t pLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to 50% point of an output LOW to HIGH transition. V OD VOLTAGE OVERDRIVE - The difference between the differential input and the reference voltages. tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output HIGH to LOW transition. t H MINIMUM HOLD TIME - The minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. t pL MINIMUM LATCH ENABLE PULSE WIDTH - The minimum time that the Latch Enable signal must be HIGH in order to acquire an input signal change. t S MINIMUM SET-UP TIME - The minimum time before the negative transition of the Latch Enable signal that an input signal change must be present in order to be acquired and held at the outputs. TIMING INFORMATION The timing diagram for the comparator is shown in figure 1. The latch enable (LE) pulse is shown at the top. If LE is high and LE low in the SPT9687, the comparator tracks the input difference voltage. When LE is driven low and LE high, the comparator outputs are latched into their existing logic states. The leading edge of the input signal (which consists of a 50 mV overdrive voltage) changes the comparator output after a time of tpdL or tpdH (Q or Q ). The input signal must be maintained for a time ts (set-up time) before the LE falling edge and LE rising edge and held for time tH after the falling edge for the comparator to accept data. After tH , the output ignores the input status until the latch is strobed again. A minimum latch pulse width of t pL is needed for strobe operation, and the output transitions occur after a time of t pLOH or tpLOL . GENERAL INFORMATION The SPT9687 is an ultrahigh-speed dual voltage compara- tor. It offers tight absolute characteristics. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. The output stage is adequate for driving terminated 50 ohm transmission lines. The SPT9687 has a complementary latch enable control for each comparator. Both should be driven by standard ECL logic levels. The dual comparator shares the same V CC and VEE connec- tions but have separate grounds for each comparator to achieve high crosstalk rejection. Figure 2 - Internal Functional Diagram ECL OUT Q Q REF REF PRE AMP VIN CLK BUF LATCH VIN VEE GND 1 LE LE GND 2VCC TYPICAL INTERFACE CIRCUIT The typical interface circuit using the comparator is shown in figure 3. Although it needs few external components and is easy to apply, there are several conditions that should be met to achieve optimal performance. The very high operating speeds of the comparator require careful layout, decoupling of supplies, and proper design of trans- mission lines. Since the SPT9687 comparator is a very high frequency and high gain device, certain layout rules must be followed to avoid spurious oscillations. The comparator should be sol- dered to the board with component lead lengths kept as short as possible. A ground plane should be used, and the input impedance to the part should be kept as low as possible to decrease parasitic feedback. If the output board traces are longer than approximately one-half inch, microstripline tech- niques must be employed to prevent ringing on the output waveform. Also, the microstriplines must be terminated at the far end with the characteristic impedance of the line to prevent reflections. All supply voltage pins should be de- coupled with high frequency capacitors as close to the device as possible. All ground and N/C pins should be connected to the same ground plane to further improve noise immunity and shielding. If using the SPT9687 as a single comparator, the outputs of the inactive comparator can be grounded, left open or terminated with 50 Ohms to -2 V. All outputs on the active comparator, whether used or unused, should have identical terminations to minimize ground cur- rent switching transients. Note: To ensure proper power up of the device, the input should be kept below +1.5 V during power up.

A 0.300 7.62 B 0.014 0.026 0.36 0.66 C .100 typ 2.54 D .010 typ 0.25 E 1.150 1.950 29.21 49.53 F 0.290 0.330 7.37 8.38 G 0.246 0.254 6.25 6.45 H 0.740 0.760 18.80 19.30 A B C H D E F G 16-Lead Plastic DIP 20-Contact Leadless Chip Carrier (LCC) C D F A B Pin 1Bottom View G H E INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A .040 typ 1.02 B .050 typ 1.27 C 0.045 0.055 1.14 1.40 D 0.345 0.360 8.76 9.14 E 0.054 0.066 1.37 1.68 F .020 typ 0.51 G 0.022 0.028 0.56 0.71 H 0.075 1.91

20-Lead Plastic Leaded Chip Carrier (PLCC) A B E Pin 1 G L M N H I J K O C D F TOP VIEW Pin 1 BOTTOM VIEW INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A .045 typ 1.14 B C 0.350 0.356 8.89 9.04 D 0.385 0.395 9.78 10.03 E 0.350 0.356 8.89 9.04 F 0.385 0.395 9.78 10.03 G 0.042 0.056 1.07 1.42 H 0.165 0.180 4.19 4.57 I 0.085 0.110 2.16 2.79 J 0.025 0.040 0.64 1.02 K 0.015 0.025 0.38 0.64 L 0.026 0.032 0.66 0.81 M 0.013 0.021 0.33 0.53 N 0.050 1.27 O 0.290 0.330 7.37 8.38 16-Lead Small Outline Integrated Circuit (SOIC) INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.150 0.157 3.81 3.99 B 0.230 0.244 5.84 6.20 C 0.386 0.393 9.80 9.98 D .050 Typ 1.27 Typ E 0.0138 0.0192 0.35 0.49 F 0.004 0.0098 0.127 0.25 G 0.061 0.068 1.55 1.73 H 0.0075 0.0098 0.19 0.25 I 0.055 0.061 1.40 1.55 C G A B DE F H I

LE A Inverted Latch Enable A VEE Negative Supply Voltage -INA Inverting Input A +INA Non-Inverting Input A +INB Non-Inverting Input B -INB Inverting Input B VCC Positive Supply Voltage LEB Latch Enabled B LE B Inverted Latch Enable B GND B Ground B Q B Output B Q B Inverted Output B PIN ASSIGNMENTS Q A GND A LE A VEE -INA +INA Q B GND B LE B VCC -INB +INB QA BQ LE A LEB PDIP/SOIC Q A GND A LE A VEE -INA +INA Q B GND B N/C VCC -INB+INB 9 101 11 21 3 3 2 1 20 19 N/C N/C N/CQ A Q B BLELE A TOP VIEW LCC/PLCC LE B

ORDERING INFORMATION

PART NUMBER Temperature Range PACKAGE TYPE SPT9687SIN -25 to +85 °C 16L PDIP SPT9687SIP -25 to +85 °C 20L PLCC SPT9687SIC -25 to +85 °C 20C LCC SPT9687SIS -25 to +85 °C 16L SOIC SPT9687SCU +25 °C Die* *Please see the die specification for guaranteed electrical performance.