SPT9101SCU

SPT9101 CADEKA | Alldatasheet

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Technical content

125 MSPS SAMPLE-AND-HOLD AMPLIFIER

FEATURES

• Second Source of AD9101
• 350 MHz Sampling Bandwidth
• 125 MHz Sampling Rate
• Excellent Hold Mode Distortion -75 dB at 50 MSPS (23 MHz VIN) -62 dB at 100 MSPS (48 MHz VIN)
• 7 ns Acquisition Time to 0.1%
• <1 ps Aperture Jitter
• 66 dB Feedthrough Rejection at 50 MHz
• Low Spectral Noise Density

APPLICATIONS

• Test Instrumentation Equipment
• RF Demodulation Systems
• High Performance CCD Capture
• Digital Sampling Oscilloscopes
• Commercial and Military Radar
• High-Speed DAC Deglitching Amp + C H OL D Sampler + 3RR RT NCLK NCLK VIn VO UT BLOCK DIAGRAM GENERAL DESCRIPTION The SPT9101 is a high-speed track-and-hold amplifier de- signed for a wide range of use. The SPT9101 is capable of sampling at speeds up to 125 MSPS with resolutions ranging from 8 to 12 bits. Trim programmable internal hold and compensation capacitors provide for optimized input band- width and slew rate versus noise performance. The performance of this device makes it an excellent front end driver for a wide range of ADCs on the market today. Significant improvements in dynamic performance can be achieved by using this device ahead of virtually all ADCs that do not have an internal track-and-hold. The SPT9101 is offered in 20-lead SOIC and LCC packages over the industrial temperature range and in die form. Contact the factory for military and /833 package options.

Gain ΔVIN = 0.5 V +25 °C I 3.93 4.0 4.07 V/V Full Temp. VI 3.9 4.1 V/V Offset ΔVIN = 0 V +25 °CI ±3 ±10 mV Full Temp. VI ±30 mV Output Resistance +25 °C V 0.5 Ω Output Short Circuit Current Full Temp. V ±60 mA PSRR ΔVS = 0.5 V p-p +25 °CV I 3 7 4 3 d B Pedestal Sensitivity to Pos. Supply Full Temp. V 4 mV/V ΔVS = 0.5 V p-p Pedestal Sensitivity to Neg. Supply Full Temp. V 8 mV/V ΔVS = 0.5 V p-p Analog Input/Output Maximum Output Voltage Range6 Full Temp. VI ±2.4 ±2.7 V Input Bias Current +25 °CI ±15 ±30 µA Full Temp. VI ±35 µA Input Capacitance +25 °CV 2 p F Input Resistance Full Temp. VI 100 450 k Ω Clock Inputs Input Bias Current +25 °CV I 3 3 0 µA Input Low Voltage Full Temp. VI -1.8 -1.5 V Input High Voltage Full Temp. VI -1.0 -0.8 V Track Mode Dynamics Bandwidth (-3 dB) VOut = 1.0 V p-p Full Temp. IV 150 180 MHz Slew Rate 4 V Output Step Full Temp. IV 1100 1400 V/ µs Overdrive Recovery Time1 To 0.1% V 55 ns Integrated Output Noise BW = 5 to 200 MHz V 270 µV Input RMS Spectral Noise 10 MHz V 3.9 nV Hz ABSOLUTE MAXIMUM RATING (Beyond which damage may occur) 1 ELECTRICAL SPECIFICATIONS +VS=+5.0 V, -VS=-5.2 V, RLOAD =100 Ω , unless otherwise specified. TEST TEST SPT9101 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Note 1: Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical application. Output Currents Temperature Supply Voltages Input Voltages

+VS=+5.0 V, -VS=-5.2 V, RLOAD =100 Ω , unless otherwise specified. TEST TEST SPT9101 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Hold Mode Dynamics Worst Harmonic 23 MHz, 50 MSPS V -75 dB FS VOut = 2 V p-p +25 °C Worst Harmonic 48 MHz, 100 MSPS IV -62 -57 dB FS VOut = 2 V p-p +25 °C Worst Harmonic 48 MHz, 100 MSPS IV -53 dB FS VOut = 2 V p-p Full Temp. Worst Harmonic 48 MHz, 125 MSPS V -57 dB FS VOut = 2 V p-p +25 °C Sampling Bandwidth2 -3 dB, +25 ˚C V 350 MHz VIN = 0.5 V p-p Hold Noise3 (RMS) +25 °C V 150 x t H mV/s Droop Rate V IN=0.0 V, +25 °C V -40 mV/ µs Feedthrough Rejection (50 MHz) Full Temp. V -66 dB VOut = 2 V p-p Maximum Hold Time, VIN=0 V Full Temp. IV 100 200 ns Track-and-Hold Switching Aperture Delay +25 °C V -250 ps Aperture Jitter +25 °C V <1 ps rms Pedestal Offset, VIN=0 V +25 °CI ±10 ±25 mV Full Temp. VI ±35 mV Transient Amplitude V IN = 0 V, Full Temp. V 8 mV Settling Time to 4 mV Full Temp. V 4 ns Glitch Product4 +25 °C V 20 pV-s VIN = 0 V Hold-to-Track Switching Acquisition Time to 0.1% +25 °CV 7 n s

2 V Output Step

Acquisition Time to 0.01% +25 °CI V 1 1 1 4 n s 2 V Output Step Full Temp. IV 16 ns Power Supply5 +V S Voltage Full Temp, Track Mode VI 54 65 mA Full Temp, Clocked Mode VI 44 55 mA -VS Voltage Full Temp, Track Mode VI 54 65 mA Full Temp, Clocked Mode VI 44 55 mA Power Dissipation Full Temp, Track Mode VI 551 663 mW Full Temp, Clocked Mode VI 449 561 mW 1Time to recover within rated error band from 160% overdrive. 2Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier. 3Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (tH ) is 20 ns, the accumulated noise is typically 3 µV (150 mV/s x 20 ns). This value must be combined with the track mode noise to obtain total noise. 4Total energy of worst case track-to-hold or hold-to-track glitch. Typical thermal impedances:Θ JC (LCC) = +6 °C/W Θ JA (SOIC) = +85 °C/W in still air at +25 °C ambient. 5Clocked mode is specified with a 50% clock duty cycle. 6Analog input voltage should be limited ≤0.8 volts to maintain device in linear range.

TIMING SPECIFICATION DEFINITIONS ACQUISITION TIME This is the time it takes the SPT9101 to acquire the analog signal at the internal hold capacitor when it makes a transition from hold mode to track mode. (See figure 1.) The acquisition time is measured from the 50% input clock transition point to the point when the signal is within a specified error band at the internal hold capacitor (ahead of the output amplifier). It does not include the delay and settling time of the output amplifier. Because the signal is internally acquired and settled at the hold capacitor before the output voltage has settled, the sampler can be put in hold mode before the output has settled. TRACK-TO-HOLD SETTLING TIME The time required for the output to settle to within 4 mV of its final value. APERTURE DELAY The aperture delay time is the interval between the leading edge transition of the clock input and the instant when the input signal was equal to the held value. It is the difference in time between the digital hold switch delay and the analog signal propagation time. Because the analog propagation time is longer than the digital delay in the SPT9101, the aperture delay is a negative value. Acquisition Time Aperature Delay Track-to-Hold Settling Hold Track Hold CLK NCLK Output Input Observed at Hold Capacitor Observed at Amplifier Output TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/ max specifications are guaranteed. The Test Level column indicates the specific device test- ing actually performed during production and Quality Assurance inspection. Any blank sec- tion in the data column indicates that the speci- fication is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at T A=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at T A = 25 °C. Parameter is guaranteed over specified temperature range.

The RTN pin may be tied to an external voltage to generate an offset at the output. VOut must be kept to less than ±2.7 V typical output swing. VOut, with an external reference voltage at the RTN pin, is represented by the following formula: VOut = 4 VIN - 3 VRef where VRef = voltage at RTN pin and | VOut | ≤ 2.7 V The following options are generally not recommended due to the possibility of degraded noise performance of the device: the RTN pin can also be tied to an external resistor to reduce the gain but performance may degrade due to increased noise from the external resistor. Also RTN can be left open for unity gain mode, however, noise will increase. In all cases, V IN must be kept to -0.5 V≤ VIN ≤ +0.5 V for rated performance. SAMPLER FOR 12-BIT ADC APPLICATION The SPT9101 was specifically designed for applications where improved bandwidth performance is required. Figure 3 shows as simple block diagram of the SPT9101 as a sampler ahead of the SPT7922 12-bit, 30 MSPS ADC. Figure 3 - Sampler for 12-Bit ADC SPT9101 SPT7922VIN Clock 1 Clock 2 The graph below entitled Improved Dynamic Performance Using the SPT9101 shows the performance with and without the SPT9101. The SPT9101 significantly extends the dy- namic performance range of the converter. PERFORMANCE CHARACTERISTICS SPT9101 Hold Mode Distortion vs. Temperature -65 -60 -50 -25 0 25 50 75 10 0 Temperature (°C) dB Worst Harmonic Input Frequency = 50 MHz Clock Frequency = 100 MHz Hold = 4 ns Track = 6 ns SPT9101 Hold Mode Distortion vs Input Frequency -75 -70 -65 -60 -55 1 10 100 Input Frequency (MHz) dB Worst Harmonic Clock Frequency = 100 MHz Track = 6 ns Hold = 4 ns Improved Dynamic Performance Using the SPT9101 TDE (dB) 51 0 1 5 2 040 FIN (MHz) SPT7922 SPT9101 & SPT7922 (FS = 28 MSPS) Droop Rate vs Temperature - 2 002 04 06 08 0 Temperature (°C) mV/us -40 -80 -120

A .040 typ 1.02 B .050 typ 1.27 C 0.045 0.055 1.14 1.40 D 0.345 0.360 8.76 9.14 E 0.054 0.066 1.37 1.68 F .020 typ 0.51 G 0.022 0.028 0.56 0.71 H 0.075 1.91 C D F A B Pin 1Bottom View G H E 20-Lead SOIC INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.291 0.299 7.40 7.60 B 0.394 0.419 10.00 10.65 C 0.496 0.512 12.60 13.00 D 0.050 typ 1.27 typ E 0.014 0.019 0.35 0.49 F 0.004 0.012 0.10 0.30 G 0.093 0.104 2.35 2.65 H 0.009 0.013 0.23 0.32 C G A B DE F H I

N RT N N/CVOutN/C N/C CLK +V S GND GND +VS +VS +VS S -VS VIN GND NCLK -VS S 12019 2 3 111213 10 9 PIN ASSIGNMENTS SOIC PIN FUNCTIONS Name I/O Function RTN I Gain Set Resistor Return +VS I +5 V Power Supply GND I Ground CLK I True ECL T/H Clock NCLK I Complement ECL T/H Clock -VS I -5.2 V Power Supply N/C - No Connection VIN I Analog Signal Input VOUT O Analog Signal Output

ORDERING INFORMATION

PART NUMBER PACKAGE TYPE TEMPERATURE RANGE SPT9101SIS 20L SOIC -40 to +85 °C SPT9101SIC 20L LCC -40 to +85 °C SPT9101SCU Die* +25 °C *Please see die specification for guranteed electrical performance. N/C GND GND CLK RT N RT N +V S +V S +V S +V S -VS -VS VIn N/C GND NCLK -VS VOut N/C -VS LCC (Bottom View)