SPT8100

SPT8100 CADEKA | Alldatasheet

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16-BIT, 5 MSPS CMOS A/D CONVER TER TECHNICAL D ATA JANUAR Y 9, 2002 FEA TURES

• 16-bit, 5 MSPS CMOS analog-to-digital converter On-chip PGA: gain range from 0 to 19.5 dB in seven selectable settings: +19.5 dB DLE: ±0.5 LSB, ILE: ±1.25 LSB SFDR: 94 dB @ ƒIN = 900 kHz, –8.1 dBFS Internal sample-and-hold and voltage reference Pow er dissipation: 465 mW at 5 MSPS +5 V analog supply and +3.3 to +5.25 V digital output supply 44-lead LQFP plastic package APPLICA TIONS Data acquisition systems IR imaging Scanners and digital copiers High-end CCD cameras Medical imaging Wireless communications Lab and test equipment Automatic test equipment

DESCRIPTION

The SPT8100 is a high-performance , 16-bit analog-to- digital converter that operates at a sample rate of up to 5 MSPS . Excellent dynamic performance and high linear- ity is achieved by a digitally calibrated pipelined architec- ture fabricated in CMOS process technology. A low-noise programmab le gain amplifier (PGA) is also in- corporated on chip. The PGA is digitally programmab le in seven selected settings over a 0 to +19.5 dB range. The SPT8100 also features an on-chip internal sample-and- hold and internal reference for minimal external circuitry. It operates from a single +5 V supply. Total pow er dissipa- tion, including internal reference, is 465 mW. A separate digital output supply pin is provided for +3.3 V or 5 V logic output levels. The SPT8100 is available in a 44-lead LQFP package over the industrial temperature range of –40 °C to +85 °C. AGND Low-Noise PGA 16-bit, 5 MSPS ADC VREF GS2 – GS0 (Gain Set) VIN+ VIN– 16-bits D15 – D0 (Data Outputs) O VR (Over-Range) DV DD +5V OV DD +3/5 V BIASR (Ext Bias Resistor) CLK VCM OE (Output Enable) BIASC (Ext Bias Capacitor) RD Y (Ready) AV DD +5V OGNDDGND RS (Reset) VRT VRB BLOCK DIA GRAM

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Supply Voltages Input Voltages Output Temperature Note 1: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX , AVDD =DV DD =+5.0 V, OVDD = 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT =1.43 kΩ , unless otherwise specified. TEST TEST SPT8100 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 15.9 16 Bits DC Accuracy Integral Linearity Error (ILE) V ±1.25 LSB Differential Linearity Error (DLE) V ±0.5 LSB Gain Error 1 IV –7.5 +7.5 %FSR Offset Error2 IV –5+ 5 % F S R Analog Input (into PGA) Differential Input Voltage Range VIN+, VIN– V5 V PPD Input Capacitance IV 15 pF Input Resistance3 PGA Gain = 0 dB IV 5.5 k Ω Input Bandwidth4 PGA Gain = 0 dB V 12 MHz Input Common Mode Voltage Range V 1.15 2.40 3.65 V Programmable Gain Amp Composite Input-Referred ƒIN > 300 kHz Noise Floor PGA Gain = 0 dB V 1.4 LSB RMS PGA Gain = 2.9 dB V 1.5 LSB RMS PGA Gain = 5.8 dB V 1.6 LSB RMS PGA Gain = 11.8 dB V 2.0 LSB RMS PGA Gain = 14.8 dB V 2.3 LSB RMS PGA Gain = 17.5 dB V 2.6 LSB RMS PGA Gain = 19.5 dB V 2.8 LSB RMS PGA Range V 19.5 dB PGA Gain Steps PGA Gain Accuracy VI ±0.3 dB Conversion Characteristics Maximum Conversion Rate VI 5 MSPS Pipeline Delay (Latency)5 IV 5.5 Clocks Reset Pulse Time (RS ) IV 3 Clocks Reset Calibration Time FS = 5 MSPS V 150 ms References and External Bias VRT – VRB (Internal Ref) VI 2.375 2.5 2.625 V Bias Resistor Range (External) V 800 1430 2500 Ω VCM Output Voltage IV 2.275 2.40 2.525 V VCM Output Current IV 47 µA VRT V 3.45 3.65 3.85 V VRB V 0.95 1.15 1.35 V 1 Total gain error of PGA and ADC using internal references. 2 Total offset error of PGA and ADC relative to mid-scale. 3 See table I for input resistance as a function of PGA gain.

4 Input bandwidth is a frequency to which the fundamental energy drops by 3 dB

5 The input is sampled on the falling edge of the clock and is available on the

output after the rising edge of the clock, 5.5 clock cycles later.

TA=TMIN to TMAX , AVDD =DV DD =+5.0 V, OVDD = 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT =1.43 kΩ , unless otherwise specified. TEST TEST SPT8100 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Dynamic Performance1 Effective Number of Bits ADC Input = –1 dBFS2 ƒIN = 60 kHz IV 12.2 13.0 Bits ƒIN = 900 kHz V 12.7 Bits Signal-to-Noise Ratio (without Harmonics) ADC Input = –1 dBFS2 ƒIN = 75 kHz IV 78 81 dB ƒIN = 900 kHz V 80 dB Harmonic Distortion ADC Input = –0.5 dBFS ƒIN = 60 kHz IV –92 –84 dB ƒIN = 900 kHz V –82 dB Signal-to-Noise and Distortion (SINAD) ADC Input = –1 dBFS ƒ IN = 60 kHz IV 75 80 dB ƒIN = 900 kHz V 78 dB Spurious Free Dynamic Range3 ƒIN = 60 kHz ADC Input = –0.5 dB IV 85 94 dBc ƒIN = 900 kHz V 94 dBc ƒIN = 2 MHz R EXT = 1 kΩ @ 10 MSPS V 83 dBc ƒIN = 3 MHz R EXT = 1 kΩ @ 10 MSPS V 78 dBc Two-Tone Intermodulation 3rd Order Distortion ƒ1=400 kHz, ƒ2=410 kHz4 V –94 dB ƒ1=890 kHz, ƒ2=900 kHz5 V –89 dB Inputs GS0 –GS2 Logic 1 Voltage VI 2.4 V GS0 –GS2 Logic 0 Voltage VI 0.8 V CLK, RS Logic 1 Voltage VI 2.0 V CLK, RS Logic 0 Voltage VI 0.8 V Maximum Input Current Low VI –10 +10 µA Maximum Input Current High VI –10 +10 µA Input Capacitance V 5 pF Digital Outputs Logic 1 Voltage I OH = –2 mA VI OV DD – 0.5 V Logic 0 Voltage I OL = 2 mA VI 0.4 V CLK to Output Delay Time (tD )C LOAD = 20 pF IV 30 ns Power Supply Requirements Voltages OV DD IV 3.0 3.3 5.25 V AV DD IV 4.75 5.0 5.25 V DV DD IV 4.75 5.0 5.25 V Currents I DD VI 93 103 mA Power Dissipation VI 465 515 mW 1 Dynamic performance tested at ƒS=4.4 MSPS 2 0 dBFS is 5.0 V peak-to-peak differential 3 ADC Input = –8.1 dBFS, unless otherwise noted 4 Test Conditions: PGA setting of 5.8 dB; Analog Input at ADC = –0.7 dB 5 Test Conditions: PGA setting of 0 dB; Analog Input at ADC = –1.9 dB TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifi- cations are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at T A = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteriza- tion data. V Parameter is a typical value for information purposes only. VI 100% production tested at T A = +25 °C. Parameter is guaranteed over specified temperature range.

The SPT8100 combines a high-resolution 5 MSPS 16-bit ADC, a built-in reference, and a programmable gain amp- lifier (PGA) with resistive input impedance in a 44-pin package. The device includes a digitally calibrated pipeline ADC, which is calibrated on assertion of a simple reset signal. The combination of low noise, high linearity, a high-input impedance buffer (with programmable gain), wideband S/H, on-board voltage references, and simple digital inter- face (16-bit parallel output word synchronous with the master sampling clock) makes the SPT8100 extremely easy to use in a wide variety of systems. For optimum performance, the analog inputs should be driven differentially, and may be AC-coupled or DC- coupled to a source. Typical applications include high-per- formance data acquisition systems, automatic test equip- ment, and wideband digital communications receivers such as wireless basestations. OPERATIONAL DESCRIPTION The following sections describe in greater detail individual blocks and functions of the SPT8100. The incoming analog differential signal (maximum level 5 V peak-to-peak differential) enters the device at the pins V IN+/VIN–. The analog signal path is partitioned into a pro- grammable gain amplifier (PGA) and an ADC. The PGA has maximum gain of +19.5 dB; the gain is set by the digi- tal control signals GS0 to GS2. The output of the PGA is fed directly to the ADC, which samples at a rate equal to the CLK frequency and outputs a 16-bit wide parallel word. The ADC uses a pipeline multi- stage architecture. Latency is 5.5 clock cycles. ADC CLOCK The chip requires a single low-jitter clock to be applied at the CLK pin, with nominal 40–60% duty cycle. All clock generation is performed internally and all converter and S/H clocks in the ADC path are directly derived from CLK. If the sample rate is changed by more than a factor of 2, the device must be recalibrated using the RS (reset) pin. DEVICE STARTUP/INITIALIZATION SEQUENCE Note: This initialization sequence is required. Without it, the device will not work. Allow sufficient time for the analog blocks on the SPT8100 to power on and come up to their quiescent DC states. Allowance may also be needed for thermal time constants associated with the package/board. On powerup, the SPT8100’s RS (reset) should be held low for at least three clock cycles. The power supply voltages applied to the device must be stable during this time. The clock signal (CLK) must be running for at least three clock cycles prior to the rising edge of RS , and must continue running. When the RS signal goes from low to high, calibration is ini- tiated. RDY is driven low two clock cycles after the rising edge of RS , and will stay low for 150 ms with a 5 MHz clock. When the initialization is complete, RDY returns high and the device is ready for normal operation. Note that the cali- bration of the ADC can be interrupted (before completion) by changing the RS signal from high to low, which will cause another reset to occur. When RS goes from low back to high, another calibration cycle will begin. RDY cannot be tri-stated: it is always driven either high or low. The CLK must be constantly running throughout the Figure 1 – Device Initialization Timing Requires external reset on powerup /MT51/MT32/MT99/MT108/MT111/MT99/MT107/MT32/MT99/MT121/MT99/MT108/MT101/MT115/MT32/MT109/MT105/MT110 /MT73/MT110/MT105/MT116/MT105/MT97/MT108/MT105/MT122/MT97/MT116/MT105/MT111/MT110/MT32/MT112/MT101/MT114/MT105/MT111/MT100/MT58/MT32/MT49/MT53/MT48/MT32/MT109/MT115/MT32/MT119/MT105/MT116/MT104/MT32/MT53/MT32/MT77/MT72/MT122/MT32/MT99/MT108/MT111/MT99/MT107 N N+1 N+2 INVALID DATA /MT78/MT43/MT53 /MT78/MT43/MT54 /MT78/MT43/MT55 /MT50/MT52/MT32/MT110/MT115/MT32/MT116/MT121/MT112 /MT78/MT43/MT56 PWR ON AIN CLK RS RDY D OUT /MT78/MT43/MT52 /MT50/MT32/MT99/MT108/MT111/MT99/MT107/MT32/MT99/MT121/MT99/MT108/MT101/MT115 /MT53/MT32/MT110/MT115/MT32/MT116/MT121/MT112

initialization phase until RDY is deasserted. Note that, although typically the device is initialized when power is first applied, the initialization is only started when the RS is asserted; there is no “power-on-reset” circuitry on chip. RS may be held low for an indefinite period of time. While RS is low, RDY will remain high. After RS is returned to high, RDY will go low for the duration of the calibration. PROGRAMMABLE GAIN AMPLIFIER The programmable gain amplifier (PGA) precedes the ADC inputs. The differential inputs, which are resistive, are at pins V IN+ and VIN–.The maximum input range is 5 V peak-to-peak differential (2.5 V single-ended). To achieve maximum overall system noise performance, the source driving these inputs needs to be as low-noise and as low- jitter as possible, while maintaining the required distortion performance. In addition, the driving source must be low impedance to maintain the accuracy of the PGA gain. The internal 0 dB analog signal level and ADC full-scale output level is 5 V peak-to-peak differential (2.5 V single- ended). The PGA may be used to provide gain for an input less than 5 V peak-to-peak differential. The gain of the PGA can be programmed using a three-bit control, available at pins GS0 to GS2. See table I. Note that the input resistance is a function of the gain setting. Table I – PGA Gain Control PGA Input V/V 3 dB GS2 GS1 GS0 Gain Resistance Gain BW LSB RMS (dB) (k ΩΩΩΩΩ ) 0 0 0 0 5.57 1 12 1.4 0 0 1 2.9 4.65 1.40 10 1.5 0 1 0 5.8 3.97 1.95 8 1.6 0 1 1 11.8 2.23 3.9 7 2.0 1 0 0 14.8 1.66 5.5 6 2.3 1 1 0 19.5 1.00 9.5 5 2.8 1 1 1 X Forbidden TYPICAL INTERFACE CIRCUIT ANALOG INPUT DRIVER The differential analog inputs (VIN+, VIN–) have a resistive input impedance of 1 kΩ minimum. For best performance, the input source should be a differential input, as shown in figure 2, typical interface circuit. The SPT8100 provides its own common-mode voltage on the pin marked V CM . Out- put drive capability of VCM is a maximum of 47 µA (50 kΩ to ground). The SPT8100 application note (AN8100) shows an ex- ample of two modes of driving the SPT8100. One mode is through a transformer and the other is through a single-to- differential converter. In all cases, both inputs V IN+ and VIN– must be kept within the input common-mode range BIAS C CONNECTION An external capacitor, CEXT on the BIASC pin, is used only for noise filtering of an internal voltage associated with the references. Its value is not critical: 1 µF in parallel with 0.01 µF is recommended. BIAS R CONNECTION As shown in the typical interface circuit, REXT is needed to connect between BIASR to ground. This resistor ranges from 800 Ω to 2.5 kΩ . The proper selection of REXT is a function of the sample rate and input frequency. Nominally, at 5 MSPS, R EXT =1.43 kΩ is recommended. If linearity for large signal levels at an analog bandwidth of 2 MHz is criti- cal, the value should be decreased to R EXT =1.24 kΩ ; and for even higher-frequency analog inputs, REXT =1.0 kΩ can be used. At lower sample rates (for example 2 MSPS), and lower analog input frequencies, the value may be in- creased to R EXT =2 kΩ . (Refer to the typical interface circuit table in figure 2b.) POWER SUPPLIES AND GROUNDING The SPT8100 requires three power supplies: analog AVDD , digital DVDD and output supply OVDD . This device works best if all three supplies are coming from the analog supply side of the system as shown in the typical interface circuit (figure 2a). Note, in figure 2a, that the supplies to the logic interface circuit and the OV DD are separate from each other. In a case where the +A3.3/5 V supply is not available, try to implement the design as close as possible to that shown in figure 2b. Place the ferrite bead (FB1) as close to the device as possible. To avoid latch-up, the delta between all three grounds must stay with 100 mV; this includes transients. (Refer to the absolute maximum ratings specifications.)

Figure 5 – Timing Diagram 2 CLK Digital Outputs OE tD1 tD2 tD3 Table II – Timing Parameters Parameter Symbol Min Typ Max Units CLK high to Data Valid tD1 18 24 40 1 ns OE inactive to HiZ t D2 10 16 30 ns OE active to Data Valid tD3 10 16 30 ns 1 Conditions: load capacitance = 20 pF , VOH = 3.3 V FFT Plot Typical Differential Linearity Error (DLE) Test Conditions: ƒIN = 2 MHz ƒCLK = 4.4 MHz PGA Gain = 18 dB R EXT = 1.08 kΩ ADC Input (Post PGA) = –5.4 dBFS TA = +25 °C Test Conditions: ƒIN = 75 kHz ƒCLK = 4.4 MHz PGA Gain = 0 dB Near Full-Scale Input Two-Tone Intermodulation FFT Spurious-Free Dynamic Range 100 5 V P-P

0.9 MHz, low

0.9 MHz, high

0.9 MHz, med

2 MHz, high

2 MHz, med

2 MHz, low

3 MHz, high

3 MHz, med

3 MHz, low

SFDR (dBc) Composite Level at ADC Input (dBFS) Test Conditions: ƒ1 = 890 kHz ƒ2 = 900 kHz ƒCLK = 4.4 MHz PGA Gain = 6 dB R EXT = 1.43 kΩ ADC Input (Post PGA) = –8.0 dBFS TA = +25 °C Test Conditions:

10 MSPS, 5 V, 25 °C

Low: REXT =1.43 kΩ @96 mA Med: REXT =1.24 kΩ @109 mA High: REXT =1 kΩ @129 mA DLE (LSB)

/MT73/MT110/MT100/MT101/MT120 /MT65 /MT66 /MT67/MT68 /MT80/MT105/MT110/MT32/MT49 /MT69 /MT70 /MT71 /MT72 /MT73 /MT74 /MT75 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.465 0.480 11.80 12.20 B 0.390 0.398 9.90 10.10 C 0.390 0.398 9.90 10.10 D 0.465 0.480 11.80 12.20 E 0.0315 BSC 0.80 BSC F 0.012 0.018 0.30 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.018 0.030 0.45 0.75 J 0.039 typ 1.0 typ K0 –7° 0–7°

PIN ASSIGNMENTS PIN FUNCTIONS Pin Name Description AGND Analog ground DGND Digital ground DV DD Digital +5.0 V supply OGND Ground for digital I/O OV DD Digital outputs supply (+3.3/5 V) CLK Master reference clock OE Output enable (active high) D0 –D 15 Data output bits; D0 is LSB; D15 is MSB O VR O verrange indicator bit (active high) N/C No connect GS[2:0] 3-bit PGA gain setting control inputs AV DD Analog +5.0 V supply RS Resets internal state of chip (active low) RD Y Initialization in progress indicator; RDY goes low during reset initialization. Chip is ready for normal operation when RDY is high. BIASC External bias capacitor connection BIASR External bias resistor connection VRT , VRB ADC reference voltage outputs VCM Common mode reference voltage output VIN+, VIN– Analog inputs to the PGA /MT49/MT50 /MT49/MT51 /MT49/MT52 /MT49/MT53 /MT49/MT54 /MT49/MT55 /MT49/MT56 /MT49/MT57 /MT50/MT48 /MT50/MT49 /MT50/MT50 /MT52/MT52 /MT52/MT51 /MT52/MT50 /MT52/MT49 /MT52/MT48 /MT51/MT57 /MT51/MT56 /MT51/MT55 /MT51/MT54 /MT51/MT53 /MT51/MT52 /MT49 /MT50 /MT51 /MT52 /MT53 /MT54 /MT55 /MT56 /MT57 /MT49/MT48 /MT49/MT49 /MT51/MT51 /MT51/MT50 /MT51/MT49 /MT51/MT48 /MT50/MT57 /MT50/MT56 /MT50/MT55 /MT50/MT54 /MT50/MT53 /MT50/MT52 /MT50/MT51 /MT65/MT71/MT78/MT68 /MT68/MT71/MT78/MT68 /MT68/MT86/MT68/MT68 /MT68/MT86/MT68/MT68 /MT79/MT71/MT78/MT68 /MT79/MT86/MT68/MT68 /MT67/MT76/MT75 /MT79/MT69 /MT68/MT48/MT32/MT40/MT76/MT83/MT66/MT41 /MT68/MT49 /MT68/MT50 /MT68/MT51 /MT68/MT52 /MT68/MT53 /MT68/MT54 /MT68/MT55 /MT68/MT56 /MT68/MT57 /MT68/MT49/MT48 /MT68/MT49/MT49 /MT68/MT49/MT50 /MT68/MT49/MT51 /MT82/MT68/MT89 /MT78/MT47/MT67 /MT78/MT47/MT67 /MT65/MT71/MT78/MT68 /MT65/MT86/MT68/MT68 /MT71/MT83/MT50 /MT78/MT47/MT67 /MT79/MT86/MT82 /MT68/MT49/MT53/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT49/MT52 /MT65/MT86/MT68/MT68 /MT71/MT83/MT48 /MT86/MT73/MT78/MT150 /MT86/MT73/MT78/MT43 /MT71/MT83/MT49 /MT86/MT67/MT77 /MT65/MT71/MT78/MT68 /MT86/MT82/MT84 /MT86/MT82/MT66 /MT66/MT73/MT65/MT83/MT82 /MT66/MT73/MT65/MT83/MT67 /MT82/MT83 ORDERING INFORMA TION PA R T NUMBER TEMPERA TURE RANGE PACKA GE SPT8100SIT –40 to +85 °C 44L LQFP