SPT8000

SPT8000 FAIRCHILD | Alldatasheet

Document overview

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• PDF pages: 11

Technical content

14-BIT, 20 MSPS, CMOS A/D CONVERTER PRELIMINARY INFORMATION OCTOBER 12, 2001

FEATURES

• 14-bit, 20 MSPS CMOS analog-to-digital converter  Excellent performance: DLE: ±0.5 LSB, ILE: ±1.2 LSB

12.1 Effective Number of Bits @ ƒ

IN = 5 MHz SFDR = 87 dB @ ƒIN = 5 MHz  Internal sample-and-hold and voltage reference  Power dissipation: 725 mW at 20 MSPS  +5 V analog supply and +3.3/5 V digital output supply  Out-of-range indicator  44-lead TQFP plastic package  –40 °C to +85 °C temperature range

APPLICATIONS

 Wireless communications  IR imaging  Scanners and digital copiers  High-end CCD cameras  Medical imaging  Automatic test equipment  Data acquisition systems  Lab and test equipment strumentation applications, as well as communications applications. The device operates from a single +5 V supply. A separate digital output supply pin is provided for +3/5 V logic output levels. Total power dissipation, including internal refer- ence, is 725 mW. It is in a 44-lead TQFP package over the industrial temperature range of –40 °C to +85 °C. /MT65/MT86/MT68/MT68 /MT65/MT71/MT78/MT68/MT66/MT71/MT78/MT68 /MT79/MT86/MT68/MT68 /MT79/MT71/MT78/MT68 /MT83/MT72/MT65 /MT65/MT68/MT67/MT49 /MT65/MT68/MT67/MT50 /MT65/MT68/MT67/MT51 /MT65/MT68/MT67/MT53 /MT66/MT105/MT97/MT115 /MT71/MT101/MT110/MT101/MT114/MT97/MT116/MT111/MT114/MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101 /MT38 /MT66/MT117/MT102/MT102/MT101/MT114/MT115 /MT86/MT73/MT78/MT43 /MT86/MT73/MT78/MT150 /MT67/MT76/MT75 /MT86/MT82/MT69/MT70/MT47/MT69/MT88/MT84/MT66 /MT86/MT82/MT84 /MT86/MT82/MT67 /MT86/MT66/MT83 /MT68/MT97/MT116/MT97/MT32/MT65/MT108/MT105/MT103/MT110/MT109/MT101/MT110/MT116/MT32/MT38/MT32/MT82/MT101/MT103/MT105/MT115/MT116/MT101/MT114/MT115 /MT69/MT114/MT114/MT111/MT114/MT32/MT67/MT111/MT114/MT114/MT101/MT99/MT116/MT105/MT111/MT110/MT32/MT38/MT32/MT67/MT97/MT108/MT105/MT98/MT114/MT97/MT116/MT105/MT111/MT110 /MT79/MT84/MT82 /MT68/MT49/MT51/MT150/MT68/MT48/MT32/MT40/MT68/MT48/MT61/MT76/MT83/MT66/MT41 /MT82/MT69/MT83/MT69/MT84/MT66 /MT66/MT85/MT83/MT89 /MT49/MT52 /MT65/MT68/MT67/MT52 /MT77/MT68/MT65/MT67/MT49/MT77/MT68/MT65/MT67/MT50 /MT77/MT68/MT65/MT67/MT51/MT77/MT68/MT65/MT67/MT52 /MT67/MT65/MT76 /MT66/MT97/MT110/MT100/MT103/MT97/MT112 /MT67/MT77

DESCRIPTION

This high-performance, 14-bit analog-to-digital converter operates at a sample rate of up to 20 MSPS. It utilizes a digitally calibrated, pipelined CMOS architecture to achieve excellent dynamic performance and linearity. Incorporated on chip are a high-performance sample-and- hold amplifier and internal reference for minimal external circuitry. The excellent linearity and superb dynamic performance of this device make it ideal for image processing and in- BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=25 °C, AVDD =+5.0 V, OVDD =3.3 V, ƒS=20 MSPS, Internal References, unless otherwise specified. TEST TEST SPT8000 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 14 Bits DC Performance Differential Linearity Error (DLE) V ±0.5 LSB Integral Linearity Error (ILE) V ±1.2 LSB No Missing Codes V Guaranteed Offset (Mid Scale) Error V ±1.0 LSB Gain Error External V RT & VRC V ±0.05 % FS Offset Error Temperature Drift1 –40 to +85 °C V ±2.4 ppm FS/ °C Gain Error Temperature Drift External V RT & VRC V ±3.5 ppm FS/ °C –40 to +85 °C Analog Input Input Voltage Span2: VIN+, VIN– Common Mode=+2.25 V V ±1 V Input Capacitance V 10 pF Input Full-Power Bandwidth V 82 MHz Timing Characteristics Conversion Rate V 20 25 MSPS Pipeline Delay (Latency) V 16.5 Clock Cycles Clock Duty Cycle V 40 50 60 % Clock Period (t CLK )V 5 0 n s Output Delay (tOD )C L=3.5 pF V 8 ns Dynamic Performance Effective Number of Bits (ENOBs) ƒIN = 5 MHz V 12.1 Bits Signal-to-Noise and Distortion (SINAD)ƒIN = 5 MHz V 74.5 dB Signal-to-Noise Ratio (SNR) ƒIN = 5 MHz V 75 dB Total Harmonic Distortion (THD) ƒIN = 5 MHz V –84 dB Spurious Free Dynamic Range (SFDR)ƒIN = 5 MHz V 87 dB Digital Inputs (CAL, RESETB) Logic 1 Voltage V 2.4 V Logic 0 Voltage V 0.8 V Logic 1 Input Current V –10 +10 µA Logic 0 Input Current V –10 +10 µA Input Capacitance V 5 pF 1 After one-time calibration at 25 °C. Supply Voltages Input Voltages Digital Outputs Temperature

TA=25 °C, AVDD =+5.0 V, OVDD =3.3 V, ƒS=20 MSPS, Internal References, unless otherwise specified. TEST TEST SPT8000 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Clock Input (CLK) Logic 1 Voltage TBD V Logic 0 Voltage TBD V Logic 1 Input Current V –10 +10 µA Logic 0 Input Current V –10 +10 µA Input Capacitance V 5 pF Digital Outputs (D0–D13, OTR, BUSY) Logic 1 Voltage I OH =4.5 mA, OVDD =5 V V 90% OV DD V IOH =2.5 mA, OVDD =3.3 V V 90% OV DD V Logic 0 Voltage I OL =–4.5 mA, OVDD =5 V V 10% OV DD V IOL =–2.5 mA, OVDD =3.3 V V 10% OV DD V Voltage Reference Output Voltage (VREF ) V 1.0 V Reference Temperature Coefficient V 100 ppm/ °C Top Reference Voltage (VRT ) V 3.25 V Bottom Reference Voltage (VRC ) V 1.25 V Common Mode Voltage (CM) V 2.25 V Power Supply Requirements AV DD Supply Voltage V 4.75 5.0 5.25 V OV DD Supply Voltage V 3.3 5.25 V AV DD Supply Current Full Scale 5 MHz Input V 145 mA OV DD Supply Current Full Scale 5 MHz Input V 0.07 mA Power Dissipation Full Scale 5 MHz Input V 725 mW TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range.

DIFFERENTIAL LINEARITY ERROR (DLE) OR DIFFERENTIAL NONLINEARITY (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differ- ential Linearity Error is the maximum deviation, expressed in LSBs, from this ideal value. INTEGRAL LINEARITY ERROR (ILE) OR INTEGRAL NONLINEARITY (INL) The ideal transfer for an ADC is a straight line drawn between “zero” and “full scale.” The point used as “zero” occurs 0.5 LSB before the first code transition. “Full scale” is defined as a level 1.5 LSB beyond the last code transi- tion. ILE is the worst-case deviation of a code from the straight line. The deviation of each code is measured from the middle of that code. MISSING CODE A code with zero width is missing. A code that is missing will have a DLE of –1. For example, as the input voltage is increasing, the output will jump between the adjacent specification that guarantees no missing codes requires that every code combination appear in a monotonically in- creasing sequence as the analog input is increased. OFFSET ERROR, BIPOLAR In the differential mode, the major carry transition LSB below mid scale (0 V differential input). The Offset Error specifies the deviation of the actual transition from that point. GAIN ERROR The last transition should occur at an analog value 1.5 LSB below the nominal full scale. The first transition is 0.5 LSB above the low end of the scale (–FS in bipolar converters). The gain error is the deviation of the actual difference be- tween the first and last code transitions from the ideal dif- ference between the first and last transitions. INPUT FULL-POWER BANDWIDTH The frequency at which the amplitude of the recon- structed fundamental signal is reduced by 3 dB for a full- scale input. CLOCK DUTY CYCLE Ratio of clock pulse high (t CH ) to total clock period (tCLK ) times 100%. SPECIFICATION DEFINITIONS Duty Cycle =tCH tCLK X 100% N = SINAD – 1.76 6.02 SIGNAL-TO-NOISE RATIO (SNR) The ratio of the power of the desired signal (fundamental) to the sum of the power of noise signals at a given point in time. The first 9 harmonics are excluded from the noise signals. Usually expressed in dB. HARMONIC 1.Of a sinusoidal wave, an integral multiple of the frequency of the wave. Note: The frequency of the sine wave is called the fundamental frequency or the first harmonic, the second harmonic is twice the fundamen- tal frequency, the third harmonic is thrice the fundamen- tal frequency, etc. 2.Of a periodic signal or other periodic phenomenon, such as an electromagnetic wave or a sound wave, a compo- nent frequency of the signal that is an integral multiple of the fundamental frequency. Note: The fundamental frequency is the reciprocal of the period of the periodic phenomenon. Contrast with fundamental overtone. TOTAL HARMONIC DISTORTION (THD) The ratio of the sum of the power of first 9 harmonics above the fundamental frequency to the power of the fun- damental frequency. Usually expressed in dB. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) The ratio of the power of the desired signal (fundamental) to the sum of the power of all spectral components below Nyquist Frequency, including noise and distortion. Usually expressed in dB. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal power to the power of the single largest harmonic or spurious signal.

TYPICAL PERFORMANCE CHARACTERISTICS /MT54/MT48 /MT54/MT53 /MT55/MT48 /MT55/MT53 /MT56/MT48 /MT56/MT53 /MT57/MT48 /MT57/MT53 /MT50/MT48 /MT51/MT48/MT49/MT53 /MT50/MT53 /MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT83/MT78/MT82/MT44/MT32/MT83/MT73/MT78/MT65/MT68/MT44/MT32/MT150/MT84/MT72/MT68/MT44/MT32/MT83/MT70/MT68/MT82/MT32/MT40/MT100/MT66/MT41 /MT131/MT83/MT32/MT61/MT32/MT50/MT48/MT32/MT77/MT72/MT122 /MT48 /MT53/MT49 /MT48 /MT83/MT73/MT78/MT65/MT68 /MT83/MT78/MT82 /MT150/MT84/MT72/MT68 /MT83/MT70/MT68/MT82 Performance Versus Input Frequency /MT54/MT48 /MT54/MT53 /MT55/MT48 /MT55/MT53 /MT56/MT48 /MT56/MT53 /MT57/MT48 /MT57/MT53 /MT150/MT53/MT48 /MT48 /MT53/MT48 /MT49/MT48/MT48/MT150/MT50/MT53 /MT50/MT53 /MT55/MT53 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT40/MT68/MT101/MT103/MT114/MT101/MT101/MT115/MT32/MT67/MT41 /MT83/MT78/MT82/MT44/MT32/MT83/MT73/MT78/MT65/MT68/MT44/MT32/MT150/MT84/MT72/MT68/MT44/MT32/MT83/MT70/MT68/MT82/MT32/MT40/MT100/MT66/MT41 /MT83/MT73/MT78/MT65/MT68 /MT83/MT78/MT82 /MT150/MT84/MT72/MT68 /MT83/MT70/MT68/MT82 /MT131/MT73/MT78/MT32/MT61/MT32/MT53/MT32/MT77/MT72/MT122/MT131/MT83/MT32/MT61/MT32/MT50/MT48/MT32/MT77/MT72/MT122 Performance Versus Temperature Performance Versus Sample Rate Performance Versus Sample Rate /MT54/MT48 /MT54/MT53 /MT55/MT48 /MT55/MT53 /MT56/MT48 /MT56/MT53 /MT57/MT48 /MT57/MT53 /MT50/MT48 /MT51/MT48/MT49/MT53 /MT50/MT53 /MT83/MT97/MT109/MT112/MT108/MT101/MT32/MT82/MT97/MT116/MT101/MT32/MT40/MT77/MT83/MT80/MT83/MT41 /MT83/MT78/MT82/MT44/MT32/MT83/MT73/MT78/MT65/MT68/MT44/MT32/MT150/MT84/MT72/MT68/MT44/MT32/MT83/MT70/MT68/MT82/MT32/MT40/MT100/MT66/MT41 /MT83/MT73/MT78/MT65/MT68 /MT83/MT78/MT82 /MT150/MT84/MT72/MT68 /MT83/MT70/MT68/MT82 /MT112 /MT131/MT73/MT78/MT32/MT61/MT32/MT53/MT32/MT77/MT72/MT122 /MT48 /MT53/MT49 /MT48 /MT54/MT48 /MT54/MT53 /MT55/MT48 /MT55/MT53 /MT56/MT48 /MT56/MT53 /MT57/MT48 /MT57/MT53 /MT50/MT48 /MT51/MT48/MT49/MT53 /MT50/MT53 /MT83/MT97/MT109/MT112/MT108/MT101/MT32/MT82/MT97/MT116/MT101/MT32/MT40/MT77/MT83/MT80/MT83/MT41 /MT83/MT78/MT82/MT44/MT32/MT83/MT73/MT78/MT65/MT68/MT44/MT32/MT150/MT84/MT72/MT68/MT44/MT32/MT83/MT70/MT68/MT82/MT32/MT40/MT100/MT66/MT41 /MT83/MT73/MT78/MT65/MT68 /MT83/MT78/MT82 /MT150/MT84/MT72/MT68 /MT83/MT70/MT68/MT82 /MT131/MT73/MT78/MT32/MT61/MT32/MT49/MT48/MT32/MT77/MT72/MT122 /MT48 /MT53/MT49 /MT48 /MT83/MT73/MT78/MT65/MT68 /MT83/MT78/MT82 /MT150/MT84/MT72/MT68 /MT83/MT70/MT68/MT82 Differential Linearity Error Versus Code Integral Linearity Error Versus Code /MT48/MT50/MT48/MT48/MT48/MT52/MT48/MT48/MT48/MT54/MT48/MT48/MT48/MT56/MT48/MT48/MT48/MT49/MT48/MT48/MT48/MT48/MT49/MT50/MT48/MT48/MT48/MT49/MT52/MT48/MT48/MT48 /MT49/MT54/MT48/MT48/MT48 /MT49/MT56/MT48/MT48/MT48 /MT48/MT46/MT54 /MT48/MT46/MT52 /MT48/MT46/MT50 /MT48/MT46/MT48 /MT150/MT48/MT46/MT50 /MT150/MT48/MT46/MT52 /MT150/MT48/MT46/MT54 /MT150/MT48/MT46/MT56 /MT67/MT79/MT68/MT69 /MT76/MT83/MT66/MT115 /MT49/MT46/MT53 /MT49/MT46/MT48 /MT48/MT46/MT53 /MT48/MT46/MT48 /MT150/MT48/MT46/MT53 /MT150/MT49/MT46/MT48 /MT48/MT50/MT48/MT48/MT48/MT52/MT48/MT48/MT48/MT54/MT48/MT48/MT48/MT56/MT48/MT48/MT48/MT49/MT48/MT48/MT48/MT48/MT49/MT50/MT48/MT48/MT48/MT49/MT52/MT48/MT48/MT48 /MT49/MT54/MT48/MT48/MT48 /MT49/MT56/MT48/MT48/MT48 /MT67/MT79/MT68/MT69 /MT76/MT83/MT66/MT115

Figure 1 – Timing Diagram /MT68/MT97/MT116/MT97/MT32/MT83/MT49 /MT68/MT97/MT116/MT97/MT32/MT83/MT50/MT68/MT97/MT116/MT97/MT32/MT79/MT117/MT116 /MT68/MT48/MT150/MT68/MT49/MT51 /MT67/MT76/MT75 /MT40/MT86/MT73/MT78/MT43/MT41/MT32/MT150/MT32/MT40/MT86/MT73/MT78/MT150/MT41 /MT83/MT49 /MT116/MT79/MT68 /MT83/MT50 /MT83/MT51/MT116/MT67/MT76/MT75 /MT116/MT67/MT72 /MT116/MT67/MT76 /MT49/MT54/MT32/MT116/MT67/MT76/MT75 FUNCTIONAL DESCRIPTION The SPT8000 is a five-stage, pipeline analog-to-digital converter (ADC) implemented in a fine-line CMOS pro- cess. The block diagram on page one illustrates the device’s functional block-level implementation. The input sample-and-hold amplifier (SHA) guarantees its specified performance for the input signal frequencies up to the Nyquist frequency. It samples the differential analog input signal at the rising edge of CLK input and holds it for the next half-clock cycle. The SHA starts acquiring the input signal once CLK input goes low and acquires the next sample at the next rising edge of CLK. Each of the first four pipeline stages consists of a flash ADC (ADCn) and a multiplying digital-to-analog converter (MDACn), where n=1, 2, 3 or 4. The first stage flash ADC (ADC1) digitizes the output of the SHA and produces a lower-resolution digital code corresponding to the SHA output. The first stage MDAC1 subtracts from the SHA output the ideal voltage corresponding to the ADC1 code to generate the residue voltage, then amplifies the residue and passes it to the second stage. The subsequent stages 2 through 4 repeat the same operation, and ADC5 gives the last digital code corresponding to the output of MDAC4. The digital codes from ADC1 to ADC5 are time aligned and stored inside the “Data Alignment & Regis- ters” block. The SPT8000 incorporates one bit of overlap between two subsequent pipeline stages and uses this redundancy to digitally correct for errors in ADC1 through ADC4. In addi- tion, the SPT8000 employs an internal digital calibration circuitry to eliminate errors of the SHA and MDACs. Its function is controlled by an internal microcontroller. When in calibration mode, the SPT8000 configures itself such that errors of each stage can be measured by the ADC made of subsequent stages. The measured errors are stored in on-chip digital memory (RAM). During subse- quent normal conversions, the microcontroller looks up the RAM contents and makes digital corrections of the er- rors, to produce the final 14-bit digital output free of the errors. The 14-bit digital output along with OTR (out-of- range flag) are latched and buffered to drive the output pins. These output buffers have their own power supply and ground (OV DD and OGND), and can interface +5 V or +3.3 V external logic circuitry. The SPT8000 has an internal bandgap voltage reference that produces a temperature-stable 1 V output at V REF /EXTB pin. This voltage sets the input span of the SPT8000 about CM of 2.25 V. Therefore, the input span nominally is set to 1.25 V (V RC ) to 3.25 V (VRT ). Internal buffers provide low-impedance outputs for CM, VRT and VRC that are used throughout the pipeline stages. The out- put impedance of the VREF /EXTB pin is set relatively high (approximately 4.7 kΩ ), allowing the user to override the internal 1 V reference and change the input span. The user can also drive V RT and VRC directly with external buffers. To do this, VREF /EXTB must be shorted to AGND. Shorting this pin to AGND disables the internal buffers driving VRT and VRC . INTERNAL DIGITAL CALIBRATION The SPT8000 achieves the specified performance by in- ternal digital calibration, eliminating the need for external adjustments or trimming by the user. The calibration takes advantage of the fact that the accu- racy requirement for a pipeline stage is progressively reduced. For example, the SHA and MDAC1 must be ac- curate to 14 bits in order to achieve 14 bits of overall ADC accuracy. If we assume that ADC1’s resolution is N and that there is a one-bit overlap between the first and second stages, the accuracy requirement for MDAC2 is reduced to (14–N+1) bits (note: N>1). The obtainable accuracy of a stage is set by the circuit’s non-idealities such as device mismatches, finite bandwidth, finite gain, etc. For the specific implementation of the SPT8000, the

/MT43/MT68/MT51/MT47/MT53 /MT65/MT73/MT78 /MT84/MT49 /MT50/MT50 /MT86/MT73/MT78/MT150 /MT86/MT82/MT69/MT70/MT47/MT69/MT88/MT84/MT66 /MT78/MT67 /MT86/MT73/MT78/MT43 /MT78/MT67 /MT86/MT82/MT84 /MT86/MT82/MT67 /MT78/MT67 /MT67/MT77 /MT78/MT67 /MT86 /MT66/MT83 /MT68/MT49/MT50 /MT68/MT49/MT51 /MT66/MT85/MT83/MT89 /MT67/MT65/MT76 /MT82/MT83/MT69/MT84/MT66 /MT66/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT79/MT71/MT78/MT68 /MT68/MT48/MT32/MT40/MT76/MT83/MT66/MT41 /MT67/MT76/MT75 /MT65/MT71/MT78/MT68 /MT66/MT71/MT78/MT68 /MT78/MT67 /MT65/MT71/MT78/MT68 /MT68/MT51 /MT68/MT49 /MT68/MT50 /MT68/MT52 /MT68/MT53 /MT68/MT54 /MT68/MT55 /MT68/MT56 /MT68/MT57 /MT68/MT49/MT48 /MT68/MT49/MT49 /MT49 /MT49/MT49 /MT49/MT50 /MT50/MT51/MT51/MT51 /MT52/MT52 /MT83/MT80/MT84/MT56/MT48/MT48/MT48 /MT79/MT84/MT82 /MT78/MT67 /MT43/MT65/MT53/MT43/MT65/MT53 /MT43/MT65/MT53 /MT43/MT65/MT53 /MT43/MT65/MT53 /MT43/MT68/MT51/MT47/MT53 /MT43 /MT43 /MT43 /MT43 /MT51/MT52 /MT49/MT48/MT48/MT112/MT70 /MT54/MT56 /MT54/MT56/MT112/MT70 /MT43 /MT43 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT49/MT48/MT48/MT112/MT70 /MT43 /MT43 /MT46/MT48/MT49 /MT49/MT48/MT48/MT112/MT70 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT77/MT105/MT110/MT105/MT45/MT67/MT105/MT114/MT99/MT117/MT105/MT116 /MT40/MT84/MT52/MT45/MT54/MT84/MT41/MT73/MT110/MT116 /MT69/MT120/MT116 /MT46/MT48/MT49 /MT43 /MT49/MT48/MT48/MT112/MT70 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT43 /MT49/MT48/MT48/MT112/MT70 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT49/MT48/MT48/MT112/MT70 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT49/MT48/MT48/MT112/MT70 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT49/MT48/MT48/MT112/MT70 /MT48/MT46/MT49 /MT49/MT48 /MT50/MT48/MT48 /MT54/MT56 /MT67/MT76/MT75/MT45/MT73/MT110 /MT43 /MT73/MT110/MT116/MT101/MT114/MT102/MT97/MT99/MT101/MT32/MT76/MT111/MT103/MT105/MT99 /MT43/MT68/MT53 /MT56 /MT81/MT53 /MT86/MT67/MT67 /MT68/MT53 /MT68/MT52 /MT81/MT52 /MT68/MT51 /MT81/MT51 /MT67/MT80 /MT47/MT77/MT82 /MT68/MT48 /MT68/MT49 /MT81/MT49 /MT68/MT50 /MT81/MT50 /MT71/MT78/MT68 /MT81/MT48 /MT65/MT67/MT84/MT49/MT55/MT52 /MT82/MT101/MT115/MT101/MT116/MT47/MT67/MT97/MT108 /MT82/MT101/MT99/MT111/MT109/MT109/MT101/MT110/MT100/MT101/MT100/MT32/MT82/MT101/MT115/MT101/MT116/MT47/MT67/MT97/MT108/MT32/MT67/MT105/MT114/MT99/MT117/MT105/MT116/MT49/MT48/MT87 /MT49/MT48/MT87 /MT49/MT48/MT48/MT112/MT70 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT46/MT48/MT49 /MT52/MT46/MT55 /MT53/MT48 /MT76/MT83/MT66 /MT77/MT83/MT66 /MT66/MT117/MT115/MT121 /MT70/MT101/MT114/MT114/MT105/MT116/MT101/MT32/MT66/MT101/MT97/MT100 /MT79/MT84/MT82 /MT78/MT79/MT84/MT69/MT83/MT58 /MT61 /MT65/MT110/MT97/MT108/MT111/MT103/MT32/MT71/MT114/MT111/MT117/MT110/MT100 /MT61 /MT68/MT105/MT103/MT105/MT116/MT97/MT108/MT32/MT71/MT114/MT111/MT117/MT110/MT100 /MT43/MT65/MT53 /MT61 /MT65/MT110/MT97/MT108/MT111/MT103/MT32/MT43/MT53/MT32/MT86/MT111/MT108/MT116/MT115 /MT43/MT68/MT51/MT47/MT53/MT61 /MT68/MT105/MT103/MT105/MT116/MT97/MT108/MT32/MT43/MT51/MT32/MT111/MT114/MT32/MT43/MT53/MT32/MT86/MT111/MT108/MT116/MT115 /MT43/MT68/MT53 /MT55/MT32/MT67/MT76/MT75/MT32/MT99/MT121/MT99/MT108/MT101/MT115 /MT109/MT105/MT110/MT105/MT109/MT117/MT109 /MT43/MT68/MT53 /MT65/MT86/MT68/MT68 /MT65/MT86/MT68/MT68 /MT65/MT86/MT68/MT68 /MT65/MT86/MT68/MT68 /MT65/MT86/MT68/MT68 /MT79/MT86/MT68/MT68 Figure 5 – Typical Interface Circuit

A B C D Pin 1 E F G H I J K INCHES MILLIMETERS SYMBOL MIN TYP MAX MIN TYP MAX A 0.630 16.00 B 0.551 14.00 C 0.551 14.00 D 0.630 16.00 E 0.039 1.00 F 0.012 0.016 0.30 0.40 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.020 0.030 0.50 0.75 J 0.039 1.00 K 0-7 ° 0-7°

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE SPT8000SIT –40 to +85 °C 44L TQFP remains High until it completes the calibration. The internal calibration routine takes approximately 74.5 ms for 20 MHz clock input. The SPT8000 ignores the Analog Input when BUSY is High. When BUSY is Low, it is ready to convert the Analog Input. CAL Calibration Start Input. Holding CAL High for more than two falling edges of CLK, while RESETB is High, initiates the SPT8000’s internal calibration routine. RESETB Reset Input (active Low). Logic 0 on this asynchronous reset pin will set the internal digital state machine to its initial state and clear all internal calibration coefficients. VBS Noise Reduction Pin. Connect a noise reduction capacitor of 4.7 µF or larger from this pin to AGND. CM Common Mode Level Output. +2.25 V nominal. Connect a noise reduction capacitor of 4.7 µF or larger from this pin to AGND. VRC Lower Reference. +1.25 V nominal. This voltage sets the lower bound of analog input span. Connect a noise reduction capacitor of 4.7 µF or larger from this pin to AGND. VRT Upper Reference. +3.25 V nominal. This voltage sets the upper bound of analog input span. Connect a noise reduction capacitor of 4.7 µF or larger from this pin to AGND. VIN+ Analog Input Pin (+). The nominal span at this pin is +1.25 V to +3.25 V. VIN– Analog Input Pin (–). The nominal span at this pin is +3.25 V to +1.25 V. VREF /EXTB Voltage Reference I/O Pin. +1.00 V nominal. The voltage at this pin sets the span above and below CM for each analog input pin. Driving V REF /EXTB to 0 V will disable internal buffers driving VRT and VRC , allowing the user to drive VRT and VRC externally. Connect a noise reduction capacitor of 4.7 µF or larger from this pin to AGND. PIN ASSIGNMENTS /MT49/MT50 /MT49/MT51 /MT49/MT52 /MT49/MT53 /MT49/MT54 /MT49/MT55 /MT49/MT56 /MT49/MT57 /MT50/MT48 /MT50/MT49 /MT50/MT50 /MT52/MT52 /MT52/MT51 /MT52/MT50 /MT52/MT49 /MT52/MT48 /MT51/MT57 /MT51/MT56 /MT51/MT55 /MT51/MT54 /MT51/MT53 /MT51/MT52 /MT49 /MT50 /MT51 /MT52 /MT53 /MT54 /MT55 /MT56 /MT57 /MT49/MT48 /MT49/MT49 /MT51/MT51 /MT51/MT50 /MT51/MT49 /MT51/MT48 /MT50/MT57 /MT50/MT56 /MT50/MT55 /MT50/MT54 /MT50/MT53 /MT50/MT52 /MT50/MT51 /MT65/MT71/MT78/MT68 /MT66/MT71/MT78/MT68 /MT78/MT47/MT67 /MT65/MT86 /MT68/MT68 /MT65/MT71/MT78/MT68 /MT65/MT86/MT68/MT68 /MT67/MT76/MT75 /MT68/MT48/MT32/MT40/MT76/MT83/MT66/MT41 /MT68/MT49 /MT68/MT50 /MT68/MT51 /MT68/MT52 /MT68/MT53 /MT68/MT54 /MT68/MT55 /MT68/MT56 /MT68/MT57 /MT68/MT49/MT48 /MT68/MT49/MT49 /MT65/MT71/MT78/MT68 /MT78/MT47/MT67 /MT66/MT71/MT78/MT68 /MT65/MT86/MT68/MT68 /MT67/MT65/MT76 /MT66/MT85/MT83/MT89 /MT79/MT84/MT82 /MT68/MT49/MT51/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT49/MT50 /MT86/MT82/MT69/MT70/MT47/MT69/MT88/MT84/MT66 /MT78/MT47/MT67 /MT86/MT73/MT78/MT150 /MT86/MT73/MT78/MT43 /MT78/MT47/MT67 /MT86/MT82/MT84 /MT86/MT82/MT67 /MT78/MT47/MT67 /MT86/MT66/MT83 /MT65/MT86/MT68/MT68 /MT79/MT71/MT78/MT68 /MT79/MT86/MT68/MT68 /MT82/MT69/MT83/MT69/MT84/MT66 /MT65/MT86/MT68/MT68 /MT67/MT77 /MT78/MT47/MT67 /MT83/MT80/MT84/MT56/MT48/MT48/MT48 PIN FUNCTIONS Name Description AGND Ground AV DD +5 V Supply N/C No Connect. Leave the pin open or tie it to AGND. BGND Ground CLK Clock Input OGND Ground for BUSY , OTR, and Data Bit Outputs OV DD +3.3 V to +5 V Supply for BUSY , OTR, and Data Bit Outputs D0 –D13 Data Bit Outputs. D0=LSB, D13=MSB OTR Out of Range Output. OTR goes High for the Analog input above (overrange) or below (underrange) the full-scale range. The corresponding Data Bit Outputs are all 1s for overrange, and all 0s for underrange. BUSY Busy Output. BUSY goes High when the SPT8000 goes into its internal calibration routine and LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation