SPT7862 CADEKA | Alldatasheet
Document overview
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Technical content
10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER
FEATURES
- Dual-channel, 10-Bit, 40 MSPS analog-to-digital converter
- Low power dissipation: 320 mW (typical)
- Internal track-and-hold
- Single +5 volt supply
- Tri-state, TTL/CMOS-compatible outputs
- Selectable +3 or +5 V logic I/O
- High ESD protection of 3,500 volts minimum
APPLICATIONS
- Video set-top boxes
- Cellular base stations
- QPSK/QAM RF demodulation
- S-video digitizers
- Composite video digitizers
- Portable and handheld instrumentation
- Medical ultrasound
- Cable modems
- Video frame grabbers GENERAL DESCRIPTION The SPT7862 contains two separate 10-bit CMOS analog- to-digital converters that have sampling rates of up to 40 MSPS. Each device has its own separate clock and refer- ence inputs so that they can be used independently in multichannel applications or can be driven from the same inputs for demanding quadrature demodulation and S-video applications. On-chip track-and-hold and advanced propri- etary circuit design in a CMOS process technology provide very good dynamic performance. The SPT7862 operates from a single +5 V supply. Digital data outputs are user selectable at +3 or +5 V. Output data format is straight binary. The SPT7862 is available in a 64-lead TQFP package (10 x 10 mm ) over the industrial temperature range of –40 °C to +85 °C. ADC Reference Ladder Timing Generation VINA VRHF A VRHSA VRLF A VRLSA CLK A ADC Reference Ladder Timing Generation VINB VRHFB VRHSB VRLFB VRLSB CLK B Output Buffers OV DD A (+3.3/5.0 V) DA9–0 EN Output Buffers OV DDB (+3.3/5.0 V) DB9–0 AV DD AGND DVDD DGND VINRA VINRB OGND A OGND B DA VB DA VA BLOCK DIAGRAM
TA=TMIN to TMAX , AVDD =DV DD =OV DD =+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified. TEST TEST SPT7862 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 10 Bits DC Accuracy Integral Nonlinearity V ±1.0 LSB Differential Nonlinearity V ±0.5 LSB Analog Input Input Voltage Range IV V RLS VRHS V Input Resistance V 29 k Ω Input Capacitance V 5.0 pF Input Bandwidth (Small Signal) V 250 MHz Offset V ±2.0 LSB Gain Error V ±2.0 LSB Reference Input Resistance V 500 Ω Voltage Range VRLS IV 0 – 2.0 V VRHS IV 3.0 – AV DD V VRHS – VRLS V 1.0 4.0 5.0 V Δ(VRHF – VRHS )V 9 0 m V Δ(VRLS – VRLF )V 7 5 m V Conversion Characteristics Maximum Conversion Rate VI 40 MHz Minimum Conversion Rate IV 2 MHz Pipeline Delay (Latency) IV 12 Clock Cycles Aperture Delay Time V 4.0 ns Aperture Jitter Time V 7 ps(rms) Dynamic Performance Effective Number of Bits ƒIN = 3.58 MHz V 9.1 Bits ƒIN = 10.0 MHz VI 7.8 8.3 Bits Signal-to-Noise Ratio (without Harmonics) ƒIN = 3.58 MHz V 57.9 dB ƒIN = 10.0 MHz T A = +25 °C I 52 54.2 dB ƒIN = 10.0 MHz T A = TMIN to TMAX IV 47 dB ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Supply Voltages Input Voltages Output Temperature
Harmonic Distortion 9 Distortion bins from ƒIN = 3.58 MHz 1024 pt FFT V –63 dB ƒIN = 10.0 MHz T A = +25 °C I –55.7 –52 dB ƒIN = 10.0 MHz T A = TMIN to TMAX IV –52 dB Signal-to-Noise and Distortion (SINAD) ƒ IN = 3.58 MHz V 56.7 dB ƒIN = 10.0 MHz T A = +25 °C I 49 51.8 dB ƒIN = 10.0 MHz T A = TMIN to TMAX IV 46 dB Spurious Free Dynamic Range ƒIN = 10.0 MHz V 56.8 58.3 60 dB Differential Phase V ±0.3 Degree Differential Gain V ±0.3 % Channel-to-Channel Crosstalk ƒIN = 3.58 MHz V 74 dB ƒIN = 10.0 MHz V 67 dB Inputs Logic 1 Voltage VI 2.1 V Logic 0 Voltage VI 0.8 V Maximum Input Current Low VI –10 +10 µA Maximum Input Current High VI –10 +10 µA Input Capacitance V +5 pF Digital Outputs Logic 1 Voltage I OH = 0.5 mA VI OV DD –0.5 V Logic 0 Voltage I OL = 1.6 mA VI 0.44 V tRISE 15 pF load V 10 ns tFALL 15 pF load V 10 ns Output Enable to Data Output Delay 20 pF load, T A = +25 °C V 10 ns 50 pF load over temp. V 22 ns Power Supply Requirements Voltages OVDD IV 3.0 5.0 V DV DD IV 5.0 V AV DD IV 5.0 V Currents AIDD + DIDD VI 52 62 mA OIDD VI 12 14 mA Power Dissipation VI 320 380 mW Power Supply Refection Ratio V 70 dB TEST LEVEL CODES All electrical characteristics are subject to the follow- ing conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaran- teed over specified temperature range. TEST LEVEL I II III IV V VI ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX , AVDD =DV DD =OV DD =+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified. TEST TEST SPT7862 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
TYPICAL PERFORMANCE CHARACTERISTICS 0 5 10 15 20 THD SNR SINAD THD, SNR, SINAD vs Input Frequency Input Frequency (MHz) THD, SNR, SINAD (dB) 0 10 30 50 THD SNR SINAD THD, SNR, SINAD vs Sample Rate Sample Rate (MSPS) THD, SNR, SINAD (dB) 52 0 4 01 ƒIN = 10 MHz –55 –40 0 25 70 85 125 THD SNR SINAD THD, SNR, SINAD vs Temperature Temperature (°C) THD, SNR, SINAD (dB) –25 ƒIN = 10 MHz 0 10 30 50 Power Dissipation vs Sample Rate Sample Rate (MSPS) Power Dissipation (mW) 52 0 4 01 500 400 300 200 100 600 ƒIN = 10 MHz Spectral Response Frequency (MHz) Amplitude (dB)
Very few external components are required to achieve the stated device performance. Figure 2 shows the typical inter- face requirements when using the SPT7862 in normal circuit operation. The following sections provide descrip- tions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING log supply as shown in figure 2. A separate digital supply using this power supply configuration to prevent a possible latch-up condition on power up. OPERATING DESCRIPTION The general architecture for the dual CMOS ADC is shown in the block diagram. Each ADC design contains 16 identi- cal successive approximation (SAR) ADC sections (all oper- ating in parallel), a 16-phase clock generator, an 11-bit 16:1 digital output multiplexer, correction logic, and a voltage ref- erence generator which provides common reference levels for each ADC section. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each SAR ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as follows: Table II – Clock Cycles Clock Operation
1 Reference zero sampling
2 Auto-zero comparison
3 Auto-calibrate comparison
4 Input sample
5–15 11-bit SAR conversion
16 Data transfer
The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent SAR ADC sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one SAR ADC section. After 16 clock periods, the timing cycle repeats. The latency from analog input sample to the corresponding digital output is 12 clock cycles. DV DD OV DD A Interface Logic +D5V+A5 +A5 10 µF +D5 Interface Logic +D5V +3V/5V +3V/5V 10DA9–0 OGND A DA VA OV DDB DB9–0 OGND B DA VB EN Enable/Tri-State (Enable = Active Low) AV DD FB CLK B ClockINB +5V Analog +5V Analog Return VRHF A VRHSA VRLSA VRLF A VINA VINRA VCAL CLK A VRHFB VRHSB VRLSB VRLFB VINB VINRB VINA ClockINA Ref In (+4V) AGND DGND* SPT7862 *To reduce the possibility of latch-up, avoid connecting the DGND pins of the ADC to the digital ground of the system. NO TES: 1. FB is a 10 µH inductor or ferrite bead. It is to be located as close to the device as possible. 2.All capacitors are 0.1 µF surface-mount, unless otherwise specified. Ref In (+4V) +5V Digital +5V Digital Return 10 µF VINB Figure 2 – Typical Interface Circuit ply voltages on the SPT7862 be derived from a single ana- CADEKA suggests that both the digital and the analog sup- should be used for all interface circuitry. CADEKA suggests
- Since only 16 comparators are used, a huge power sav- ings is realized.
- The auto-zero operation is done using a closed loop sys- tem that uses multiple samples of the comparator’s response to a reference zero.
- The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration volt- age for each SAR ADC section.
- Capacitive displacement currents, which can induce sam- pling error, are minimized since only one comparator samples the input during a clock cycle.
- The total input capacitance is very low, since sections of the converter which are not sampling the signal are iso- lated from the input by transmission gates. VOLTAGE REFERENCE The SPT7862 requires the use of a single external voltage reference for driving the high side of each reference ladder. Each ladder is totally independent and may operate at dif- ferent voltage levels. The high side of the reference ladder must operate within a range of 3 V to 5 V. The lower side of each ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input volt- age range will track the total voltage difference measured between the ladder sense lines, V RHS and VRLS . Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line volt- ages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than ±2 LSB can be obtained. In cases in which wider variations in offset and gain can be tolerated, the external reference can be tied directly to V RHF and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a .01 µF ca- pacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account: The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from V RHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS . Figure 3 – Ladder Force/Sense Circuit for Each ADC AGND VRHF VRHS VRLS VRLF VIN All capacitors are 0.01 µF
4 N/C
Figure 4 – Simplified Reference Ladder Drive Circuit Without Force/Sense Circuit R/2 R R R R R R R/2 R=30 Ω (typ) All capacitors are 0.01 µF VRLF (AGND) 0.0 V VRLS (0.075 V) VRHS (+3.91 V) 90 mV 75 mV +4.0 V External Reference Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF – VRHS = 2.25 % of (VRHF – VRLF ) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS – VRLF = 1.9 % of (VRHF – VRLF ) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF and VRLF is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V) and a 75 mV increase is seen at VRLS (= 0.075 V).
VINA and VINB are the analog inputs and VINRA and VINRB are the respective input returns. Each input return is typically tied to its respective low side reference ladder sense line. (See Figure 2.) The input voltage range is from V RLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See the Voltage Reference section.) The drive requirements for the analog inputs are very mini- mal, when compared to most other converters, due to the SPT7862’s extremely low input capacitance of only 5 pF and a high input resistance in excess of 29 kΩ . Each analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. Figure 6 – On-Chip Protection Circuit VDD Analog Pad 120 Ω 120 Ω CLOCK INPUT Each ADC is driven independently from a single-ended TTL-input clock. Because the pipelined architecture oper- ates on the rising edge of the clock input, each ADC can operate over a wide range of input clock duty cycles without degrading the dynamic performance. DIGITAL OUTPUTS The digital outputs (DA9–0 and DB9–0) are driven by sepa- rate supplies (OV DDA and OV DDB ) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7862’s TTL/CMOS-compatible outputs with the user’s logic system supply. Each digital output supply may be driven indepen- dently. The format of the output data (D0–D9) is straight binary. (See Table III.) The outputs are latched on the rising edge of CLK. The EN pin controls tri-stating of both data output ports. These outputs can be switched into a tri-state mode by bringing EN high. Table III – Output Data Information ANALOG INPUT OVERRANGE OUTPUT CODE D10 D9–D0 +F.S. + 1/2 LSB 1 11 1111 1111 +F.S. –1/2 LSB 0 11 1111 111Ø +1/2 F.S. 0 ØØ ØØØØ ØØØØ +1/2 LSB 0 00 0000 000Ø
0.0 V 0 00 0000 0000
(Ø indicates the flickering bit between logic 0 and 1) EVALUATION BOARD The EB7862 evaluation board is available to aid designers in demonstrating the full performance of the SPT7862. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note describing the operation of this board as well as information on the testing of the SPT7862 is also available. Contact the factory for price and availability. Figure 5 – Recommended Input Protection Circuit 47 Ω ADCBuffer AV DD+V D1 = D2 = Hewlett Packard HP5712 or equivalent CALIBRATION The SPT7862 uses a user-transparent, auto-calibration scheme to ensure 10-bit accuracy over time and tempera- ture. Gain and offset errors are continually adjusted to 10-bit accuracy during device operation. Upon power up, the SPT7862 begins its calibration algo- rithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10- bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon power up of 250 µsec (for a 40 MHz clock). Once calibrated, the SPT7862 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7862 to remain in calibration. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness and prevents latch-up under severe discharge conditions with- out degrading analog transition times.
A 0.465 0.480 11.80 12.20 B 0.390 0.398 9.90 10.10 C 0.017 0.023 0.42 0.58 D 0.006 0.010 0.15 0.26 E 0.295 typ 7.5 typ F 0.433 typ 0.000 11 typ G 0.055 0.067 1.40 1.70 H 0.005 0.005 0.125 0.132 I 0-10 ° 0-10° J 0.012 0.028 0.30 0.70 K 0.000 0.008 0.00 0.20 PACKAGE OUTLINE 64-Lead TQFP A B 64 49 1 48 3217 C D E F G H I J K Index
PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT7862SIT –40 to +85 °C 64-Lead TQFP
ORDERING INFORMATION
PIN ASSIGNMENTS PIN FUNCTIONS Pin Name Description VINA Analog Input (A) VINB Analog Input (B) VINRA Analog Input Return (A) VINRB Analog Input Return (B) VRHFA/B VREF High Force Input A/B VRHSA/B VREF High Sense Input A/B VRLFA/B VREF Low Force Input A/B VRLSA/B VREF Low Sense Input A/B AV DD Analog VDD DV DD Digital VDD OV DD A/B Digital Output Power Supply +3.3 V to +5.0 V AGND Analog Ground DGND Digital Ground OGND A/B Digital Output Ground CLK A/B Input Clock A/B (separate) EN Enable Outputs (Active Low) D0–9A Data Outputs A (10 bits) D0–9B Data Outputs B (10 bits) DAV A/B Data Available A/B VCAL Decoupling Pin 32313029282726252423222120191817