SPT7853SCT

SPT7853 CADEKA | Alldatasheet

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TRIPLE 10-BIT, 30 MSPS A/D CONVERTER BLOCK DIAGRAM GENERAL DESCRIPTION The SPT7853 has three 10-bit analog-to-digital converters on one CMOS chip, each with a sample rate of 30 MSPS. This device is ideal for professional-level video decoding to 4:2:2/4:4:4 CCIR-601 standard specifications for compo- nent digital video, including YCrCb and RGB decoding, pro- fessional video equipment, video frame grabbers, medical imaging, flat panel display and projection applications. The SPT7853 offers significant advantages over discrete single-channel A/D implementations. Board area, package count, system cost and power dissipation can greatly be reduced by using a single SPT7853 device. In addition, several performance advantages exist, including low chan- nel-to-channel cross-talk noise and well matched channel- to-channel gain specifications. The three analog-to-digital converters are driven from a common 2X sample rate CMOS clock. The SPT7853 typically consumes only 580 mW of total power from a single +5 V supply. Digital outputs can operate with +3 V or +5 V logic and are tri-state capable. The SPT7853 is offered in a small 52-pin thin quad flat pack (TQFP) package and operates over the 0 to +70 °C com- mercial temperature range.

APPLICATIONS

• CCIR-601 (4:2:2/4:4:4) digital component video
• RGB video decoding
• Medical imaging
• Flat panel displays
• PC projectors

FEATURES

• Three 10-bit, 30 MSPS ADCs on one chip
• SINAD of 54.5 dB @ ƒIN = 3.58 MHz
• Channel-to-channel cross talk: –66 dB typical
• Channel-to-channel gain matching of <0.1 dB
• Single 2X sample rate clock
• Total power dissipation: 580 mW (typical)
• Tri-state +3 V to +5 V digital outputs CMOS-compatible
• Single +5 V power supply Timing Generation Reference Ladder ADC A ADC B ADC C T/H T/H T/H VINB DA0–9 Clock VINA VINC DB0–9 DC0–9 VRH Force/Sense 2 VRL Force/Sense 2 Output Enable Output Buffer Output Buffer Output Buffer DA V

TA=TMIN to TMAX , VDD =OV DD =+5.0 V, VIN=0 to 4 V, ƒS=30 MSPS, ƒCLK =60 MHz, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified. TEST TEST SPT7853 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC Performance Resolution 10 Bits Differential Linearity ƒs = 20 MSPS V ±0.5 LSB Integral Linearity ƒs = 20 MSPS V ±1.0 LSB Analog Input Input Voltage Range2 IV V RLS VRHS V Input Resistance IV 50 k Ω Input Capacitance V 5 pF Input Bandwidth (Full Power) V 120 MHz –Full-Scale Error 2 V ±0.5 %FS +Full-Scale Error2 V ±0.25 %FS Reference Ladder Resistance VI 120 170 220 Ω Timing Characteristics Conversion Rate VI 30 MSPS Clock Duty Cycle Range IV 45 55 % Clock-to-Sample Rate Relationship IV 2:1 Pipeline Delay (Latency) IV 12 Clock Cycles Aperture Delay Time V 5 ns Aperture Jitter Time V 15 ps Dynamic Performance Effective Number of Bits ƒIN = 3.58 MHz @ 25 °C VI 8.3 8.7 Bits @ 0 to 70 °C V 8.0 Bits ƒIN = 10.0 MHz @ 25 °C V 7.4 Bits Signal-to-Noise Ratio ƒIN = 3.58 MHz @ 25 °CV I 5 3 5 6 d B @ 0 to 70 °C V 51.6 dB ƒIN = 10.0 MHz @ 25 °C V 48 dB Total Harmonic Distortion ƒIN = 3.58 MHz @ 25 °C VI –56 –58 dB @ 0 to 70 °C V –54.6 dB ƒIN = 10.0 MHz @ 25 °C V –51 dB Signal-to-Noise + Distortion Ratio ƒIN = 3.58 MHz @ 25 °C VI 52 54.5 dB @ 0 to 70 °C V 49.7 dB ƒIN = 10.0 MHz @ 25 °C V 46 dB Supply Voltages Temperature Output Currents Temperature Note: 1. Operation at any Absolute Maximum Rating is not implied and operation beyond the ratings may cause damage to the device. See Electrical Specifications for proper nominal applied conditions in typical applications. ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C 2The full-scale range spans the reference ladder sense pins, VRHS and VRLS . Refer to the Voltage Reference section for discussion.

TA=TMIN to TMAX , VDD =OV DD =+5.0 V, VIN=0 to 4 V, ƒS=30 MSPS, ƒCLK =60 MHz, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified. TEST TEST SPT7853 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Dynamic Performance Spurious Free Dynamic Range ƒIN = 3.58 MHz @ 25 °C V 65 dBc @ 0 to 70 °C V 56.3 dBc Channel-to-Channel Cross Talk ƒIN = 3.58 MHz V –66 dB Channel-to-Channel Gain Matching V ±0.1 dB Differential Phase V 0.5 Degree Differential Gain V 0.5 % Power Supply Requirements VDD Supply Voltage IV +4.75 +5.0 +5.25 V OV DD Supply Voltage IV +2.7 +5.25 V Supply Current IDD VI 81 105 mA OIDD V9 1 1 m A Power Dissipation Without reference ladder C L = 10 pF V 485 mW Including reference ladder C L = 10 pF VI 580 750 mW Digital Inputs/Outputs Digital Input Logic 1 Voltage VI 4.0 V Digital Input Logic 0 Voltage VI 1.0 V Digital Output Logic 1 Voltage I OH = 500 µAV I O V DD –0.5 V Digital Output Logic 0 Voltage IOL = 800 µA VI 0.4 V tRISE/tFALL (CL = 10 pF) V 10 ns OEN to Data Output V 12 ns TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at T A = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at T A = +25 °C. Parameter is guaranteed over specified temperature range. TEST LEVEL I II III IV V VI

TYPICAL PERFORMANCE CHARACTERISTICS 02 6 8 1 0 THD SNR SINAD THD, SNR, SINAD vs Input Frequency Input Frequency (MHz) THD, SNR, SINAD (dB) 01 0 2 03 04 0 THD SNR SINAD THD, SNR, SINAD vs Sample Rate Sample Rate (MSPS) THD, SNR, SINAD (dB) ƒIN=3.58 MHz 02 04 06 08 0 THD SNR SINAD THD, SNR, SFDR, SINAD vs Temperature Temperature (°C) THD, SNR, SFDR, SINAD (dB) SFDR 600 500 400 300 200 100 0 5 10 15 20 Power Dissipation vs Sample Rate1 Sample Rate (MSPS) Power Dissipation (mW) 25 30 35 40 Note 1: Power dissipation does not include reference. –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 25 50 75 100 125 Large Signal Bandwidth Frequency (MHz) dB 0.5 1.0 –20 –40 –60 –80 –100 –120 0 5 10 15 x106 Spectral Response Frequency (MHz) Amplitude (dB) CLK 30 MHz ƒIN=3.58 MHz

Very few external components are required to achieve the stated device performance. Figure 2 shows the typical inter- face requirements when using the SPT7853 in normal cir- cuit operation. The following sections provide descriptions of the major functions and outline critical performance crite- ria to consider for achieving the optimal device perfor- mance. Figure 2 – Typical Interface Circuit The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each SAR ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as follows: Table II – Clock Cycles Clock Operation

1 Reference zero sampling

2 Auto-zero comparison

3 Auto-calibrate comparison

4 Input sample

5-15 11-bit SAR conversion

16 Data transfer

The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by two clock cycles so that the analog input is sampled on every other cycle of the input clock by exactly one ADC section. After 16 clock periods, the timing cycle repeats. The sample rate for the configura- tion is one-half of the clock rate, e.g., for a 60 MHz clock rate, the input sample rate is 30 MHz. The latency from ana- log input sample to the corresponding digital output is 12 clock cycles.

• Since only eight comparators are used, a huge power savings is realized.
• The auto-zero operation is done using a closed loop sys- tem that uses multiple samples of the comparator’s response to a reference zero.
• The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section.
• Capacitive displacement currents, which can induce sam- pling error, are minimized since only one comparator samples the input during a clock cycle.
• The total input capacitance is very low since sections of the converter which are not sampling the signal are iso- lated from the input by transmission gates. VOLTAGE REFERENCE The SPT7853 requires the use of a single external voltage reference for driving the high side of the reference ladder of each ADC. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured between the ladder sense lines, V RHS and VRLS . POWER SUPPLIES AND GROUNDING The digital and the analog supply voltages on the SPT7853 are internally derived from a single analog supply. A sepa- rate digital supply must be used for all interface circuitry (OV DD ). Connect the digital ground (DGND) to the analog ground plane, as shown in figure 2, to prevent possible latch-up condition. OPERATING DESCRIPTION The general architecture for the CMOS ADC is shown in the block diagram. Each ADC uses a parallel SAR architecture. Each contains eight identical successive approximation ADC sections, all operating in parallel, a 16-phase clock generator, an 11-bit 8:1 digital output multiplexer, correc- tion logic, and a voltage reference generator which pro- vides common reference levels for each ADC section. +A5 +4.7 AGND REF IN (+4V typ) VIN1 VIN2 VIN3 4.7 + +D2.7V-5V DGND Enable +D2.7V–5V VRHF VRHS VRLF VRLS VRLT VCAL VINA VINB VINC AGND DGND VDD OEN DA0–9 DB0–9 DC0–9 DAV OV DD CLK SPT7853 1. Place the Ferrite bead as close to the ADC as possible. 2. All capacitors are 0.01 microfarad surface mount unless otherwise specified. 3. Place 0.01 microfarad surface mount as close to the respective decoupling pin as possible. 4. All input pins (references, analog inputs, clock input and /OEN) must be protected to within the specified absolute maximum ratings. NOTES: Interfacing Logic Clock Input Ferrite Bead AGND DGND Hi-Z

The SPT7853 is driven from a single-ended input clock. Be- cause the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. The device’s sample rate is 1/2 of the input clock frequency. (See the timing diagram.) DIGITAL OUTPUTS The digital outputs for each channel (D0–D9) are driven by a separate supply (OV DD ) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7853’s CMOS- compatible outputs with the user’s logic system supply. The format of the output data (D0–D9) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing OEN high. Table III – Output Data Information ANALOG INPUT OUTPUT CODE D9-D0 +F.S. + 1/2 LSB 11 1111 1111 +F.S. –1/2 LSB 11 1111 111Ø +1/2 F.S. ØØ ØØØØ ØØØØ +1/2 LSB 00 0000 000Ø

0.0 V 00 0000 0000

(Ø indicates the flickering bit between logic 0 and 1). DATA AVAILABLE The Data Available pin goes high when the data output bits are valid (see figure 1b). Note: Optimal performance of the data valid pin is achieved when using an input clock with a minimum span range of ≤1 V (clock low) to ≥4 V (clock high). EVALUATION BOARD The EB7853 Evaluation Board is available to aid designers in demonstrating the full performance of the SPT7853. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7853) describing the operation of this board as well as information on the testing of the SPT7853 is also available. Contact the factory for price and availability. CALIBRATION The SPT7853 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit accuracy during device operation. This process is completely transparent to the user. Upon powerup, the SPT7853 begins its calibration algo- rithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10-bit LSB. Since the calibration algorithm is an over- sampling process, a minimum of 10k clock cycles are re- quired. This results in a minimum calibration time upon powerup of 150 µsec. Once calibrated, the SPT7853 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7853 to remain in calibration. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge condi- tions without degrading analog transition times. Figure 6 – On-Chip Protection Circuit VDD Analog Pad 120 Ω 120 Ω POWER SUPPLY SEQUENCING CONSIDERATIONS All logic inputs should be held low until power to the device has settled to the specific tolerances. Avoid power decoupling networks with large time constants which could delay V DD power to the device.

A B C D E F G H I J K INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.472 typ 12.0 typ B 0.394 typ 10.0 typ C 0.472 typ 12.0 typ D 0.394 typ 10.0 typ E 0.0630 typ 1.60 F 0.0256 typ 0.65 typ G 0.009 0.013 0.22 0.33 H 0.0394 typ 1.0 typ I 0.004 0.006 0.09 0.16 J 0.018 0.029 0.45 0.75 K0 ° 7° 0° 7° PACKAGE OUTLINE 52-Lead TQFP

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT7853SCT 0 to +70 °C 52-Pin TQFP

ORDERING INFORMATION

VINA Analog input for channel A VINB Analog input for channel B VINC Analog input for channel C DA0–DA9 CMOS-compatible digital output data for channel A (+2.7 V to +5.0 voltage logic) DB0–DB9 CMOS-compatible digital output data for channel B (+2.7 V to +5.0 voltage logic) DC0–DC9 CMOS-compatible digital output data for channel C (+2.7 V to +5.0 voltage logic) OEN Output enable pin. (Low = enabled; High = high impedance) CLK CMOS-compatible input clock (2x of sample rate). VRHF Input for top of reference ladder (force) VRHS Input for top of reference ladder (sense) VRLF Input for bottom of reference ladder (force) VRLS Input for bottom of reference ladder (sense) VDD Analog +5 V; Digital +5 V OV DD Output supply +2.7 / +5 V AGND Analog ground DGND Digital ground VRLT Tie to VRLS VCAL Calibration reference DAV Data available PIN FUNCTIONS VRHS VRLF VRLS VRLT AGND VINA AGND VINB VDD VCAL AGND VINC AGND CLK DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DA V OV DD N/C OEN DC0 DC1 DC2 DC3 DC4 DC5 DC6 DC7 DC8 DC9 VDD VRHF AGND DA 9 DA 8 DA 7 DA 6 DA 5 DA 4 DA 3 DA 2 DA 1 DA 0 DGND