SPT7851 CADEKA | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 9

Technical content

Features

  • 10-Bit, 20 MSPS Analog-to-Digital converter
  • Monolithic CMOS
  • Internal track-and-hold
  • L ow input capacitance: 1.4 pF
  • L ow power dissipation: 79mW
  • 2.8 to 3.6V power supply range
  • TTL-compatible outputs
  • -40°C to +85°C operation

Applications

  • CCD imaging cameras and sensors
  • Medical imaging
  • RF communications
  • Document and film scanners
  • Electro-optics
  • T ransient signal analysis
  • Handheld equipment

Description

The SPT7851 10-bit, 20 MSPS analog-to-digital converter has a pipelined converter architecture built in a CMOS process. It delivers high performance with a typical power dissipation of only 79mW. With low distortion and high dynamic range, this device offers the performance needed for imaging, multimedia, telecommunications and instru- mentation applications. The SPT7851 is available in a 44-lead Thin Quad Flat Pack (TQFP) package in the industrial temperature range (-40°C to +85°C). SPT7851 10-Bit, 20 MSPS, 79mW Analog-to-DIgital Converter Functional Block Diagram Stage Stage Stage Stage Clock Driver Digital Delays, Error Correction and Output VIN+ VIN– VREF+ VREF– CLK Digital Output (D0 – D9) DACADC + G=2– D<1…0> Pipeline Stage www.cadeka.com

REV. 1B October 2003 DATA SHEET SPT7851 Electrical Specifications T A = T MIN MAX , V DD1 = V DD2 = V DD3 = 3.3V, V REF– = 1.0V, V REF+ = 2.0V, Common Mode Voltage = 1.65V , ƒ CLK = 20 MSPS, Bias1 = 90 µ A, Bias2 = 9.5 µ A, Differential Input, Duty Cycle = 50%; unless otherwise noted) Parameter Conditions Test Level Min Typ Max Units DC Accuracy Resolution 10 Bits Differential Linearity V ±0.6 LSB Integral Linearity V ±0.75 LSB No Missing Codes VI Analog Input Input Voltage Range (differential) IV ±0.6 ±1.0 ±1.7 V Common Mode Input Voltage IV 1.2 1.65 1.9 V Input Capacitance V 1.4 pF Input Bandwidth (large signal) V 120 MHz Offset (mid-scale) V IN+ = V IN- = V CM V ±1.0 %FSR Gain Error V 0.3 %FSR Reference Voltages Reference Input Voltage Range V REF+ – V REF– IV 0.6 1.0 1.7 V Negative Reference Voltage (V REF– )I V 0.9 1.0 1.3 V Positive Reference Voltage (V REF+ )I V 1.9 2.0 2.9 V Common Mode Output Voltage (V CM O = -1 µ AV I 1.3 1.65 1.8 V V REF+ Current V 35 µ A V REF– Current V -25 µ A Switching Performance Maximum Conversion Rate VI 20 MHz Pipeline Delay (see Figure 1) IV 7.5 CLK Aperture Delay Time (T AP )V 5 n s Aperture Jitter Time V 10 ps-rms Dynamic Performance Signal-To-Noise Ratio ƒ IN = 5MHz VI 57 58 dB ƒ IN = 10MHz V 58 dB Effective Number of Bits ƒ IN = 5MHz VI 9.0 9.3 Bits ƒ IN = 10MHz V 9.0 Bits Total Harmonic Distortion ƒ IN = 5MHz VI -68 -61 dB ƒ IN = 10MHz V -60 dB Signal-To-Noise and Distortion ƒ IN = 5MHz VI 56 58 dB ƒ IN = 10MHz V 56 dB Spurious Free Dynamic Range ƒ IN = 5MHz VI 62 70 dB ƒ IN = 10MHz V 61 dB Differential Phase V 0.2 deg Differential Gain V 0.5 % Guaranteed

REV. 1B October 2003 SPT7851 DATA SHEET TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. LEVEL TEST PROCEDURE IV Parameter is guaranteed (but not tested) by design or characterization data. V Parameter is a typical value for information purposes only. VI 100% production tested at T A = +25°C. Parameter is guaranteed over specified temperature range. Absolute Maximum Ratings (beyond which the device may be damaged) Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Digital Inputs Logic 1 Voltage VI 80% V DD Logic 0 Voltage VI 20% V DD Maximum Input Current Low V IN = GND VI ±1 µ A Maximum Input Current High V IN = V DD VI ±1 µ A Input Capacitance V 1.8 pF Digital Outputs Logic 1 Voltage I O = -2mA VI 85% V DD 90% V DD V Logic 0 Voltage I O = +2mA VI 0.1 0.4 V CLK to Output Delay Time (t D )I V 4 8 1 2 n s Power Supply Requirements Supply Voltage (V DD1 , V DD2 , V DD3 )I V 2.8 3.3 3.6 V Supply Current (I DD )V I 2 4 3 0 m A Power Dissipation VI 79 100 mW Power Supply Rejection Ratio V 67 dB Parameter Min Max Units Supply Voltages V DD1 , V DD2 DD3 -0.5 +6 V Input Voltages Analog and Digital Input -0.5 V DD +0.5 V V REF+ , V REF– , CLK -0.5 V DD +0.5 V Operating Temperature Range -40 +85 °C Storage Temperature Range -65 +125 °C Parameter Conditions Test Level Min Typ Max Units Electrical Specifications T A = T MIN MAX , V DD1 = V DD2 = V DD3 = 3.3V, V REF– = 1.0V, V REF+ = 2.0V, Common Mode Voltage = 1.65V , ƒ CLK = 20 MSPS, Bias1 = 90 µ A, Bias2 = 9.5 µ A, Differential Input, Duty Cycle = 50%; unless otherwise noted)

REV. 1B October 2003 DATA SHEET SPT7851 Typical Performance Characteristics T A = T MIN MAX , V DD1 = V DD2 = V DD3 = 3.3V, V REF– = 1.0V, V REF+ = 2.0V, Common Mode Voltage = 1.65, ƒ CLK = 20 MSPS, Bias1 = 90 µ A, Bias2 = 9.5 µ A, Differential Input, Duty Cycle = 50%; unless otherwise noted) THD, SNR, SINAD vs. Temperature THD, SNR, SINAD (dB) Temperature ( °C) -40 -25 0 25 50 70 THD, SNR, SINAD vs. Input Frequency THD, SNR, SINAD (dB) Input Frequency (MHz) 100 102101 THDSNR SINAD THD, SNR, SINAD vs. Sample Rate THD, SNR, SINAD (dB) Sample Rate (MSPS) 100 102101 THD SINAD SNR NOTE: Bias1 and Bias2 currents optimized for each sample rate 150 100 125 Power Dissipation vs. Sample Rate Power Dissipation (mW) Sample Rate (MSPS) 100 102101 NOTE: Bias1 and Bias2 currents optimized for each sample rate THD SNR SINAD IBIAS1 (µA) 3.4VBias1 (V) 2.0 3.2 300 Bias1 Voltage vs. Bias1 Current 60 90 120 150 180 IBias1 VBias1 30 2.19 60 2.53 90 2.79 120 3 150 3.22 3.0 2.8 2.6 2.4 2.2 IBIAS2 (µA) 0.90VBias2 (V) 0.85 Bias2 Voltage vs. Bias2 Current 69 1 2 15 18 IBias2 VBias2 3 0.6975 6 0.7535 9 0.796 12 0.8295 15 0.85950.80 0.75 0.70 0.65 0.60

REV. 1B October 2003 7 SPT7851 DATA SHEET Clock The SPT7851 accepts a low voltage CMOS logic level at the CLK input. The duty cycle of the clock should be kept as close to 50% as possible. Because consecutive stages in the ADC are clocked in opposite phase to each other, a non-50% duty cycle reduces the settling time available for every other stage and thus could potentially cause a degradation of dynamic performance. For optimal performance at high input frequencies, the clock should have low jitter and fast edges. The rise/fall times should be kept shorter than 2ns. Overshoot and undershoot should be avoided. Clock jitter causes the noise floor to rise proportional to the input frequency. Because jitter can be caused by crosstalk on the PC board, it is recommended that the clock trace be kept as short as possible and standard transmission line practices be followed. Digital Outputs The digital output data appears in an offset binary code at 3.3V CMOS logic levels. A negative full scale input results in an all zeros output code (000…0). A positive full scale input results in an all 1’s code (111…1). The output data is available 7.5 clock cycles after the data is sampled. The input signal is sampled on the high to low transition of the input clock. Output data should be latched on the low to high clock transition as shown in figure 1, the Timing Diagram. The output data is invalid for the first 20 clock cycles after the device is powered up. Evaluation Board The EB7851 Evaluation Board is available to aid designers in demonstrating the full performance capability of the SPT7851. The board includes an on-board clock driver, adjustable voltage references, adjustable bias current circuits, single-to-differential input buffers with adjustable levels, a single-to-differential transformer (1:1), digital output buffers and 3.3/5 V adjustable logic outputs. An application note (AN7851) is also available which describes the operation of the evaluation board and provides an example of the recommended power and ground layout and signal routing. Contact the factory for price and availability. Pin Configuration N/C N/C N/C N/C Bias 1 Bias 2 VCM GND VIN+ VIN– GND VDD3 D0 (LSB) D9 (MSB) GND CLK N/C VDD3 VDD2 VDD2 VDD1 VDD1 VDD1 VREF– VREF+ DNC DNC GND GND GND GND GND GND GND GND GND Pin Assignments Pin Name Description VIN+, VIN– Analog Inputs VREF+, VREF– External Reference Inputs CLK Input Clock VCM Common Mode Output Voltage (1.65V typ) Bias1 Bias Current (90 µA typ) Bias2 Bias Current (9.5 µA typ) D0 – D9 Digital Outputs (D0 = LSB) GND Analog Ground V DD1 Analog Power Supply VDD2 Digital Power Supply VDD3 Digital Output Power Supply N/C No connect DNC Do not connect pins; leave floating

8 REV. 1B October 2003 DATA SHEET SPT7851 Package Dimensions TQFP-44 Symbol Inches Millimeters Min Max Min Max A 0.472 Typ 12.00 Typ B 0.394 Typ 10.00 Typ C 0.394 Typ 10.00 Typ D 0.472 Typ 12.00 Typ E 0.031 Typ 0.80 Typ F 0.012 0.018 0.300 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.018 0.030 0.450 0.750 J 0.039 Typ 1.00 Typ K 0-7° 0-7° Index A B C D Pin 1 E F G H I J K

Ordering Information

Temperature range for all parts: -40°C to +85°C . Model Part Number Package Container Pack Qty SPT7851 SPT7851SIT 44-pin TQFP Tray -