SPT7835SIS

SPT7835 CADEKA | Alldatasheet

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Technical content

10-BIT, 5 MSPS, 75 mW A/D CONVER TER TECHNICAL D ATA JUNE 27, 2001 FEA TURES

• Monolithic 5 MSPS converter 75 mW pow er dissipation O n-chip track-and-hold Single +5 V pow er supply TTL/CMOS outputs 5 pF input capacitance Low cost Tri-state output buffers H igh ESD protection: 3,500 V minimum Selectable +3 V or +5 V logic I/O APPLICA TIONS All high-speed applications where low pow er dissipation is required Video imaging Medical imaging IR imaging Scanners Digital communications GENERAL DESCRIPTION The SPT7835 is a 10-bit monolithic, low-cost, ultralow- pow er analog-to-digital converter capable of minimum w ord rates of 5 MSPS. The on-chip track-and-hold func- tion assures very good dynamic performance without the need for external components. The input drive require- ments are minimized due to the SPT7835’s low input capacitance of only 5 pF. Pow er dissipation is extremely low at only 75 mW typical at 5 MSPS with a power supply of +5.0 V. The digital out- puts are +3 V or +5 V, and are user selectable. The SPT7835 is pin-compatible with an entire family of 10-bit, CMOS con verters (SPT7835/40/50/55/60/61), which sim- plifies upgrades. The SPT7835 has incorporated propri- etary circuit design* and CMOS processing technologies to achieve its advanced perform ance. Inputs and outputs are TTL/CMOS-compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7835 is available in a 28-lead SOIC package over the industrial temperature range, and a 32-lead small (7 mm square) TQFP pac kage over the commercial temperature range. *Patent pending BLOCK DIA GRAM /MT49/MT49/MT45/MT66/MT105/MT116 /MT83/MT65/MT82 /MT68/MT65/MT67 /MT65/MT68/MT67/MT32/MT83/MT101/MT99/MT116/MT105/MT111/MT110/MT32/MT49 /MT84/MT47/MT72 /MT49/MT49 /MT49/MT49/MT45/MT66/MT105/MT116 /MT83/MT65/MT82 /MT68/MT65/MT67 /MT65/MT68/MT67/MT32/MT83/MT101/MT99/MT116/MT105/MT111/MT110/MT32/MT56 /MT65/MT117/MT116/MT111/MT45 /MT90/MT101/MT114/MT111 /MT67/MT77/MT80 /MT65/MT117/MT116/MT111/MT45 /MT90/MT101/MT114/MT111 /MT67/MT77/MT80 /MT84/MT47/MT72 /MT49/MT49 /MT86/MT82/MT69/MT70 /MT49/MT58/MT56 /MT77/MT117/MT120 /MT49/MT49 /MT49/MT49 /MT49/MT49 /MT49/MT49 /MT49/MT49/MT45/MT66/MT105/MT116 /MT56/MT58/MT49 /MT77/MT117/MT120/MT47 /MT69/MT114/MT114/MT111/MT114 /MT67/MT111/MT114/MT114/MT101/MT99/MT116/MT105/MT111/MT110 /MT84/MT105/MT109/MT105/MT110/MT103 /MT97/MT110/MT100 /MT67/MT111/MT110/MT116/MT114/MT111/MT108 /MT80/MT49 /MT80/MT50 /MT80/MT55 /MT80/MT56 /MT65/MT68/MT67/MT32/MT83/MT101/MT99/MT116/MT105/MT111/MT110/MT32/MT50 /MT65/MT68/MT67/MT32/MT83/MT101/MT99/MT116/MT105/MT111/MT110/MT32/MT55 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101/MT32/MT76/MT97/MT100/MT100/MT101/MT114/MT82/MT101/MT102 /MT73/MT110 /MT69/MT110/MT97/MT98/MT108/MT101 /MT67/MT76/MT75/MT32/MT73/MT110 /MT68/MT97/MT116/MT97 /MT86/MT97/MT108/MT105/MT100 /MT65/MT73/MT78 /MT68/MT49/MT48/MT32/MT79/MT118/MT101/MT114/MT114/MT97/MT110/MT103/MT101 /MT68/MT57/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT56 /MT68/MT55 /MT68/MT54 /MT68/MT53 /MT68/MT52 /MT68/MT51 /MT68/MT50 /MT68/MT49 /MT68/MT48/MT32/MT40/MT76/MT83/MT66/MT41 /MT46/MT46/MT46 /MT46/MT46/MT46 /MT46/MT46/MT46 /MT46/MT46/MT46

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX , AVDD =DV DD =OV DD =+5.0 V, VIN=0 to 4 V, ƒCLK =10 MHz, ƒS=5 MSPS, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified. TEST TEST SPT7835 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 10 Bits DC Accuracy Integral Linearity Error (ILE) VI ±1.0 LSB Differential Linearity Error (DLE) VI ±0.5 LSB No Missing Codes VI Guaranteed Analog Input Input Voltage Range VI V RLS VRHS V Input Resistance IV 50 k Ω Input Capacitance V 5.0 pF Input Bandwidth (Small Signal) V 100 MHz Offset V ±2.0 LSB Gain Error V ±2.0 LSB Reference Input Resistance VI 400 500 600 Ω Bandwidth V 100 150 MHz Voltage Range V RLS IV 0 2.0 V VRHS IV 3.0 AV DD V VRHS – VRLS V 1.0 4.0 5.0 V ∆(VRHF – VRHS )V 9 0 m V ∆(VRLS – VRLF )V 7 5 m V Reference Settling Time VRHS V 15 Clock Cycles VRLS V 20 Clock Cycles Conversion Characteristics Maximum Conversion Rate VI 5 MHz Minimum Conversion Rate IV 2 MHz Pipeline Delay (Latency) IV 12 Clock Cycles Aperture Delay Time V 5 ns Aperture Jitter Time V 10 ps (p-p) Dynamic Performance Effective Number of Bits (ENOB) ƒIN = 1 MHz VI 9.2 Bits Signal-to-Noise Ratio (SNR) (without Harmonics) ƒIN = 1 MHz VI 54 59 dB Supply Voltages Input Voltages Output Temperature

All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX , AVDD =DV DD =OV DD =+5.0 V, VIN=0 to 4 V, ƒCLK =10 MHz, ƒS=5 MSPS, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified. TEST TEST SPT7835 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Dynamic Performance Total Harmonic Distortion (THD) ƒIN = 1 MHz VI 59 63 dB Signal-to-Noise and Distortion (SINAD) ƒIN = 1 MHz VI 52 57 dB Spurious Free Dynamic Range V 63 dB Digital Inputs Logic 1 Voltage VI 2.0 V Logic 0 Voltage VI 0.8 V Maximum Input Current Low VI –10 +10 µA Maximum Input Current High VI –10 +10 µA Input Capacitance V 5 pF Digital Outputs Logic 1 Voltage I OH = 0.5 mA VI 3.5 V Logic 0 Voltage I OL = 1.6 mA VI 0.4 V tRISE 15 pF load V 10 ns tFALL 15 pF load V 10 ns Output Enable to Data Output Delay 20 pF load, TA = +25 °CV 1 0 n s 50 pF load over temp. V 22 ns Power Supply Requirements Voltages OV DD IV 3.0 5.0 V DV DD IV 4.75 5.0 5.25 V AV DD IV 4.75 5.0 5.25 V Currents AI DD VI 9 12 mA DIDD VI 6 10 mA Power Dissipation ƒIN = 1 MHz VI 75 110 mW

Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. APERTURE JITTER The variations in aperture delay for successive samples. DIFFERENTIAL GAIN (DG) A signal consisting of a sine wave superimposed on vari- ous DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. DIFFERENTIAL PHASE (DP) A signal consisting of a sine wave superimposed on vari- ous DC levels is applied to the input. Differential phase is the maximum variation in the sampled sine wave phases at these DC levels. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. INTEGRAL LINEARITY ERROR (ILE) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from –FS through +FS. The deviation is measured from the edge of each particular code to the true straight line. OUTPUT DELAY Time between the clock’s triggering edge and output data valid. OVERVOLTAGE RECOVERY TIME The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise and distortion power. TOTAL HARMONIC DISTORTION (THD) The ratio of the total power of the first 9 harmonics to the power of the measured sinusoidal signal. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal. INPUT BANDWIDTH Small signal (50 mV) bandwidth (3 dB) of analog input stage. DIFFERENTIAL LINEARITY ERROR (DLE) Error in the width of each code from its theoretical value. (Theoretical = V FS /2N ) N = SINAD – 1.76 6.02 SPECIFICATION DEFINITIONS

TYPICAL PERFORMANCE CHARACTERISTICS /MT83/MT78/MT82/MT32/MT118/MT115/MT32/MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121 /MT49/MT48/MT150/MT49 /MT49/MT48/MT48 /MT51/MT48 /MT52/MT48 /MT53/MT48 /MT54/MT48 /MT55/MT48 /MT50/MT48 /MT56/MT48 /MT131/MT83/MT32/MT61/MT32/MT53/MT32/MT77/MT83/MT80/MT83 /MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT83/MT105/MT103/MT110/MT97/MT108/MT45/MT116/MT111/MT45/MT78/MT111/MT105/MT115/MT101/MT32/MT82/MT97/MT116/MT105/MT111/MT32/MT40/MT100/MT66/MT41 /MT84/MT72/MT68/MT32/MT118/MT115/MT32/MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121 /MT49/MT48/MT150/MT49 /MT49/MT48/MT48 /MT51/MT48 /MT52/MT48 /MT53/MT48 /MT54/MT48 /MT55/MT48 /MT50/MT48 /MT56/MT48 /MT131/MT83/MT32/MT61/MT32/MT53/MT32/MT77/MT83/MT80/MT83 /MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT84/MT111/MT116/MT97/MT108/MT32/MT72/MT97/MT114/MT109/MT111/MT110/MT105/MT99/MT32/MT68/MT105/MT115/MT116/MT111/MT114/MT116/MT105/MT111/MT110/MT32/MT40/MT100/MT66/MT41 /MT83/MT73/MT78/MT65/MT68/MT32/MT118/MT115/MT32/MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121 /MT49/MT48/MT150/MT49 /MT49/MT48/MT48 /MT51/MT48 /MT52/MT48 /MT53/MT48 /MT54/MT48 /MT55/MT48 /MT50/MT48 /MT56/MT48 /MT131/MT83/MT32/MT61/MT32/MT53/MT32/MT77/MT83/MT80/MT83 /MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT83/MT105/MT103/MT110/MT97/MT108/MT45/MT116/MT111/MT45/MT78/MT111/MT105/MT115/MT101/MT32/MT97/MT110/MT100/MT32/MT68/MT105/MT115/MT116/MT111/MT114/MT116/MT105/MT111/MT110/MT32/MT40/MT100/MT66/MT41 /MT53/MT48 /MT49/MT49/MT48 /MT57/MT48 /MT55/MT48 /MT53/MT48 /MT51/MT48 /MT49/MT48 /MT84/MT111/MT116/MT97/MT108/MT32/MT80/MT111/MT119/MT101/MT114/MT32/MT68/MT105/MT115/MT115/MT105/MT112/MT97/MT116/MT105/MT111/MT110/MT32/MT118/MT115/MT32/MT83/MT97/MT109/MT112/MT108/MT101/MT32/MT82/MT97/MT116/MT101 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101/MT32/MT105/MT115/MT32/MT101/MT120/MT99/MT108/MT117/MT100/MT101/MT100/MT32/MT61/MT32/MT51/MT48/MT32/MT109/MT87/MT32/MT84/MT121/MT112 /MT83/MT97/MT109/MT112/MT108/MT101/MT32/MT82/MT97/MT116/MT101/MT32/MT40/MT67/MT76/MT75/MT47/MT50/MT41/MT32/MT77/MT72/MT122 /MT80/MT111/MT119/MT101/MT114/MT32/MT68/MT105/MT115/MT115/MT105/MT112/MT97/MT116/MT105/MT111/MT110/MT32/MT40/MT109/MT87/MT41

TYPICAL INTERF ACE CIRCUIT Very few external components are required to achieve the stated device performance . Figure 2 shows the typical in- terface requirements when using the SPT7835 in normal circuit operation. The following sections provide descrip- tions of the major functions and outline critical perfor- mance criteria to consider for achieving the optimal device performance . PO WER SUPPLIES AND GR OUNDING ply voltages on the SPT7835 be derived from a single ana- log supply as shown in figure 2. A separate digital supply using this pow er supply configuration to prevent a possible latch-up condition on pow erup. OPERA TING DESCRIPTION The general architecture for the CMOS ADC is shown in the block diagram. The design contains eight identical successive approximation ADC sections, all operating in parallel, a 16-phase clock generator, an 11-bit 8:1 digital output multiplexer, correction logic, and a voltage refer- ence generator that provides common reference levels for each ADC section. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as shown in table II. /MT86/MT82/MT72/MT70 /MT86/MT82/MT76/MT83 /MT86/MT82/MT76/MT70 /MT86/MT82/MT72/MT83 /MT86/MT73/MT78 /MT67/MT76/MT75 /MT86/MT67/MT65/MT76 /MT68/MT65/MT86 /MT68/MT49/MT48 /MT68/MT49 /MT69/MT78 /MT65/MT86/MT68/MT68/MT65/MT71/MT78/MT68/MT68/MT71/MT78/MT68/MT42/MT68/MT86/MT68/MT68 /MT82/MT101/MT102/MT32/MT73/MT110 /MT40/MT43/MT52/MT32/MT86/MT41 /MT86/MT73/MT78 /MT67/MT76/MT75/MT32/MT73/MT78 /MT69/MT110/MT97/MT98/MT108/MT101/MT47/MT84/MT114/MT105/MT45/MT83/MT116/MT97/MT116/MT101 /MT40/MT69/MT110/MT97/MT98/MT108/MT101/MT32/MT61/MT32/MT65/MT99/MT116/MT105/MT118/MT101/MT32/MT76/MT111/MT119/MT41 /MT73/MT110/MT116/MT101/MT114/MT102/MT97/MT99/MT105/MT110/MT103 /MT76/MT111/MT103/MT105/MT99/MT115 /MT83/MT80/MT84/MT55/MT56/MT51/MT53 /MT68/MT71/MT78/MT68 /MT43 /MT49/MT48/MT32/MT181/MT70 /MT43/MT53/MT32/MT86 /MT68/MT105/MT103/MT105/MT116/MT97/MT108 /MT43/MT53/MT32/MT86 /MT68/MT105/MT103/MT105/MT116/MT97/MT108 /MT82/MT84/MT78 /MT51/MT46/MT51/MT47/MT53 /MT76/MT49 /MT78/MT79/MT84/MT69/MT83/MT58/MT49/MT41/MT76/MT49/MT32/MT105/MT115/MT32/MT116/MT111/MT32/MT98/MT101/MT32/MT108/MT111/MT99/MT97/MT116/MT101/MT100/MT32/MT97/MT115/MT32/MT99/MT108/MT111/MT115/MT101/MT108/MT121/MT32/MT116/MT111/MT32/MT116/MT104/MT101/MT32/MT100/MT101/MT118/MT105/MT99/MT101/MT32/MT97/MT115/MT32/MT112/MT111/MT115/MT115/MT105/MT98/MT108/MT101/MT46 /MT50/MT41/MT65/MT108/MT108/MT32/MT99/MT97/MT112/MT97/MT99/MT105/MT116/MT111/MT114/MT115/MT32/MT97/MT114/MT101/MT32/MT48/MT46/MT49/MT32/MT181/MT70/MT32/MT115/MT117/MT114/MT102/MT97/MT99/MT101/MT45/MT109/MT111/MT117/MT110/MT116/MT32/MT117/MT110/MT108/MT101/MT115/MT115/MT32/MT111/MT116/MT104/MT101/MT114/MT119/MT105/MT115/MT101/MT32/MT115/MT112/MT101/MT99/MT105/MT102/MT105/MT101/MT100/MT46 /MT51/MT41/MT76/MT49/MT32/MT105/MT115/MT32/MT97/MT32/MT49/MT48/MT32/MT181/MT72/MT32/MT105/MT110/MT100/MT117/MT99/MT116/MT111/MT114/MT32/MT111/MT114/MT32/MT97/MT32/MT102/MT101/MT114/MT114/MT105/MT116/MT101/MT32/MT98/MT101/MT97/MT100/MT46 /MT43/MT65/MT53 /MT65/MT71/MT78/MT68 /MT43 /MT49/MT48/MT32/MT181/MT70 /MT43/MT53/MT32/MT86 /MT65/MT110/MT97/MT108/MT111/MT103 /MT43/MT53/MT32/MT86 /MT65/MT110/MT97/MT108/MT111/MT103 /MT82/MT84/MT78 /MT43/MT65/MT53 /MT42/MT84/MT111/MT32/MT114/MT101/MT100/MT117/MT99/MT101/MT32/MT116/MT104/MT101/MT32/MT112/MT111/MT115/MT115/MT105/MT98/MT105/MT108/MT105/MT116/MT121/MT32/MT111/MT102/MT32/MT108/MT97/MT116/MT99/MT104/MT45/MT117/MT112/MT44/MT32/MT97/MT118/MT111/MT105/MT100 /MT99/MT111/MT110/MT110/MT101/MT99/MT116/MT105/MT110/MT103/MT32/MT116/MT104/MT101/MT32/MT68/MT71/MT78/MT68/MT32/MT112/MT105/MT110/MT115/MT32/MT111/MT102/MT32/MT116/MT104/MT101/MT32/MT65/MT68/MT67/MT32/MT116/MT111/MT32/MT116/MT104/MT101 /MT100/MT105/MT103/MT105/MT116/MT97/MT108/MT32/MT103/MT114/MT111/MT117/MT110/MT100/MT32/MT111/MT102/MT32/MT116/MT104/MT101/MT32/MT115/MT121/MT115/MT116/MT101/MT109/MT46 /MT51/MT46/MT51/MT47/MT53 /MT51/MT46/MT51/MT47/MT53 /MT68/MT57 /MT68/MT56 /MT68/MT55 /MT68/MT54 /MT68/MT53 /MT68/MT52 /MT68/MT51 /MT68/MT50 /MT68/MT48 /MT79/MT86/MT68/MT68 /MT79/MT71/MT78/MT68 Figure 2 – Typical Interface Circuit CADEKA suggests that both the digital and the analog sup- should be used for all interface circuitry. CADEKA suggests

Table II – Clock Cycles Clock Operation

1 Reference zero sampling

2 Auto-zero comparison

3 Auto-calibrate comparison

4 Input sample

5-15 11-bit SAR conversion

16 Data transfer

The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by two clock cycles so that the analog input is sampled on every other cycle of the input clock by exactly one ADC section. After 16 clock periods, the timing cycle repeats. The sample rate for the configu- ration is one-half of the clock rate; e.g., for a 10 MHz clock rate, the input sample rate is 5 MHz. The latency from analog input sample to the corresponding digital output is 12 clock cycles.  Since only eight comparators are used, a huge power savings is realized.  The auto-zero operation is done using a closed loop system that uses multiple samples of the comparators’ response to a reference zero.  The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration volt- age for each ADC section.  Capacitive displacement currents, which can induce sampling error, are minimized since only one compara- tor samples the input during a clock cycle.  The total input capacitance is very low since sections of the converter that are not sampling the signal are iso- lated from the input by transmission gates. VOLTAGE REFERENCE The SPT7835 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input volt- age range will track the total voltage difference measured between the ladder sense lines, V RHS and VRLS . Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than ±2 LSB can be obtained. In cases where wider variations in offset and gain can be tolerated, V REF can be tied directly to VRHF , and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a .01 µF capacitor (chip cap preferred) to minimize high-frequency noise in- jection. If this simplified configuration is used, the following considerations should be taken into account. The reference ladder circuit shown in figure 4 is a simpli- fied representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from V RHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS . Figure 3 – Ladder Force/Sense Circuit /MT65/MT71/MT78/MT68 /MT86/MT82/MT72/MT70 /MT86/MT82/MT72/MT83 /MT86/MT82/MT76/MT83 /MT86/MT82/MT76/MT70 /MT86/MT73/MT78 /MT43 /MT150 /MT65/MT108/MT108/MT32/MT99/MT97/MT112/MT97/MT99/MT105/MT116/MT111/MT114/MT115/MT32/MT97/MT114/MT101/MT32/MT48/MT46/MT48/MT49/MT32/MT181/MT70 /MT43 /MT150 Figure 4 – Reference Ladder /MT82/MT47/MT50 /MT82 /MT82 /MT82 /MT82 /MT82 /MT82 /MT82/MT47/MT50 /MT82/MT61/MT51/MT48/MT32/MT87/MT32/MT40/MT116/MT121/MT112/MT41 /MT65/MT108/MT108/MT32/MT99/MT97/MT112/MT97/MT99/MT105/MT116/MT111/MT114/MT115/MT32/MT97/MT114/MT101/MT32/MT48/MT46/MT48/MT49/MT32/MT181/MT70 /MT86/MT82/MT76/MT70 /MT40/MT65/MT71/MT78/MT68/MT41 /MT48/MT46/MT48/MT32/MT86 /MT86/MT82/MT76/MT83 /MT40/MT48/MT46/MT48/MT55/MT53/MT32/MT86/MT41 /MT86/MT82/MT72/MT83 /MT40/MT43/MT51/MT46/MT57/MT49/MT32/MT86/MT41 /MT43/MT52/MT46/MT48/MT32/MT86 /MT69/MT120/MT116/MT101/MT114/MT110/MT97/MT108 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101 /MT55/MT53/MT32/MT109/MT86 /MT57/MT48/MT32/MT109/MT86

The digital outputs (D0–D10) are driven by a separate supply (OVDD ) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7835’s TTL/CMOS- compatible outputs with the user’s logic system supply. The format of the output data (D0–D9) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing EN high. Table III – Output Data Information ANALOG INPUT OVERRANGE OUTPUT CODE D10 D9 –D0 +F .S. + 1/2 LSB 1 1 1 1 1 1 1 1 1 1 1 +F .S. –1/2 LSB 0 1 1 1 1 1 1 1 1 1 Ø +1/2 F .S. 0 ØØ ØØØØ ØØØØ +1/2 LSB 0 0 0 0 0 0 0 0 0 0 Ø

0.0 V 0 0 0 0 0 0 0 0 0 0 0

(Ø indicates the flickering bit between logic 0 and 1.) OVERRANGE OUTPUT The OVERRANGE OUTPUT (D10) is an indication that the analog input signal has exceeded the positive full- scale input voltage by 1 LSB. When this condition occurs, D10 will switch to logic 1. All other data outputs (D0 to D9) will remain at logic 1 as long as D10 remains at logic 1. This feature makes it possible to include the SPT7835 in higher resolution systems. EVALUATION BOARD The EB7835 evaluation board is available to aid designers in demonstrating the full performance of the SPT7835. This board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction of the digital data. An application note describing the operation of this board, as well as information on the testing of the SPT7835, is also available. Contact the factory for price and availability.

A 0.346 0.362 8.80 9.20 B 0.272 0.280 6.90 7.10 C 0.346 0.362 8.80 9.20 D 0.272 0.280 6.90 7.10 E 0.031 typ 0.80 BSC F 0.012 0.016 0.30 0.40 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.037 0.041 0.95 1.05 J 0.007 0.17 K0 ° 7° 0° 7° L 0.020 0.030 0.50 0.75 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.699 0.709 17.75 18.01 B 0.005 0.011 0.13 0.28 C 0.050 typ 1.27 typ D 0.018 typ 0.46 typ E 0.0077 0.0083 0.20 0.21 F 0.090 0.096 2.29 2.44 G 0.031 0.039 0.79 0.99 H 0.396 0.416 10.06 10.57 I 0.286 0.292 7.26 7.42 /MT65 /MT66 /MT67/MT68 /MT69 /MT70 /MT74 /MT75 /MT76 /MT71/MT72 /MT73 A B CD E F G I H H

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT7835SIS –40 to +85 °C 28L SOIC SPT7835SCT 0 to +70 °C 32L TQFP PIN FUNCTIONS Name Function AG N D Analog Ground VRHF Reference High Force VRHS Reference High Sense VRLS Reference Low Sense VRLF Reference Low Force VCAL Calibration Reference VIN Analog Input AV DD Analog VDD DV DD Digital VDD DGND Digital Ground CLK Input Clock ƒCLK = FS (TTL) EN Output Enable D0 –9 Tri-State Data Output, (D0=LSB) D10 Tri-State Output Overrange DAV Data Valid Output OV DD Digital Output Supply OGND D igital Output Ground N /C No Connect PIN ASSIGNMENTS /MT65/MT71/MT78/MT68 /MT86/MT82/MT72/MT70 /MT86/MT82/MT72/MT83 /MT78/MT47/MT67 /MT86/MT82/MT76/MT83 /MT86/MT82/MT76/MT70 /MT86/MT73/MT78 /MT65/MT71/MT78/MT68 /MT86/MT67/MT65/MT76 /MT65/MT86/MT68/MT68 /MT68/MT86/MT68/MT68 /MT68/MT71/MT78/MT68 /MT67/MT76/MT75 /MT68/MT65/MT86 /MT49 /MT50 /MT51 /MT52 /MT53 /MT54 /MT55 /MT56 /MT57 /MT49/MT48 /MT49/MT49 /MT49/MT50 /MT49/MT51 /MT49/MT52 /MT50/MT56 /MT50/MT55 /MT50/MT54 /MT50/MT53 /MT50/MT52 /MT50/MT51 /MT50/MT50 /MT50/MT49 /MT50/MT48 /MT49/MT57 /MT49/MT56 /MT49/MT55 /MT49/MT54 /MT49/MT53 /MT79/MT71/MT78/MT68 /MT68/MT53 /MT68/MT49 /MT68/MT51 /MT68/MT50 /MT68/MT48 /MT68/MT52 /MT79/MT86/MT68/MT68 /MT68/MT54 /MT68/MT55 /MT68/MT56 /MT68/MT57 /MT68/MT49/MT48 /MT69/MT78 /MT83/MT79/MT73/MT67 /MT50 /MT49 /MT51 /MT52 /MT53 /MT54 /MT55 /MT56 /MT50/MT51 /MT50/MT52 /MT50/MT50 /MT50/MT49 /MT50/MT48 /MT49/MT57 /MT49/MT56 /MT49/MT55 /MT50/MT54 /MT50/MT53 /MT50/MT55 /MT50/MT56 /MT50/MT57 /MT51/MT48 /MT51/MT49 /MT51/MT50 /MT49/MT53 /MT49/MT54 /MT49/MT52 /MT49/MT51 /MT49/MT50 /MT49/MT49 /MT49/MT48 /MT57 /MT86/MT82/MT76/MT70 /MT86/MT73/MT78 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT86/MT67/MT65/MT76 /MT65/MT86/MT68/MT68 /MT68/MT55 /MT68/MT54 /MT68/MT53 /MT79/MT71/MT78/MT68 /MT68/MT52 /MT68/MT51 /MT68/MT50 /MT68/MT49 /MT68/MT48 /MT68/MT65/MT86 /MT67/MT76/MT75 /MT68/MT71/MT78/MT68 /MT68/MT71/MT78/MT68 /MT68/MT56 /MT68/MT57 /MT68/MT49/MT48 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT86/MT82/MT72/MT70 /MT86/MT82/MT72/MT83 /MT86/MT82/MT76/MT83 /MT69/MT78 /MT65/MT86/MT68/MT68 /MT68/MT86/MT68/MT68 /MT79/MT86/MT68/MT68 /MT68/MT86/MT68/MT68 /MT84/MT81/MT70/MT80