SPT7820 CADEKA | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 11
Technical content
10-BIT, 20 MSPS, TTL OUTPUT , A/D CONVERTER
FEATURES
- Monolithic 20 MSPS Converter
- On-Chip Track/Hold
- Bipolar ±2.0 V Analog Input
- 60 dB SNR @ 1 MHz Input
- Low Power (1.0 W Typical)
- 5 pF Input Capacitance
- TTL Outputs
APPLICATIONS
- Medical Imaging
- Professional Video
- Radar Receivers
- Instrumentation
- Electronic Warfare
- Digital Communications Analog Prescaler Digital Output Successive Interpolation Stage i Successive Interpolation Stage i+1 Successive Interpolation Stage N Analog Input 4Coarse A/D T/H Amplifier Bank /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Decoding Network GENERAL DESCRIPTION The SPT7820 A/D converter is a 10-bit monolithic converter capable of word rates of a minimum of 20 MSPS. On board track/hold function assures excellent dynamic performance without the need for external components. Drive require- ment problems are minimized with an input capacitance of only 5 pF. Inputs and outputs are TTL compatible to interface with TTL logic systems. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.0 watt with power supply voltages of +5.0 and -5.2 volts. The SPT7820 also provides a wide input voltage swing of ±2.0 volts. The SPT7820 is available in 28-lead ceramic sidebrazed DIP, PDIP and SOIC packages over the commercial, industrial and military temperature ranges. Contact the factory for availability of die and /883 versions. BLOCK DIAGRAM
specified. TEST TEST SPT7820A SPT7820B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Resolution 10 10 Bits DC Accuracy (+25 °C) ±Full Scale Integral Nonlinearity 100 kHz Sample Rate V ±1.0 ±1.5 LSB Differential Nonlinearity V ±0.5 ±0.75 LSB No Missing Codes VI Guaranteed Guaranteed Analog Input fCLK =1 MHz Input Voltage Range V ±2.0 ±2.0 V Input Bias Current V IN=0 V VI 30 60 30 60 µA Input Bias Current T A=-55 to +125 °CI V 7 5 7 5 µA Input Resistance VI 100 300 100 300 k Ω Input Resistance T A=-55 to +125 °C IV 75 300 75 300 k Ω Input Capacitance V 5 5 pF Input Bandwidth 3 dB Small Signal V 120 120 MHz +FS Error V ±2.0 ±2.0 LSB -FS Error V ±2.0 ±2.0 LSB Reference Input fCLK =1 MHz Reference Ladder Resistance VI 500 800 500 800 Ω Reference Ladder Tempco V 0.8 0.8 Ω /°C Timing Characteristics Maximum Conversion Rate VI 20 20 MHz Overvoltage Recovery Time V 20 20 ns Pipeline Delay (Latency) IV 1 1 Clock Cycle Output Delay T A=+25 °C V 14 18 14 18 ns Aperture Delay Time T A=+25 °CV 1 1 n s Aperture Jitter Time T A=+25 °C V 5 5 ps-RMS Acquisition Time T A=+25 °C V 20 20 ns Dynamic Performance Effective Number of Bits fIN=1 MHz 9.2 8.7 Bits fIN=3.58 MHz 8.8 8.3 Bits fIN=10.0 MHz 7.5 7.0 Bits ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Supply Voltages Input Voltages CC Output Temperature Typical thermal impedances (unsoldered, in free air): 28L sidebrazed DIP: θja = 50 °C/W, 28L plastic DIP: θja = 50 °C/W, 28L SOIC: θja = 100 °C/W.
specified. TEST TEST SPT7820A SPT7820B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Dynamic Performance Signal-To-Noise Ratio (Without Harmonics) fIN=1 MHz T A=+25 °C I 57 60 54 57 dB TA=0-70, -25 to +85 °CI V 5 5 5 8 5 2 5 5 d B TA=-55 to +125 °C * IV 52 55 49 52 dB fIN=3.58 MHz T A=+25 °C I 56 58 53 55 dB TA=0-70, -25 to +85 °CI V 5 4 5 6 5 1 5 3 d B TA=-55 to +125 °C * IV 52 54 49 51 dB fIN=10.0 MHz T A=+25 °C I 50 53 47 49 dB TA=0-70, -25 to +85 °CI V 4 7 5 0 4 4 4 6 d B TA=-55 to +125 °C * IV 43 46 40 42 dB Harmonic Distortion fIN=1 MHz T A=+25 °C I 57 60 54 57 dB TA=0-70, -25 to +85 °CI V 5 4 5 7 5 1 5 4 d B TA=-55 to +125 °C * IV 50 53 47 50 dB fIN=3.58 MHz T A=+25 °C I 56 58 53 55 dB TA=0-70, -25 to +85 °CI V 5 3 5 5 5 0 5 2 d B TA=-55 to +125 °C * IV 50 52 47 49 dB fIN=10.0 MHz T A=+25 °C I 46 48 43 45 dB TA=0-70, -25 to +85 °)I V 4 5 4 7 4 2 4 4 d B TA=-55 to +125 °C * IV 45 47 42 44 dB Signal-to-Noise and Distortion fIN=1 MHz T A=+25 °C I 55 57 52 54 dB TA=0-70, -25 to +85 °CI V 5 2 4 9 d B TA=-55 to +125 °C * IV 48 45 dB fIN=3.58 MHz T A=+25 °C I 54 55 51 52 dB TA=0-70, -25 to +85 °CI V 5 1 4 8 d B TA=-55 to +125 °C * IV 48 45 dB fIN=10.0 MHz T A=+25 °C I 44 47 41 44 dB TA=0-70, -25 to +85 °CI V 4 3 4 0 d B TA=-55 to +125 °C * IV 41 38 dB Spurious Free Dynamic Range TA=+25 °C, fIN=1 MHz V 67 67 dB Differential Phase TA=+25 °C, fIN=3.58 & 4.35 MHz V 0.2 0.2 Degree Differential Gain TA=+25 °C, fIN=3.58 & 4.35 MHz V 0.5 0.7 % Digital Inputs f CLK =1 MHz Logic 1 Voltage VI 2.4 4.5 2.4 4.5 V Logic 0 Voltage VI 0.8 0.8 V Maximum Input Current Low T A=+25 °C I 0 +5 +20 0 +5 +20 µA Maximum Input Current High TA=+25 °C I 0 +5 +20 0 +5 +20 µA Pulse Width Low (CLK) IV 20 20 ns Pulse Width High (CLK) IV 20 300 20 300 ns Digital Outputs f CLK =1 MHz Logic 1 Voltage VI 2.4 2.4 V Logic 0 Voltage VI 0.6 0.6 V Power Supply Requirements Voltages VCC IV 4.75 5.25 4.75 5.25 V Currents ICC TA=+25 °C I 118 145 118 145 mA DICC TA=+25 °C I 40 55 40 55 mA -IEE TA=+25 °C I 40 57 40 57 mA Power Dissipation T A=+25 °C I 1.0 1.3 1.0 1.3 W *Temperature tested /883 only.
TYPICAL PERFORMANCE CHARACTERISTICS 100 101 102 THD vs Input Frequency Input Frequency (MHz) Total Harmonic Distortion (dB) fs = 20 MSPS Input Frequency (MHz) Signal-to-Noise Ratio (dB) SNR vs Input Frequency 100 101 102 fs = 20 MSPS /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 100 101 102 SNR, THD, SINAD vs Sample Rate Sample Rate (MSPS) SNR, THD, SINAD (dB) SNR, THD fIN = 1 MHz SINAD Signal-to-Noise and Distortion (dB) 100 101 10 SINAD vs Input Frequency Input Frequency (MHz) fs =20 MSPS -120 -90 -60 -30 Input Frequency (MHz) Amplitude (dB) Spectral Response 0 123456789 1 0 fS = 20 MSPS fIN = 1 MHz SNR, THD, SINAD vs Temperature Temperature (°C) SNR, THD, SINAD (dB) fS = 20 MSPS fIN = 1 MHz SINAD SNR -25 0 +25 +50 +75 SNR THDTHD
The SPT7820 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7820 in normal circuit operation. The following section provides a description of the pin functions and outlines critical perfor- mance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7820 requires -5.2 V and +5 V analog supply voltages. The +5 V supply is common to analog V CC and digital DVCC . A ferrite bead in series with each supply line is intended to reduce the transient noise injected into the analog V CC . These beads should be connected as closely as possible to the device. The connection between the beads and the SPT7820 should not be shared with any other device. Each power supply pin should be bypassed as closely as possible to the device. Use 0.1 µF for V EE and VCC , and 0.01 µF for DVCC (chip caps are preferred). AGND and DGND are the two grounds available on the SPT7820. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVCC return path (40 mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be sepa- rated from each other and connected together only at the device through a ferrite bead. A Schottky or hot carrier diode connected between AGND and V EE is required. The use of separate power supplies between VCC and DVCC is not recommended due to potential power supply sequencing latch-up conditions. Using the recommended interface circuit shown in figure 2 will provide optimum device performance for the SPT7820. VOLTAGE REFERENCE The SPT7820 requires the use of two voltage references: V FT and VFB . VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 Ω . The +2.5 V voltage source for reference V FT must be current limited to 20 mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. In addition, there are three reference Figure 2 - Typical Interface Circuit D10 (Overrange) D9 (MSB) D0 (LSB) D I G I T A L O U - 5.2 V COARSE A/D ANALOG PRESCALER SUCCESSIVE INTERPOLATION STAGE # 1 SUCCESSIVE INTERPOLATION STAGE # N D E C O D I N G N E T W O R K IC1 (REF-03) + 5 V VOUT Tr imGND VIN 1 µF .01 µF 10 kΩ 10 kΩ 30 kΩ 30 kΩ C19 1 µF +5 V .01 µF .01 µF CLK VIN VFT VST VRM VSB VFB R R 1 µF CLK VIN IC2 OP-07 VEE VCC DV CC VEE VCC DV CC AGND DGND DGND AGND 10 µF 10 µF C10 .01 µF (TTL) (±2 V) +2.5 V -2.5 V FB +5 V AGND DGND-5.2 V (Analog)(Analog) FB FB C11 .01 µF 100 Ω ± 2.5 V Max .01 µF .01 µF .01 µF .01 µF .1 µF .1 µF Notes to prevent latch-up due to power sequencing: 1) D1 = Schottky or hot carrier diode, P/N IN5817. 2) FB = Ferrite bead, Fair Rite P/N 2743001111 to be mounted as close to the device as possible. The ferrite bead to the ADC connection should not be shared with any other device. 3) C1-C11 = Chip cap (recommended) mounted as close to the device's pin as possible. 4) Use of a separate supply for V CC and DVCC is not recommended. 5) R1 provides current limiting to 45 mA. 6) C6, C7, C8 and C9 should be ten times larger than C10 and C11. 7) C8 = C9 = a 0.1 µF cap in parallel with a 4.7 µF cap.
ladder taps (VST , VRM and VSB ). VST is the sense for the top of the reference ladder (+2.0 V), VRM is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0 V). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). These points should be used to monitor the actual full scale input voltage of the device and should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 µF (chip cap preferred) connected to AGND from each tap is recom- mended to minimize high frequency noise injection. Figure 3 - Analog Equivalent Input Circuit VCC VEE VFTVIN /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Analog Prescaler An example of a reference driver circuit recommended is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is 10 kΩ and supports a minimum adjustable range of up to 150 mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3 LSB matching between V FT and VFB . If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. VFT and VFB should be adjusted such that VST and VSB are exactly +2.0 V and -2.0 V respectively. The analog input range will scale proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is ± 20% of the recommended reference voltages of V FT and VFB . How- ever, because the device is laser trimmed to optimize perfor- mance with ± 2.5 V references, the accuracy of the device will degrade if operated beyond a ± 2% range. The following errors are defined: +FS error = top of ladder offset voltage = Δ(+FS -V ST +1 LSB) -FS error = bottom of ladder offset voltage = Δ(-FS -VSB -1 LSB) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. ANALOG INPUT VIN is the analog input. The full scale input range will be 80% of the reference voltage or ±2 volts with VFB =-2.5 V and VFT=+2.5 V. The drive requirements for the analog inputs are minimal when compared to conventional Flash converters due to the SPT7820’s extremely low input capacitance of only 5 pF and very high input resistance of 300 kΩ . For example, for an input signal of ±2 V p-p with an input frequency of 10 MHz, the peak output current required for the driving circuit is only 628 µA. CLOCK INPUT The SPT7820 is driven from a single-ended TTL input (CLK). The CLK pulse width (tpwH) must be kept between 20 ns and 300 ns to ensure proper operation of the internal track-and- hold amplifier. (See timing diagram.) When operating the SPT7820 at sampling rates above 3 MSPS, it is recom- mended that the clock input duty cycle be kept at 50% but performance will not be degraded if kept within the range of 40-60%. The analog input signal is latched on the rising edge of the CLK. The clock input must be driven from fast TTL logic (V IH ≤4.5 V, TRISE <6 ns). In the event the clock is driven from a high current source, use a 100 Ω resistor in series to current limit to approximately 45 mA. DIGITAL OUTPUTS The format of the output data (D0-D9) is straight binary. (See table II.) The outputs are latched on the rising edge of CLK with a propagation delay of 14 ns (typ). There is a one clock cycle latency between CLK and the valid output data. (See the timing diagram.) Table II - Output Data Information ANALOG INPUT OVERRANGE OUTPUT CODE D1O D9-DO >+2.0 V + 1/2 LSB 1 11 1111 1111 +2.0 V -1 LSB O 11 1111 111Ø
0.0 V O ØØ ØØØØ ØØØØ
-2.0 V +1 LSB O OO OOOO OOOØ <-2.0 V O OO OOOO OOOO (Ø indicates the flickering bit between logic 0 and 1). The rise times and fall times of the digital outputs are not symmetrical. The propagation delay of the rise time is typi- cally 14 ns and the fall time is typically 6 ns. (See figure 4.) The nonsymmetrical rise and fall times create approximately 8 ns of invalid data.
Figure 4 - Digital Output Characteristics 3.5 V N+1 Rise Time 6 nsec6 ns typ. CLK In N 2.4 V Invalid Data (N-1)(N-2) (N-1)Data Out (Equivalent) Invalid Data /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Data Out (Actual) (N-2) (N-1) (N) 2.4 V 0.8 V
0.5 V tpd1
(14 ns typ.) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Invalid Data Invalid Data OVERRANGE OUTPUT The OVERRANGE OUTPUT (D10) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 LSB. When this condition occurs, D10 will switch to logic 1. All other data outputs (D0 to D9) will remain at logic 1 as long as D10 remains at logic 1. This feature makes it possible to include the SPT7820 into higher resolution systems. EVALUATION BOARD The EB7820 evaluation board is available to aid designers in demonstrating the full performance of the SPT7820. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note describing the operation of this board as well as information on the testing of the SPT7820 is also available. Contact the factory for price and availability.
A B C D E F G I H J 28-Lead Plastic DIP A B C D E J K F G H I INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.200 5.08 B 0.120 0.135 3.05 3.43 C 0.020 0.51 D 0.100 2.54 E 0.067 1.70 F 0.013 0.33 G 0.170 0.180 4.32 4.57 H 0.622 15.80 I 0.555 14.10 J 1.460 37.08 K 0.085 2.16 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.077 0.093 1.96 2.36 B 0.016 0.020 0.41 0.51 C 0.095 0.105 2.41 2.67 D .050 typ 0.00 1.27 E 0.040 0.060 1.02 1.52 F 0.215 0.235 5.46 5.97 G 1.388 1.412 35.26 35.86 H 0.585 0.605 14.86 15.37 I 0.009 0.012 0.23 0.30 J 0.600 0.620 15.24 15.75
A 0.696 0.712 17.68 18.08 B 0.004 0.012 0.10 0.30 C .050 typ 0.00 1.27 D 0.014 0.019 0.36 0.48 E 0.009 0.012 0.23 0.30 F 0.080 0.100 2.03 2.54 G 0.016 0.050 0.41 1.27 H 0.394 0.419 10.01 10.64 I 0.291 0.299 7.39 7.59 A B CD E F G I H
V ST V CC V EE V FT DGND DV V RM V V AGND V EE CC FB DV CC CC DIP/PDIP/SOIC PIN FUNCTIONS Name Function DGND Digital Ground D0-D9 TTL Outputs (D0=LSB) D10 TTL Output Overrange CLK Clock VEE -5.2 V Supply (Analog) AGND Analog Ground VCC +5.0 V supply (Analog) VIN Analog Input DV CC Digital +5.0 V Supply VRM Middle of Voltage Reference Ladder VFT Force for Top of Reference Ladder VST Sense for Top of Reference Ladder VFB Force for Bottom of Reference Ladder VSB Sense for Bottom of Reference Ladder PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT7820AIJ -25 to +85 °C 28L Sidebrazed DIP SPT7820BIJ -25 to +85 °C 28L Sidebrazed DIP SPT7820ACN 0 to +70 °C 28L Plastic DIP SPT7820BCN 0 to +70 °C 28L Plastic DIP SPT7820ACS 0 to +70 °C 28L SOIC SPT7820BCS 0 to +70 °C 28L SOIC SPT7820AMJ -55 to +125 °C 28L Sidebrazed DIP SPT7820BMJ -55 to +125 °C 28L Sidebrazed DIP