SPT7814

SPT7814 CADEKA | Alldatasheet

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Amplify the Human Experience 10-BIT, 40 MSPS, ECL OUTPUT A/D CONVERTER SS Orr FEATURES APPLICATIONS * Monolithic 40 MSPS Converter * Medical Imaging + On-Chip Track/Hold +« Professional Video + Bipolar 2.0 V Analog Input + Radar Receivers + 57 dB SNR @ 3.58 MHz Input + Instrumentation + 50 dB SNR @ 10.3 MHz Input + Electronic Warfare + Low Power (1.3 W Typical) * Digital Communications * 5 pF Input Capacitance + ECL Outputs GENERAL DESCRIPTION The SPT7814 A/D converter is a 10-bit monolithic converter Output data format is straight binary. Power dissipation is capable of word rates of a minimum of 40 MSPS. On board _ very lowat only 1.3 watts with power supply voltages of +5.0 track/hold function assures excellent dynamic performance —_and -5.2 volts. The SPT7814 also provides a wide input without the need for external components. Drive require- _ voltage swing of +2.0 volts. ment problems are minimized with an input capacitance of only 8 pF p ? The SPT7814 is available in a 28-lead ceramic sidebrazed . DIP, PDIP, and die form. Commercial and industrial tempera- Inputs and outputs are ECL to provide a higher level ofnoise —_ ture ranges are currently offered. Contact the factory for immunity in high speed system applications. An overrange _ availability of military temperature ranges and /833 pro- output signal is provided to indicate overflow conditions. cessed units. BLOCK DIAGRAM ann SODSEER DODOCLLIES SODEEES SOE : Ke» Output Stage i ad Stage i+1

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)' 25 °C Supply Voltages Output NEE ssncesssuvscsscsvseasvsseseursussssassrrvstesvon svssaesconvseet Os SHOMD! Vi Temperature Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TEST TEST SPT7814A SPT7814B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX | UNITS DC Accuracy (+25 °C) + Full Scale Integral Nonlinearity 250 kHz Sample Rate Vv +1.0 21.5 LSB Differential Nonlinearity Vv +0.5 +0.75 LSB No Missing Codes vi Guaranteed Guaranteed Analog Input Input Voltage Range vi +2.0 +2.0 Input Bias Current Vin=0 V vi 30 60 30 60 | pA Input Resistance vi 100 300 100 300 kQ Input Capacitance v 5 5 pF Input Bandwidth 3 dB Small Signal Vv 120 120 MHz +FS Error Vv +2.0 42.0 LSB -FS Error Vv +2.0 2.0 LSB Reference Input Reference Ladder Resistance vi 500 800 500 800 Qa Reference Ladder Tempco Vv 0.8 0.8 Orc Timing Characteristics Maximum Conversion Rate vl 40 40 MHz Overvoltage Recovery Time v 20 20 ns Pipeline Delay (Latency) IV 1 1 | Clock Cyde Output Delay Ta=+25 °C Vv 5 5 ns Aperture Delay Time Ta=+25 °C Vv 1 1 ns Aperture Jitter Time Ta=+25 °C Vv 5 5 ps-RMS Dynamic Performance Effective Number of Bits fin=1 MHz. 8.7 8.2 Bits fin=3.58 MHz 8.7 8.2 Bits fin=10.3 MHz 7.3 6.9 Bits Typical thermal impedances: 28L sidebrazed DIP: 6, = 50 °C/W, 28L plastic DIP: 0, = 50 °C/W. SPT7814 2 snr

TEST TEST SPT7814A SPT7814B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX | UNITS Dynamic Performance Signal-To-Noise Ratio (without Harmonics) fin=1 MHz +25 °C | 55 57 52 54 dB Ta=Tmin - Tmax IV 53 55 50 52 dB fin=3.58 MHz. +25 °C | 55 57 52 54 dB Ta=Tmin - Tmax IV 53 55 50 52 dB fin=10.3 MHz +25 °C | 48 50 46 48 dB Ta=Tmin - Tmax IV 45 47 43 45 dB Harmonic Distortion fin=1 MHz +25°C I 54 56 52 54 dB Ta=Tmin - Tmax IV 54 53 49 51 dB fin=3.58 MHz +25 °C I 54 56 52 54 dB Ta=Tmin - Tmax IV 51 53 49 51 dB fin=10.3 MHz +25 °C. I 46 48 43 45 dB Ta=Tmin - Tmax IV 45 47 41 43 dB Signal-to-Noise and Distortion fin=1 MHz. +25 °C I 52 54 49 51 dB Ta=Tmin - Tmax IV 49 46 dB fin=3.58 MHz +25 °C | 52 54 49 51 dB Ta=Tmin - Tmax IV 49 46 dB fin=10.3 MHz +25 °C i 44 46 41 43 dB Ta=Tmin - Tmax IV 43 40 dB Spurious Free Dynamic Range | +25 °C, fin=1 MHz V 67 67 dB Differential Phase +25 °C, fin=3.58 & 4.35 MHz Vv 0.2 0.2 Degree Differential Gain +25 °C, fin=3.58 & 4.35 MHz Vv 0.5 0.7 % Digital Inputs Logic 1 Voltage vi Aa AA v Logic 0 Voltage vi 15 -15/V Maximum Input Current Low vi -600 +200 +750 | -500 +200 +750] pA Maximum Input Current High vi -500 +300 +750 | -500 +300 +750} pA Pulse Width Low (CLK) Vv 10 10 ns Pulse Width High (CLK) IV 10 300 10 300 | ns Digital Outputs Logic 1 Voltage 502 to-2V vi 14 -0.8 14 -0.8 v Logic 0 Voltage 502 to-2V Vi 1.8 1.5 -1.8 -1.5)V Power Supply Requirements Currents Icc. Vi 140 170 140 190 | mA IEE vi 115 140 115 160 | mA Power Dissipation Outputs Open Vi 1.3 1.6 1.3 1.8) W SPT7814 3 anve7

APERTURE DELAY DIFFERENTIAL NONLINEARITY (DNL) Aperture delay represents the point in time, relative to the Error in the width of each code from its theoretical value. tising edge of the CLOCK input, that the analog input is (Theoretical = Vrs/2N) sampled. INTEGRAL NONLINEARITY (INL) APERTURE JITTER Linearity error refers to the deviation of each individual code The variations in aperture delay for successive samples. (normalized) from a straight line drawn from -Fs through +Fs. The deviation is measured from the edge of each particular DIFFERENTIAL GAIN (DG) code to the true straight line. A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the OUTPUT DELAY maximum variation in the sampled sine wave amplitudes at Time between the clock's triggering edge and output data these DC levels. valid. DIFFERENTIAL PHASE (DP) OVERVOLTAGE RECOVERY TIME. A signal consisting of a sine wave superimposed on various —- The time required for the ADC to recover to full accuracy after DC levels that is applied to the input. Differential phase isthe an analog input signal 125% of full scale is reduced to 50% variation in the sampled sine wave phases at these DC levels. of the full-scale value. EFFECTIVE NUMBER OF BITS (ENOB) SIGNAL-TO-NOISE RATIO (SNR) SINAD = 6.02N + 1.76, where N is equal to the effective The ratio of the fundamental sinusoid power to the total noise number of bits. power. Harmonics are excluded. Ny =SINAD - 1.76 _ 602 SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise +FULL-SCALE ERROR (GAIN ERROR) and distortion power. Difference between measured full scale response [(+Fs) - (-Fs)] and the theoretical response (+4 V-2 LSBs) | TOTAL HARMONIC DISTORTION (THD) where the +FS (full scale) input voltage is defined as the The ratio of the total power of the first 64 harmonics to the output transition between 1-10 and 1-11 and the -FS input —_ power of the measured sinusoidal signal voltage is defined as the output transition between 0-00 and 0-01. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the INPUT BANDWIDTH single largest harmonic or spurious signal. Small signal (50 mV) bandwidth (3 dB) of analog input stage. SPT7814 5 ani9e7

TYPICAL PERFORMANCE CHARACTERISTICS THD vs Input Frequency ‘SNR vs Input Frequency 80 20| i) 70 s fs = 40 MSPS ay fs = 40 MSPS 5 60 Z 5 Fy & so @ g 3 2 g A 3 = 0 z a BS 2 ® x0 @ 20 20 100 101 102 oO 1 2 10 10 10 Input Frequency (MHz) Input Frequency (MHz) SINAD vs Input Frequency SNR, THD, SINAD vs Sample Rate 80 80 70 70 Fy = fs =40 MSPS SNR 5 ss s = & 2 NN Zz ® 50 sina” 8 g THD 3 > fin = 1 MHz 2 «0 £4 2 6 a 30 ba 20 10° 107 102 10° 107 102 Input Frequency Sample Rate (MSPS) (MHz) Spectral Response SNR, THD, SINAD vs Temperature o 65 fs = 40 MSPS. fin = 1 MHz -30 a

8 E =

€ oso | F 3 fs = 40 MSPS -00 UTA aa at a a a Ma fin = 1 MHz i sulidifaulb sul al a! hitler lid 45 120 ie 25 o +25 +50 +75, o 4 2 3 4 5 6 7 & 9 Input Frequency (MHz) Temperature (°C) SPT7814 6 3497

TYPICAL INTERFACE CIRCUIT are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of The SPT7814 requires few external components to achieve the SPT7814. The AGND and the DGND ground planes the stated operation and performance. Figure 2 shows the should be separated from each olfiek and aly) contiected typical interface requirements when using the SPT7814 in together at the device through an inductance. Doing this will normal circuit operation. minimize the ground noise pickup. The following section provides a description of the pin func- VOLTAGE REFERENCE tions and outlines critical performance criteria to consider for A achieving the optimal device performance. The SPT7814 requires the use of two voltage references: VFT . and Vrp. Vrris the force for the top of the voltage reference POWER SUPPLIES AND GROUNDING ladder (+2.5 V typ), VeB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. The SPT7814 ires th dF t I It Vi iii and VEE, Both supstiea should be hentetse araion eppty In addition, there are 3 reference ladder taps (Vst,VRm and sources. This means the Veg and Vcc ground returns of the Vse). Vsr is the serise for the top oF sthe:reterence ledger device should both be connected to the analog ground (0 AR ee paint ot Me tedces (0.0'v eyed Ves is tl ih (-2.1 . plane. All other -5.2 V requirements of the external digital Th obs altaes forthe Var andVeg ele ara ace ote eee cowarutool poeieat ke breed pier voltages of the device when Vrt and Vrp are driven to the F fi . recommended voltages (+2.5 V and -2.5 V typical respec- a ‘° the cevice with .01 4F and 10 AF capacitors as tively). These points should be used to monitor the actual full ShOWN MiQure 2. scale input voltage of the device and should not be driven to ; the expected ideal values as is commonly done with standard BEARS GONG lo coed only for ECL. oat hana rest flash converters. When not being used, a decoupling capaci- . tor of .01 uF connected to AGND from each tap is recom- referenced to the output pulldown voltage. These grounds mended to minimize high frequency noise injection. Figure 2 - Typical Interface Circuit ‘cUKAN © ax an O =| > na © am Sens 10 (OVERRANGE) -f-——- <r: waioe vay a 40 wf de Ce TTT = oe oe = z Le TTT i : z “ —— 2 eT val a 3 7 ne F\\ | ~ fee | AS be ota * poof) - HAH _— rmatenest0 0.1% sy, _ fs tort toe + oye ope | *i«t CTT + ue EK oF sev wy Due | ot ww F b + 4 Vey Voy 4aNo eno av (svrms cavemy Se NOTE: D1=D2=1N5817 or equivalent. (Used to prevent damage caused by power sequencing.) SPT7814 7 3nte7

An example of a reference driver circuit recommended is = The CLK pulse width (tpwH) must be kept between 10 ns and shown in figure 2. |C1 is REF-03, the +2.5 V reference with a 300 ns to ensure proper operation of the internal track-and- 10 kQ and supports a minimum adjustable range of up to SPT7814 at sampling rates above 3 MSPS, it is recom- 150 mV. IC2 is recommended to be an OP-07 or equivalent mended that the clock input duty cycle be kept at 50% to device. R2 and R3 must be matched to within 0.1% with good _ optimize performance. (See graph.) The analog input signal TC tracking to maintain a0.3LSB matching between Vrrand __ is latched on the rising edge of the CLK. Ves. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the Vrg voltage to the desired level. R1 and R4 should be adjusted such that Vst and Vsp are exactly SNR vs Clock Duty Cycle +2.0 V and -2.0 V respectively. ‘ The analog input range will scale proportionally with respect 57| to the reference voltage if a different input range is required. Py The maximum scaling factor for device operation is + 20% of = 55) the recommended reference voltages of Vrt and Vrg. How- & 83| ever, because the device is laser trimmed to optimize perfor- 3 Duty _ tpwHt mance with+ 2.5 V references, the accuracy of the device will 2 = Cycle” tpwL degrade if operated beyond a + 2% range. 2 a9 2 towH — tpwl The following errors are defined: t : i +FS error = top of ladder offset voltage = A(+FS -Vst+1 LSB) 45] — -FS error=bottom of ladder offset voltage=A(-FS -Vgp -1 LSB) ‘a where the +FS (full scale) input voltage is defined as the 30-35 40455 55H output transition between 1-10 and 1-11 and the -FS input Duty Cycle of Positive Clock Pulse (%) voltage is defined as the output transition between 0-00 and ool. DIGITAL OUTPUTS ANALOG INPUT The format of the output data (DO-D9) is straight binary. Vint and Vin2 are the analog inputs. Both inputs are tied to These outputs are ECL with the output circuit shown in the same point internally. Either one may be used as an figure 4. The outputs are latched on the rising edge of CLK analoginputsense andthe otherforaninputforce. Theinputs _ With a propagation delay of 4 ns. There is a one clock cycle can also be tied together and driven from the same source. _atency between CLK and the valid output data (see timing The full scale input range will be 80% of the reference voltage diagram). These digital outputs can drive 50 ohms to ECL or #2 volts with Vrg=-2.5 V and VrT=+2.5 V. levels when pulled down to -2 V. The total specified power dissipation of the device does not include the power used by The drive requirements for the analog inputs are minimal _these loads. The additional power used by these loads can when compared to conventional Flash converters due the Vary between 10and300 mW typically (including the overrange SPT7814’s extremely low input capacitance of only 5 pF and load) depending on the output codes. If lower power levels very high input resistance of 300kQ. Forexample,foraninput fe desired, the output loads can be reduced, but careful signal of £2 V p-p with an input frequency of 10 MHz, the peak consideration to the capacitive loads in relation to the oper- output current required for the driving circuit is only 628 pA. _ ting frequency must be considered. CLOCK INPUT Table Il - Output Data Information The clock inputs (CLK,CLK) are designed to be driven differ- DIO D9-DO entially with ECL levels. The clock may be driven single ended since CLK is internally biased to -1.3 V. CLK may be left open, but a .01 uF bypass capacitor to AGND is recom- mended. As with all high speed circuits, proper terminations are required to avoid signal reflections and possible ringing that can cause the device to trigger at an unwanted time. (@ indicates the flickering bit between logic 0 and 1). SPT7814 8 31/97

Figure 3 - Output Circuit EVALUATION BOARD AGND DGND The EB7814 evaluation board is available to aid designers in demonstrating the full performance of the SPT7814. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note describing the operation of this board as well as information on the testing of the SPT7814 is el also available. Contact the factory for price and availability. OVERRANGE OUTPUT The OVERRANGE OUTPUT (D10) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 LSB. When this condition occurs, D10 will switch to logic 1. All other data outputs (DO to D9) will remain at logic 1 as long as D10 remains at logic 1. This feature makes it possible to include the SPT7814 into higher resolution systems. SPT7814 9 ante7

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PIN ASSIGNMENTS PIN FUNCTIONS Name Function oenoLy 3 Vee DGND Digital Ground po [27] AGND DO-D9 ECL Outputs (D0=LSB) of [26 Vise D10 ECL Output Overrange pe [al Veg CLK Clock Input ps [al Vga CLK Inverted Clock Input VEE -5.2 V Supply os [gl Van AGND Analog Ground DS Sidebrazed av. PDIP 3 INt Vec +5.0 V supply ve [3 Vina Vint, ViN2 Inputs (tied together at the die) ov Lg Ee VeT Force for Top of Reference Ladder ps [ial lg Ver Vst Sense for Top of Reference Ladder an [7 Yoo VFB Force for Bottom of Reference Ladder VsB Sense for Bottom of Reference Ladder pio [12] AGND - VRM Middle of Reference Ladder penp [13] 8 Vee cik [14] [19 CLK

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT7814AlJ -25 to +85 °C 28L Sidebrazed DIP SPT7814BlJ -25 to +85 °C 28L Sidebrazed DIP SPT7814ACN Oto70 °C 28L Plastic DIP SPT7814BCN Oto 70 °C 28L Plastic DIP SPT7814BCU +25 °C Die* *Please see the die specification for guaranteed electrical performance. For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Head veland, Coloradc . CADEKA Maadquarters Lover, Clorto ka C AD EK A 7: 877.663.5452 (toll free) Amplify the Human Experience CCADEKA, the CADEKA logo design, Comlineay, and the Comlnear logo design are trademarks of registered trademarks of CADEKA Microctutts LLC. All other brand and product names may be trademarks of thet respective companies, CCADEKA rcservesthe right Lo make changes to any products and services herein at any'tme wathout notice. CADEKA does nat assume any responsibilty or tabityansing out of the application or use of any product or serwce described herein, except 2s expressly agreed to sn vetng by CADEKA; nor does the purchase, lease, or use of @ product or service from CADEKA convey a license undex any patent rights, Copynghts, trademark nghts, or any other of the intellectual property rights of CADEKA or of thd parties. Copyright %:2007-2009 by CADEXA Microcieuits LLC. All nghts reserved. ee SPT7814 11 3n97