SPT7810 CADEKA | Alldatasheet

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Technical content

10-BIT, 20 MSPS, ECL OUTPUT A/D CONVERTER

FEATURES

  • Monolithic 20 MSPS Converter
  • On-Chip Track/Hold
  • Bipolar ±2.0 V Analog Input
  • 60 dB SNR @ 1 MHz Input
  • Low Power (1.3 W Typical)
  • 5 pF input Capacitance
  • ECL Outputs

APPLICATIONS

  • Medical Imaging
  • Professional Video
  • Radar Receivers
  • Instrumentation
  • Electronic Warfare
  • Digital Communications Analog Prescaler Digital Output Successive Interpolation Stage i Successive Interpolation Stage i+1 Successive Interpolation Stage N Analog Input 4Coarse A/D T/H Amplifier Bank /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Decoding Network GENERAL DESCRIPTION The SPT7810 A/D converter is a 10-bit monolithic converter capable of word rates of a minimum of 20 MSPS. On board track/hold function assures excellent dynamic performance without the need for external components. Drive require- ment problems are minimized with an input capacitance of only 5 pF. Inputs and outputs are ECL to provide a higher level of noise immunity in high speed system applications. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.3 watts with power supply voltages of +5.0 and -5.2 volts. The SPT7810 also provides a wide input voltage swing of ±2.0 volts. The SPT7810 is available in a 28-lead ceramic sidebrazed DIP, PDIP, and die form. Commercial and industrial tempera- ture ranges are currently offered. Contact the factory for availability of military temperature range and /883 processed units. BLOCK DIAGRAM

TEST TEST SPT7810A SPT7810B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Resolution 10 10 Bits DC Accuracy (+25 °C) ± Full Scale Integral Nonlinearity 250 kHz Sample Rate V ±1.0 ±1.5 LSB Differential Nonlinearity V ±0.5 ±0.75 LSB No Missing Codes VI Guaranteed Guaranteed Analog Input Input Voltage Range VI ±2.0 ±2.0 V Input Bias Current VIN=0 V VI 30 60 30 60 µA Input Resistance VI 100 300 100 300 kΩ Input Capacitance V 5 5 pF Input Bandwidth 3 dB Small Signal V 120 120 MHz +FS Error V ±2.0 ±2.0 LSB -FS Error V ±2.0 ±2.0 LSB Reference Input Reference Ladder Resistance VI 500 800 500 800 Ω Reference Ladder Tempco V 0.8 0.8 Ω /°C Timing Characteristics Maximum Conversion Rate VI 20 20 MHz Overvoltage Recovery Time V 20 20 ns Pipeline Delay (Latency) IV 1 1 Clock Cycle Output Delay TA=+25 °CV 5 5 ns Aperture Delay Time TA=+25 °CV 1 1 ns Aperture Jitter Time TA=+25 °C V 5 5 ps-RMS Dynamic Performance Effective Number of Bits fIN=1 MHz 9.2 8.7 Bits fIN=3.58 MHz 8.8 8.3 Bits fIN=10.3 MHz 7.5 7.0 Bits ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Supply Voltages Input Voltages Output Temperature Typical thermal impedances:28L sidebrazed DIP. θja = 50 °C/W, 28L plastic DIP θja = 50 °C/W. 2 3/11/97

TEST TEST SPT7810A SPT7810B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Dynamic Performance Signal-To-Noise Ratio (without Harmonics) fIN=1 MHz +25 °C I 57 60 54 57 dB IV 55 58 52 55 dB fIN=3.58 MHz +25 °C I 56 58 53 55 dB IV 54 56 51 53 dB fIN=10.3 MHz +25 °C I 50 53 47 49 dB IV 47 50 44 46 dB Harmonic Distortion fIN=1 MHz +25 °C I 57 60 54 57 dB IV 54 57 51 54 dB fIN=3.58 MHz +25 °C I 56 58 53 55 dB IV 53 55 50 52 dB fIN=10.3 MHz +25 °C I 46 48 43 45 dB IV 45 47 42 44 dB Signal-to-Noise and Distortion fIN=1 MHz +25 °C I 55 57 52 54 dB IV 52 49 dB fIN=3.58 MHz +25 °C I 54 55 51 52 dB IV 51 48 dB fIN=10.3 MHz +25 °C I 44 47 41 44 dB IV 43 40 dB Spurious Free Dynamic Range+25 °C, fIN =1 MHz V 67 67 dB Differential Phase +25 °C, fIN=3.58 & 4.35 MHz V 0.2 0.2 Degree Differential Gain +25 °C, fIN=3.58 & 4.35 MHz V 0.5 0.7 % Digital Inputs Logic 1 Voltage VI -1.1 -1.1 V Logic 0 Voltage VI -1.5 -1.5 V Maximum Input Current Low VI -500 ±200 +750 -500 ±200 +750 µA Maximum Input Current High VI -500 ±300 +750 -500 +300 +750 µA Pulse Width Low (CLK) IV 20 20 ns Pulse Width High (CLK) IV 20 300 20 300 ns Digital Outputs Logic 1 Voltage 50 Ω to -2 V VI -1.1 -0.8 -1.1 -0.8 V Logic 0 Voltage 50 Ω to -2 V VI -1.8 -1.5 -1.8 -1.5 V Power Supply Requirements Currents ICC VI 140 170 140 190 mA -IEE VI 115 140 115 160 mA Power Dissipation Outputs Open VI 1.3 1.6 1.3 1.8 W 3 3/11/97

Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. APERTURE JITTER The variations in aperture delay for successive samples. DIFFERENTIAL GAIN (DG) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. DIFFERENTIAL PHASE (DP) A signal consisting of a sine wave superimposed on various DC levels that is applied to the input. Differential phase is the variation in the sampled sine wave phases at these DC levels. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. N = S INAD - 1.76 6.02 ± FULL-SCALE ERROR (GAIN ERROR) Difference between measured full scale response [(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. INPUT BANDWIDTH Small signal (50 mV) bandwidth (3 dB) of analog input stage. DIFFERENTIAL NONLINEARITY (DNL) Error in the width of each code from its theoretical value. (Theoretical = VFS /2N ) INTEGRAL NONLINEARITY (INL) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -Fs through +Fs. The deviation is measured from the edge of each particular code to the true straight line. OUTPUT DELAY Time between the clock's triggering edge and output data valid. OVERVOLTAGE RECOVERY TIME The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise and distortion power. TOTAL HARMONIC DISTORTION (THD) The ratio of the total power of the first 64 harmonics to the power of the measured sinusoidal signal. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal. 5 3/11/97

TYPICAL PERFORMANCE CHARACTERISTICS Input Frequency (MHz) Signal-to-Noise Ratio (dB) SNR vs Input Frequency 100 101 102 fs = 20 MSPS /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 100 101 102 SNR, THD, SINAD vs Sample Rate Sample Rate (MSPS) SNR, THD, SINAD (dB) SNR, THD fin = 1 MHz SINAD SNR, THD, SINAD vs Temperature Temperature (°C) SNR, THD, SINAD (dB) fs = 20 MSPS fin = 1 MHz SINAD SNR -25 0 +25 +50 +75 SNR THDTHD Signal-to-Noise and Distortion (dB) 100 101 102 SINAD vs Input Frequency Input Frequency (MHz) fs =20 MSPS 100 101 102 THD vs Input Frequency Input Frequency (MHz) Total Harmonic Distortion (dB) fs = 20 MSPS -120 -90 -60 -30 Input Frequency (MHz) Amplitude (dB) Spectral Response 0 1 2 34567 89 10 fs = 20 MSPS fin = 1 MHz 6 3/11/97

The SPT7810 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7810 in normal circuit operation. The following section provides a description of the pin func- tions and outlines critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7810 requires the use of two supply voltages, VEE and VCC . Both supplies should be treated as analog supply sources. This means the VEE and VCC ground returns of the device should both be connected to the analog ground plane. All other -5.2 V requirements of the external digital logic circuit should be connected to the digital ground plane. Each power supply pin should be bypassed as closely as possible to the device with .01 µF and 10 µF capacitors as shown in figure 2. The two grounds available on the SPT7810 are AGND and DGND. DGND is used only for ECL outputs and is to be referenced to the output pulldown voltage. These grounds are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of the SPT7810. The AGND and the DGND ground planes should be separated from each other and only connected together at the device through an inductance. Doing this will minimize the ground noise pickup. VOLTAGE REFERENCE The SPT7810 requires the use of two voltage references: VFT and VFB . VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. In addition, there are 3 reference ladder taps (VST ,VRM and VSB ). VST is the sense for the top of the reference ladder (+2.0 V), VRM is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0V). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). These points should be used to monitor the actual full scale input voltage of the device and should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 uF connected to AGND from each tap is recommended to minimize high frequency noise injection. An example of a reference driver circuit recommended is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a Figure 2 - Typical Interface Circuit VIN2 VEE VRM .01 µF 10 µF R R 4Coarse A/D 11 x 50 Ω D0 (LSB) D9 (MSB) D10 (OVERRANGE) DG DG AG AG VCC VCC VEE -2 V-5.2 V +5 V AGND ( 5 V RTN & -5.2 V RTN ) DGND ( -2 V RTN ) VFT VFB SUCCESSIVE INTERPOLA TION STAGE # N SUCCESSIVE INTERPOLA TION STAGE # i T/H AMPLIFIER BANK ANALOG PRESCALER VIN1 10 µF .01 µF + 10 µF .01 µF 10 µF .01 µF + L /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines .01 µF + 23 VIN VOUT Trim GND 10 kΩ R2 * 30 kΩ 10 kΩ R3 * 30 kΩ IC1 IC2 (REF-03) (OP-07) -5.2 V .01 µF +2.5 V -5.2 V +5 V .01 µF VST .01 µF VSB *R2 and R3 matched to 0.1% .01 µF 10 µH +5 V CLK CLK CLK-IN CLK-IN Decoding Netw or k Analog Input Analog Input 10 µF +5 V .01 µF 10 µF -2.5 V Digital Outputs NO TE: D1=D2=1N5817 or equivalent. (Used to prevent damage caused by pow er sequencing.) 7 3/11/97

+2.0 V and -2.0V respectively. to the reference voltage if a different input range is required. degrade if operated beyond a ± 2% range. voltage or ±2 volts with VFB =-2.5 V and VFT=+2.5 V. output current required for the driving circuit is only 628 µA. that can cause the device to trigger at an unwanted time. clock input duty cycle be kept at 50% to optimize performance. The analog input signal is latched on the rising edge of the CLK. The format of the output data (D0-D9) is straight binary. figure 4. The outputs are latched on the rising edge of CLK ating frequency must be considered.

0.0 V O Ø Ø ØØØØ ØØØØ

(Ø indicates the flickering bit between logic 0 and 1). possible to include the SPT7810 into higher resolution systems. also available. Contact the factory for price and availability.

A 0.077 0.093 1.96 2.36 B 0.016 0.020 0.41 0.51 C 0.095 0.105 2.41 2.67 D .050 typ 0.00 1.27 E 0.040 0.060 1.02 1.52 F 0.215 0.235 5.46 5.97 G 1.388 1.412 35.26 35.86 H 0.585 0.605 14.86 15.37 I 0.009 0.012 0.23 0.30 J 0.600 0.620 15.24 15.75A B C D E F G I H J A B C D E J K F G H I INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.200 5.08 B 0.120 0.135 3.05 3.43 C 0.020 0.51 D 0.100 2.54 E 0.067 1.70 F 0.013 0.33 G 0.170 0.180 4.32 4.57 H 0.622 15.80 I 0.555 14.10 J 1.460 37.08 K 0.085 2.16 28-Lead Plastic DIP 9 3/11/97