SPT7755 CADEKA | Alldatasheet

Document overview

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Technical content

8-BIT, 750 MSPS, FLASH A/D CONVERTER OCTOBER 2002

FEATURES

  • 1:2 Demuxed ECL compatible outputs
  • Wide input bandwidth – 900 MHz
  • L ow input capacitance – 15 pF
  • Metastable errors reduced to 1 LSB
  • Monolithic for low cost
  • G ray code output

APPLICATIONS

  • Digital oscilloscopes
  • T ransient capture
  • Radar, EW, ECM
  • Direct RF down-conversion GENERAL DESCRIPTION The SPT7755 is a full parallel (flash) analog-to-digital con- verter capable of digitizing full scale (0 to –2 V) inputs into eight-bit digital words at an update rate of 750 MSPS. The ECL-compatible outputs are demultiplexed into two sepa- rate output banks , each with diff erential data ready out- puts to ease the task of data capture. The SPT7755’s wide input bandwidth and lo w capacitance eliminate the need for external track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7755 operates from a single – 5.2 V supply, with a nominal power dissipation of 5.5 W. The SPT7755 is a vailable in an 80-lead surf ace-mount MQuad pac kage o ver the industr ial temper ature r ange /MT50/MT53/MT54 /MT50/MT53/MT53 /MT49/MT53/MT50 /MT49/MT53/MT49 /MT49/MT50/MT56 /MT49/MT50/MT55 /MT54/MT52 /MT54/MT51 /MT50 /MT49 /MT67/MT76/MT79/MT67/MT75 /MT66/MT85/MT70/MT70/MT69/MT82/MT50/MT53/MT54/MT32/MT32/MT84/MT79/MT32/MT56/MT32/MT66/MT105/MT116/MT32/MT68/MT101/MT99/MT111/MT100/MT101/MT114 /MT87/MT105/MT116/MT104/MT32/MT77/MT101/MT116/MT97/MT115/MT116/MT97/MT98/MT108/MT101/MT32/MT69/MT114/MT114/MT111/MT114/MT32/MT67/MT111/MT114/MT114/MT101/MT99/MT116/MT105/MT111/MT110 /MT68/MT48 /MT40/MT76/MT83/MT66/MT41 /MT68/MT49 /MT68/MT50 /MT68/MT51 /MT68/MT52 /MT68/MT53 /MT68/MT54 /MT68/MT55 /MT40/MT77/MT83/MT66/MT41 /MT68/MT56 /MT40/MT79/MT86/MT82/MT41 /MT86/MT82/MT84 /MT65/MT110/MT97/MT108/MT111/MT103 /MT73/MT110/MT112/MT117/MT116 /MT80/MT114/MT101/MT97/MT109/MT112/MT67/MT111/MT109/MT112/MT97/MT114/MT97/MT116/MT111/MT114 /MT86/MT82/MT77 /MT86/MT82/MT66 /MT67/MT76/MT75/MT67/MT76/MT75 /MT69/MT67/MT76/MT32/MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT66/MT117/MT102/MT102/MT101/MT114/MT115/MT32/MT65/MT110/MT100/MT32/MT76/MT97/MT116/MT99/MT104/MT101/MT115 /MT49/MT58/MT50/MT32/MT68/MT69/MT77/MT85/MT76/MT84/MT73/MT80/MT76/MT69/MT88/MT69/MT82 /MT68/MT56/MT66 /MT68/MT55/MT66 /MT68/MT54/MT66 /MT68/MT53/MT66 /MT68/MT52/MT66 /MT68/MT51/MT66 /MT68/MT50/MT66 /MT68/MT49/MT66 /MT68/MT48/MT66 /MT68/MT56/MT65 /MT68/MT55/MT65 /MT68/MT54/MT65 /MT68/MT53/MT65 /MT68/MT52/MT65 /MT68/MT51/MT65 /MT68/MT50/MT65 /MT68/MT49/MT65 /MT68/MT48/MT65 /MT68/MT56/MT66/MT32/MT40/MT79/MT86/MT82/MT41 /MT68/MT55/MT66/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT54/MT66 /MT68/MT53/MT66 /MT68/MT52/MT66 /MT68/MT51/MT66 /MT68/MT50/MT66 /MT68/MT49/MT66 /MT68/MT48/MT66/MT32/MT40/MT76/MT83/MT66/MT41 /MT68/MT56/MT65/MT32/MT40/MT79/MT86/MT82/MT41 /MT68/MT55/MT65/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT54/MT65 /MT68/MT53/MT65 /MT68/MT52/MT65 /MT68/MT51/MT65 /MT68/MT50/MT65 /MT68/MT49/MT65 /MT68/MT48/MT65/MT32/MT40/MT76/MT83/MT66/MT41 /MT68/MT82/MT65/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT65/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT69/MT77/MT85/MT88 /MT67/MT76/MT79/MT67/MT75 /MT66/MT85/MT70/MT70/MT69/MT82 /MT68/MT82/MT66/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT66/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT66/MT65/MT78/MT75/MT32/MT65 /MT66/MT65/MT78/MT75/MT32/MT66 BLOCK DIAGRAM

2 October 2002

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TEST TEST SPT7755A SPT7755B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Resolution 88 Bits DC Accuracy Integral Linearity Error (ILE) ƒ CLK = 100 kHz I –1.0 +1.0 –1.5 +1.5 LSB Differential Linearity Error (DLE) ƒ CLK = 100 kHz I –0.85 +0.95 –0.95 +1.5 LSB No Missing Codes Guaranteed Guaranteed Analog Input Input Voltage Range I V RB VRT VRB VRT V Input Bias Current V IN=0 V I .75 2.0 .75 2.0 mA Input Resistance V 15 15 k Ω Input Capacitance Over Full Input Range V 15 15 pF Input Bandwidth Small Signal V 900 900 MHz Large Signal V 500 500 MHz Offset Error V RT IV –30 +30 –30 +30 mV Offset Error VRB IV –30 +30 –30 +30 mV Input Slew Rate V5 5 V/ns Clock Synchronous Input Currents V 2 2 µA Reference Input Ladder Resistance I 60 80 60 80 Ω Reference Bandwidth V 30 30 MHz Timing Characteristics Maximum Sample Rate I 750 750 MHz Aperture Jitter V 2 2 ps Acquisition Time V 250 250 ps Dynamic Performance Signal-To-Noise Ratio (without Harmonics) ƒIN = 50 MHz I 46 44 dB ƒIN = 250 MHz I 44 42 dB Total Harmonic Distortion ƒIN = 50 MHz I –45 –43 dBc ƒIN = 250 MHz I –37 –35 dBc Signal-to-Noise and Distortion ƒIN = 50 MHz I 43 41 dB ƒIN = 250 MHz I 36 34 dB Supply Voltages Negative Supply Voltage (VEE TO GND) –7.0 to +0.5 V Input Voltage Output Temperature

3 October 2002

All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all test are pulsed tests; therefore, T J = TC = TA. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. VP arameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. ELECTRICAL SPECIFICATIONS TEST TEST SPT7755A SPT7755B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Dynamic Performance Spurious Free Dynamic Range ƒIN = 50 MHz I 48 44 dB ƒIN = 250 MHz I 40 36 dB Digital Inputs Input High Voltage Input Low Voltage Clock Pulse Width High (tPWH)I 0.67 0.5 0.67 0.5 ns Clock Pulse Width Low (tPWL)I 0.67 0.5 0.67 0.5 ns Digital Outputs Logic 1 Voltage I –1.1 –0.9 –1.1 –0.9 V Logic 0 Voltage I –1.8 –1.5 –1.8 –1.5 V Rise Time 20% to 80% V 450 450 ps Fall Time 20% to 80% V 450 450 ps Power Supply Requirements Current IEE I 1.05 1.2 1.05 1.2 A Power Dissipation I 5.5 6.25 5.5 6.25 W Typical Thermal Impedance: θJC = +4 °C/W.

4 October 2002

The SPT7755 is one of the fastest monolithic 8-bit parallel flash A/D converters available today. The nominal conver- sion rate is 750 MSPS and the analog bandwidth is in excess of 900 MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block diagram). This not only reduces clock transient kick- back to the input and reference ladder due to a low AC beta, but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabi- lize the input capacitance so that it remains constant over different input voltage and frequency ranges and therefore makes the part easier to drive than previous flash convert- ers. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to “trip” into or out of the active state. This gain reduces metastable states that can cause errors at the output. The SPT7755 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 Ω loads. Figure 1 – SPT7755 Typical Interface Circuit /MT53/MT48/MT32/MT87 /MT53/MT48/MT32/MT87 /MT86/MT73/MT78 /MT86/MT73/MT78 /MT86/MT82/MT84/MT70 /MT86/MT82/MT84/MT83 /MT42 /MT85/MT49 /MT43 /MT150 /MT50/MT50/MT32/MT87 /MT42 /MT85/MT49/MT43 /MT150/MT50/MT50/MT32/MT87 /MT150/MT53/MT46/MT50/MT32/MT86 /MT50/MT78/MT50/MT57/MT48/MT55 /MT86/MT82/MT66/MT83 /MT86/MT82/MT66/MT70 /MT53/MT48/MT32/MT87 /MT86/MT73/MT78/MT42/MT42 /MT150/MT50/MT46/MT48/MT32/MT86 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101 /MT67/MT111/MT110/MT118/MT101/MT114/MT116/MT85/MT50 /MT53/MT48/MT32/MT87 /MT150/MT50/MT32/MT86 /MT80/MT117/MT108/MT108/MT100/MT111/MT119/MT110 /MT40/MT65/MT110/MT97/MT108/MT111/MT103/MT41 /MT67/MT76/MT75 /MT67/MT76/MT75 /MT150/MT53/MT46/MT50/MT32/MT86 /MT86/MT69/MT69 /MT65/MT71/MT78/MT68 /MT68/MT71/MT78/MT68 /MT86/MT82/MT77 /MT68/MT56/MT66/MT32/MT40/MT79/MT86/MT82/MT41 /MT68/MT55/MT66/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT54/MT66 /MT68/MT53/MT66 /MT68/MT52/MT66 /MT68/MT51/MT66 /MT68/MT50/MT66 /MT68/MT49/MT66 /MT68/MT48/MT66/MT32/MT40/MT76/MT83/MT66/MT41 /MT68/MT56/MT65/MT32/MT40/MT79/MT86/MT82/MT41 /MT68/MT55/MT65/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT54/MT65 /MT68/MT53/MT65 /MT68/MT52/MT65 /MT68/MT51/MT65 /MT68/MT50/MT65 /MT68/MT49/MT65 /MT68/MT48/MT65/MT32/MT40/MT76/MT83/MT66/MT41 /MT150/MT50/MT46/MT48/MT32/MT86 /MT80/MT117/MT108/MT108/MT100/MT111/MT119/MT110 /MT40/MT68/MT105/MT103/MT105/MT116/MT97/MT108/MT41 /MT53/MT48/MT32/MT87 /MT46/MT49/MT32/MT181/MT70 /MT70/MT66/MT32/MT61/MT32 /MT70/MT101/MT114/MT114/MT105/MT116/MT101/MT32/MT98/MT101/MT97/MT100 /MT85/MT49 /MT61 /MT79/MT80/MT50/MT57/MT49/MT32/MT111/MT114/MT32/MT101/MT113/MT117/MT105/MT118/MT97/MT108/MT101/MT110/MT116/MT32/MT119/MT105/MT116/MT104/MT32/MT108/MT111/MT119/MT32/MT111/MT102/MT102/MT115/MT101/MT116/MT47/MT110/MT111/MT105/MT115/MT101/MT46 /MT82/MT61/MT49/MT32/MT107/MT87/MT59/MT32/MT48/MT46/MT49/MT37/MT32/MT109/MT97/MT116/MT99/MT104/MT101/MT100/MT46 /MT61/MT65/MT71/MT78/MT68 /MT61/MT68/MT71/MT78/MT68 /MT85/MT50 /MT61 /MT79/MT78/MT32/MT83/MT101/MT109/MT105/MT99/MT111/MT110/MT100/MT117/MT99/MT116/MT111/MT114/MT32/MT69/MT67/MT76/MT105/MT110/MT80/MT83/MT32/MT76/MT73/MT84/MT69/MT44/MT32/MT77/MT67/MT49/MT48/MT69/MT76/MT49/MT54/MT44 /MT100/MT105/MT102/MT102/MT101/MT114/MT101/MT110/MT116/MT105/MT97/MT108/MT32/MT114/MT101/MT99/MT101/MT105/MT118/MT101/MT114/MT32/MT119/MT105/MT116/MT104/MT32/MT50/MT53/MT48/MT32/MT112/MT115/MT32/MT40/MT116/MT121/MT112/MT41/MT32/MT112/MT114/MT111/MT112/MT97/MT103/MT97/MT116/MT105/MT111/MT110/MT32/MT100/MT101/MT108/MT97/MT121/MT46 /MT85/MT51 /MT61 /MT77/MT67/MT49/MT48/MT69/MT76/MT49/MT54/MT32/MT111/MT114/MT32/MT77/MT67/MT49/MT48/MT48/MT69/MT76/MT49/MT54/MT46 /MT42/MT32 /MT61 /MT49/MT48/MT32/MT181/MT70/MT32/MT84/MT97/MT110/MT116/MT97/MT108/MT117/MT109/MT32/MT67/MT97/MT112/MT97/MT99/MT105/MT116/MT111/MT114/MT32/MT97/MT110/MT100/MT32/MT48/MT46/MT49/MT32/MT181/MT70/MT32/MT67/MT104/MT105/MT112/MT32/MT67/MT97/MT112/MT97/MT99/MT105/MT116/MT111/MT114 /MT42/MT42/MT32 /MT61 /MT67/MT97/MT114/MT101/MT32/MT109/MT117/MT115/MT116/MT32/MT98/MT101/MT32/MT116/MT97/MT107/MT101/MT110/MT32/MT116/MT111/MT32/MT97/MT118/MT111/MT105/MT100/MT32/MT101/MT120/MT99/MT101/MT101/MT100/MT105/MT110/MT103/MT32/MT116/MT104/MT101/MT32/MT109/MT97/MT120/MT105/MT109/MT117/MT109/MT32/MT114/MT97/MT116/MT105/MT110/MT103 /MT102/MT111/MT114/MT32/MT116/MT104/MT101/MT32/MT105/MT110/MT112/MT117/MT116/MT44/MT32/MT101/MT115/MT112/MT101/MT99/MT105/MT97/MT108/MT108/MT121/MT32/MT100/MT117/MT114/MT105/MT110/MT103/MT32/MT112/MT111/MT119/MT101/MT114/MT32/MT117/MT112/MT32/MT115/MT101/MT113/MT117/MT101/MT110/MT99/MT105/MT110/MT103/MT32/MT111/MT102/MT32/MT116/MT104/MT101 /MT97/MT110/MT97/MT108/MT111/MT103/MT32/MT105/MT110/MT112/MT117/MT116/MT32/MT100/MT114/MT105/MT118/MT101/MT114/MT46 /MT82 /MT82 /MT42 /MT150/MT53/MT46/MT50/MT32/MT86 /MT70/MT66 /MT68/MT82/MT66 /MT68/MT82/MT66 /MT68/MT82/MT65 /MT68/MT82/MT65 /MT85/MT51 /MT85/MT51 /MT68/MT82/MT65/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT65/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT66/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT66/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT53/MT48/MT32/MT87 /MT150/MT50/MT46/MT48/MT32/MT86/MT32/MT80/MT117/MT108/MT108/MT100/MT111/MT119/MT110/MT32/MT40/MT68/MT105/MT103/MT105/MT116/MT97/MT108/MT41 /MT53/MT48/MT32/MT87

5 October 2002

The circuit in figure 1 is intended to show the most elabo- rate method of achieving the least error b y correcting for integral linearity, input induced distortion, and power sup- ply/ground noise. This is achieved by the use of e xternal reference ladder tap connections, input buffer, and supply decoupling. Please contact the f actory for the SPT7755 evaluation board application note that contains more details on interfacing the SPT7755. The function of each pin and e xternal connections to other components is as follows: VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a .01 µF ceramic capaci- tor. A 10 µF tantalum can also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and ap- propriately bypassed as shown in figure 1. VIN (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient dr ive capability. The pins can also be tied together and driven by the same source. The SPT7755 is superior to similar de- vices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has con- stant capacitance and induces less slew rate distortion. CLK, CLK (CLOCK INPUTS) The clock inputs are designed to be dr iven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. D0 TO D8, DR, DR, (A AND B) The digital outputs can dr ive 50 Ω to ECL le vels when pulled down to –2 V. When pulled down to –5.2 V, the out- puts can drive 130 Ω to 1 kΩ loads. All digital outputs are ommends using differential receivers on the outputs of the data ready lines to ensure the proper output r ise and fall times. VRBF, VRBS, VRTF, VRTS, VRM (REFERENCE INPUTS) There are two reference inputs and one external reference voltage tap. These are –2 V (VRB force and sense), mid- tap (VRM) and A GND (VRT force and sense). The refer- ence pins and tap can be driven by op amps as shown in figure 1 or VRM may be bypassed for limited temperature operation. These v oltage inputs can be b ypassed to AGND for further noise suppression if so desired. Table I – Output Coding VIN D8 D7 . . . D8 >–0.5 LSB 1 1 0 0 0 0 0 0 0 –0.5 LSB 1 1 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 –1.5 LSB 0 1 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1

  • • •
  • • •
  • • • –1.0 V 0 1 1 0 0 0 0 0 0 00 1 0 0 0 0 0 0
  • • •
  • • •
  • • • –2.0 V +0.5 LSB 0 0 0 0 0 0 0 0 1 00 0 0 0 0 0 0 0 <(–2.0 V +0.5 LSB) 0 0 0 0 0 0 0 0 0 Indicates the transition between the two codes THERMAL MANAGEMENT The typical thermal impedance is as follows: ΘCA = +17 °C/W in still air with no heat sink We highly recommend that a heat sink be used f or this device with adequate air flow to ensure rated performance of the de vice. We have found that a Thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal perfor- mance under laboratory tests. Application specific condi- tions should be tak en into account to ensure that the device is properly heat sinked. grey code with the coding as shown in table I. CADEKA rec-

6 October 2002

The SPT7755 has 256 preamp/comparator pairs which are each supplied with the voltage from VRT to VRB divided equally by the resistive ladder as shown in the block dia- gram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage ap- plied at V IN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one’s individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. When the CLK pin changes from low to high the comparators are latched to the state prior to the clock transition and output logic codes in se- quence from the top comparators, closest to V RT (0 V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decod- ers when the CLK is changed from high to low. At the out- put of the decoders is a set of four 7-bit latches which are enabled (“track”) when the clock changes from high to low. From here, the output of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. Figure 2 – Timing Diagram /MT86/MT73/MT78 /MT67/MT76/MT75 /MT67/MT76/MT75 /MT68/MT82/MT65 /MT68/MT82/MT65 /MT68/MT82/MT66 /MT68/MT82/MT66 /MT68/MT97/MT116/MT97/MT32/MT66/MT97/MT110/MT107/MT32/MT66 /MT78/MT45/MT49 /MT78/MT43/MT49 /MT78/MT43/MT51 /MT78 /MT78/MT43/MT49 /MT78/MT43/MT50 /MT78/MT43/MT51 /MT78/MT43/MT52 /MT78/MT43/MT53/MT78/MT43/MT54 /MT78/MT45/MT50 /MT78 /MT78/MT43/MT50 /MT78/MT43/MT52 /MT49/MT46/MT55/MT53/MT32/MT110/MT115 /MT116/MT121/MT112 /MT49/MT46/MT52/MT32/MT110/MT115 /MT116/MT121/MT112 /MT68/MT97/MT116/MT97/MT32/MT66/MT97/MT110/MT107/MT32/MT65 /MT50/MT46/MT48/MT32/MT110/MT115 /MT49/MT46/MT55/MT53/MT32/MT110/MT115 /MT116/MT121/MT112 /MT49/MT46/MT52/MT32/MT110/MT115 /MT116/MT121/MT112

7 October 2002

Figure 3 – Subcircuit Schematics Input Circuit Output Circuit Clock Input /MT65/MT71/MT78/MT68 /MT86/MT73/MT78 /MT86/MT69/MT69 /MT86/MT82 /MT65/MT71/MT78/MT68 /MT68/MT97/MT116/MT97/MT32/MT79/MT117/MT116 /MT68/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT67/MT76/MT75 /MT86/MT69/MT69 /MT67/MT76/MT75 PACKAGE OUTLINE 80-Lead MQuad /MT66 /MT70 /MT72 /MT32/MT73 /MT75 /MT65 /MT67 /MT68 /MT69 /MT74 /MT71 /MT32/MT76 /MT32/MT77 Inches Millimeters Symbol Min Max Min Max A 0.904 0.923 22.95 23.45 B 0.777 0.781 19.74 19.84 C 0.472 typ 12.00 typ D 0.541 0.545 13.74 13.84 E 0.667 0.687 16.95 17.45 F 0.031 typ 0.80 typ G 0.012 0.018 0.30 0.45 H 0.109 0.134 2.76 3.40 I 0.010 0.024 0.25 0.60 J 0.724 typ 18.40 typ K 0.099 0.110 2.51 2.80 L0 ° 7° 0° 7° M 0.029 0.041 0.73 1.03

8 October 2002

ORDERING INFORMATION

PART NUMBER DESCRIPTION TEMPERATURE RANGE PACKAGE SPT7755AIK ILE = 1.0 LSB –25 to +85 °C 80L MQuad SPT7755BIK ILE = 1.5 LSB –25 to +85 °C 80L MQuad PIN ASSIGNMENTS PIN FUNCTIONS NAME FUNCTION VEE Negative Supply Nominally –5.2 V AGND Analog Ground VRTF Reference Voltage Force Top, Nominally 0 V VRTS Reference Voltage Sense Top VRM Reference Voltage Middle, Nominally –1 V VRBF Reference Voltage Force Bottom, Nominally –2 V VRBS Reference Voltage Sense Bottom VIN Analog Input Voltage, Can Be Either Voltage or Sense DGND Digital Ground D0–D7A Data Output Bank A D0–D7B Data Output Bank B DRA Data Ready Bank A DRA Not Data Ready Bank A DRB Data Ready Bank B DRB Not Data Ready Bank B D8A Overrange Output Bank A D8B Overrange Output Bank B CLK Clock Input CLK Clock Input /MT68/MT71/MT78/MT68 /MT68/MT50/MT66 /MT68/MT51/MT66 /MT68/MT52/MT66 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT68/MT53/MT66 /MT68/MT71/MT78/MT68 /MT68/MT54/MT66 /MT68/MT71/MT78/MT68 /MT68/MT55/MT66 /MT68/MT56/MT66 /MT78/MT47/MT67 /MT78/MT47/MT67 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT86/MT82/MT66/MT70 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT86/MT82/MT66/MT83 /MT49/MT49 /MT49 /MT50 /MT51 /MT52 /MT53 /MT54 /MT55 /MT56 /MT57 /MT49/MT48 /MT49/MT50 /MT49/MT51 /MT49/MT52 /MT49/MT53 /MT49/MT54 /MT49/MT55 /MT49/MT56 /MT49/MT57 /MT50/MT48 /MT50/MT49 /MT50/MT50 /MT50/MT51 /MT50/MT52 /MT53/MT52 /MT54/MT52 /MT54/MT51 /MT54/MT50 /MT54/MT49 /MT54/MT48 /MT53/MT57 /MT53/MT56 /MT53/MT55 /MT53/MT54 /MT53/MT53 /MT53/MT51 /MT53/MT50 /MT53/MT49 /MT53/MT48 /MT52/MT57 /MT52/MT56 /MT52/MT55 /MT52/MT54 /MT52/MT53 /MT52/MT52 /MT52/MT51 /MT52/MT50 /MT52/MT49 /MT50/MT53 /MT50/MT54 /MT50/MT55 /MT50/MT56 /MT50/MT57 /MT51/MT48 /MT51/MT49 /MT51/MT50 /MT51/MT51 /MT51/MT52 /MT51/MT53 /MT51/MT54 /MT51/MT55 /MT51/MT56 /MT51/MT57 /MT52/MT48 /MT56/MT48 /MT55/MT57 /MT55/MT56 /MT55/MT55 /MT55/MT54 /MT55/MT53 /MT55/MT52 /MT55/MT51 /MT55/MT50 /MT55/MT49 /MT55/MT48 /MT54/MT57 /MT54/MT56 /MT54/MT55 /MT54/MT54 /MT54/MT53 /MT68/MT71/MT78/MT68 /MT78/MT47/MT67 /MT78/MT47/MT67 /MT68/MT51/MT65 /MT68/MT50/MT65 /MT86/MT69/MT69 /MT68/MT49/MT65 /MT68/MT71/MT78/MT68 /MT68/MT48/MT65 /MT68/MT71/MT78/MT68 /MT68/MT82/MT65 /MT68/MT82/MT65 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT67/MT76/MT75 /MT86/MT69/MT69 /MT67/MT76/MT75 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT86/MT82/MT84/MT83 /MT86/MT82/MT84/MT70 /MT78/MT47/MT67 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT78/MT47/MT67 /MT78/MT47/MT67 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT68/MT52/MT65 /MT68/MT53/MT65 /MT68/MT54/MT65 /MT68/MT71/MT78/MT68 /MT68/MT55/MT65 /MT68/MT71/MT78/MT68 /MT68/MT56/MT65 /MT68/MT71/MT78/MT68 /MT68/MT82/MT66 /MT68/MT71/MT78/MT68 /MT68/MT82/MT66 /MT68/MT71/MT78/MT68 /MT68/MT48/MT66 /MT68/MT49/MT66 /MT77/MT81/MT85/MT65/MT68 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT86/MT69/MT69 /MT86/MT73/MT78 /MT86/MT73/MT78 /MT86/MT82/MT77 /MT86/MT69/MT69 /MT86/MT69/MT69