SPT7730 CADEKA | Alldatasheet

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Technical content

8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER

FEATURES

  • 8-Bit, 1 kHz to 3.0 MSPS Analog-to-Digital Converter
  • Monolithic CMOS
  • Serial Output
  • Internal Sample-and-Hold
  • Analog Input Range: 0 to 2 V Nominal; 3.3 V Max
  • Power Dissipation (Excluding Reference Ladder) 45 mW at +5 V 16 mW at +3 V
  • Single Power Supply: +3 V to +5 V Range
  • High ESD Protection: 3,000 V Minimum

APPLICATIONS

  • Handheld and Desktop Scanners
  • DSP Interface Applications
  • Portable Digital Radios
  • Portable and Handheld Applications
  • Automotive Applications
  • Remote Sensing 8-Bit A/D Analog Input VREF+ Serial Output Logic Ground VDD SAR Clock Data Out Start Convert /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Track-and-Hold VREF- Timing And Control GENERAL DESCRIPTION verter delivers excellent high speed conversion performance with low cost and low power. The serial port protocol is compatible with the serial peripheral interface (SPI) or MICROWIRE™ industry standard, high-speed synchronous MPU interfaces. The large input bandwidth and fast transient response time allow for CCD applications operating up to 3.0 MSPS. The device can operate with a power supply range from +3 V to +5 V with very low power dissipation. The small package size makes this part excellent for handheld applications where board space is a premium. The SPT7730 is available in an 8-lead SOIC package over the commercial tempera- ture range. Contact the factory for availability of die and industrial temperature range versions. BLOCK DIAGRAM The CADEKA 8-bit, 3.0 MSPS, serial analog-to-digital con-

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC ELECTRICAL CHARACTERISTICS DC Performance Resolution 8 Bits Differential Linearity I ±0.2 ±0.5 LSB Integral Linearity I ±0.2 ±0.5 LSB No Missing Codes I Guaranteed Analog Input Input Voltage Range1 IV V REF- +4% V REF+ -6% V Input Resistance I 5 M Ω Input Capacitance IV 5 pF Input Bandwidth (Small Signal) IV 30 MHz Offset IV -2 +2 % of FSR Gain Error IV -2 +2 % of FSR Reference Input Resistance IV 250 280 350 Ω Voltage Range1 VREF-2 IV -4% 0 V REF+ -Δ V VREF+ 2 IV V REF-+Δ 2/3 VDD V VREF+ -VREF- (Δ) IV 1/10 V DD V Reference Settling Time IV 90 ns Timing Characteristics Maximum Conversion Rate I 3.0 1.0 MSPS Minimum Conversion Rate IV 1 kSPS Maximum External Clock Rate I 36 12 MHz Minimum External Clock Rate IV 12 kHz Aperture Delay Time IV 5 ns Aperture Jitter Time IV 5 ps Data Ouput LSB Hold Time T MIN to TMAX IV 6 8 ns 1Percentages refer to percent of [(VREF+ ) -(VREF-)] 2Δ = Minimum (VREF+ -VREF-) ABSOLUTE MAXIMUM RATING (Beyond which damage may occur) 1 Supply Voltages Input Voltages V Output Temperature Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Dynamic Performance Effective Number of Bits fIN = 500 kHz IV 7.5 Bits Signal-to-Noise Ratio fIN = 500 kHz IV 47 dB Harmonic Distortion fIN = 500 kHz IV 60 dB Power Supply Requirements3 +V DD Supply Voltage IV 3 5.5 V +V DD Supply Current V DD = 3.0 V IV 5.4 7 mA VDD = 5.0 V I 9 10 mA Power Dissipation V DD = 3.0 V IV 16 22 mW VDD = 5.0 V I 45 50 mW 3Excluding the reference ladder. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at T A=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaranteed over specified temperature range. TEST LEVEL I II III IV V VI

should be taken to ensure that the LSB is latched into an external latch with the proper amount of set and hold time. DATA OUTPUT CODING The coding of the output is straight binary. (See table I.) Table I - Data Output Coding ANALOG INPUT OUTPUT CODE D7 - DO +FS - 1/2 LSB 1111 1 1 1 Ø +1/2 FS Ø X X X XXXX +1/2 LSB OOOO OOOØ VREF- OOOO OOOO Ø indicates the flickering bit between logic O and 1. X indicates the flickering bit between logic 1 and O. ANALOG INPUT AND REFERENCE SETTLING TRACK AND HOLD TIMING Figure 9 shows the timing relationship between the input clock and SC versus the analog input tracking and reference settling. The analog input is tracked from the twelfth clock cycle of the previous conversion to the third clock cycle of the current conversion. On the falling edge of the third clock cycle, the analog input is held by the internal sample-and- hold. After this sample, the analog input may vary without affecting data conversion. The reference ladder inputs (VREF + and VREF -) may be changed starting on the falling edge of the eleventh clock cycle of the previous conversion and must be settled by the falling edge of the third clock cycle of the current conversion. (See figure 9.) VOLTAGE REFERENCE AND ANALOG INPUT The SPT7730 requires the use of a single external voltage reference for driving the high side of the reference ladder. The VREF + can be a maximum of 2/3 VDD . For example, if VDD = +5 V, then VREF + max = (2/3) * 5 V = +3.3 V. The lower side of the ladder is typically tied to AGND (0.0 V) but can be run up to a voltage that is 1/10th of VDD below VREF +: VREF - max. = VREF + - (1/10) * VDD . For example, if VDD = +5 V and VREF + = 3 V, then VREF - max. = 3 V - (1/10)* 5 V = 2.5 V. The +Full Scale (+FS) of the analog input is expected to be 6% of [(VREF +)-(VREF -)] below VREF + and the -Full Scale (-FS) of the analog input is expected to be 4% of [(VREF +) - (VREF -)] above VREF -. (See figure 1.) Therefore, Analog +FS = VREF + - 0.06 * [(VREF +) - (VREF -)], and Analog -FS = VREF - +0.04 * [(VREF +) - (VREF -)]. For example, if VREF + = 3 V and VREF - = 0 V, then Analog + FS = 3 V - 0.06 * [3 V- 0 V ] = 2.82 V, and Analog - FS = 0 V + 0.04 * [3 V - 0 V] = 0.12 V. GENERAL DESCRIPTION AND OPERATION The SPT7730 is an 8-bit analog-to-digital converter that uses a successive approximation architecture to perform data conversion. Each conversion cycle is 12 clocks in length. When the Not Start Convert (SC ) line is held low, conversion begins on the next rising edge of the input clock. When the conversion cycle begins, the data output pin is forced low until valid data output begins. The first two clock cycles are used to perform internal offset calibrations and to track the analog input. The analog input is then sampled using an internal track-and-hold amplifier on the falling edge of the third clock cycle. On clock cycles 4 through 12, an 8-bit successive approximation conversion is performed, and the data is output starting with the MSB. Serial data output begins with output of the MSB. See the Data Output Timing section for details. Each bit of the data conversion is sequentially determined and placed on the data output pin at the clock rate. This process continues until the LSB has been determined and output. At this point, if the SC line is high, the data output pin will be forced into a high impedance state, and the converter will go into an idle state waiting for the SC line to go low. This is referred to as Single Shot Mode. See Modes of Operation for details. If the SC is either held low through the entire 12 clock conversion cycle (free run mode) or is brought low prior to the trailing edge of the twelfth clock cycle (synchronous mode), the data output pin goes low and stays low until valid data output begins. Because the chip has either remained se- lected in the free run mode or has been immediately selected again in the synchronous mode, the next conversion cycle begins immediately after the twelfth clock cycle of the previ- ous conversion. See Modes of Operation for details. TYPICAL INTERFACE CIRCUIT CLOCK INPUT The SPT7730 requires a 50% ±10 % duty cycle clock running at 12 times the desired sample rate. The clock may be stopped in between conversion cycles without degradation of operation (single shot type of operation), however, the clock should remain running during a conversion cycle. POWER SUPPLY The SPT7730 requires only a single supply and operates capacitor be placed as close as possible to the supply pin. DATA OUTPUT SET UP AND HOLD TIMING As figure 8 shows, all of the data output bits (except the LSB) remains valid for a duration equivalent to one clock period and delayed by 8 ns after the falling edge of clock. Because the data converter enters into a next conversion ready state at the leading edge of clock 12, the LSB bit is valid for a duration equivalent to only the clock pulse width low and delayed by 8 ns after the falling edge of clock. Care from 3.0 V to 5.0 V. CADEKA recommends that a 0.01 µF chip

Figure 9 - Analog Input Track-and-Hold Timing and Reference Settling-and-Hold Timing PACKAGE OUTLINE 8-Lead SOIC A B C D E FG H I J K INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.187 0.194 4.80 4.98 B 0.228 0.242 5.84 6.20 C 0.050 typ 1.27 typ D 0.014 0.019 0.35 0.49 E 0.005 0.010 0.13 0.25 F 0.060 0.067 1.55 1.73 G 0.055 0.060 1.40 1.55 H 0.149 0.156 3.81 3.99 I0 ° 8° 0° 8° J 0.007 0.010 0.19 0.25 K 0.016 0.035 0.41 0.89 Ref Hold Ref Settling Window** Synchronous Mode* Single Shot Mode (SC high, no B cycle) Free Run Mode (SC always Ø) A A A A A A B B B B Sample Input Sample Input SC Clock VREF+ AIN *The rising edge of the SC line can occur any time between the rising edge of clock 1A and the falling edge of clock 12A. The reference settling window can be extended in the synchronous mode by adding extra clocks between conversion cycles. The example shown is the minimum number of clocks required (12) per conversion cycle.

PIN ASSIGNMENTS PIN FUNCTIONS Name Function Analog In Analog Signal Input Start Convert Start Convert. A high-to-low transition on this input begins the conversion cycle and enables serial data output. Clock Clock that drives A/D conversion cycle and the synchronous serial data output Data Out Serial Data. Tri-state serial data output for the A/D result driven by the CLOCK input External VREF + External voltage reference for top of reference ladder External VREF - External voltage reference for bottom of reference ladder VDD Analog and Digital +3 V to +5 V Power Supply Input GND Analog and Digital Ground Data Out External VREF + Analog In External VREF - Ground VDD Clock Start Convert

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE SPT7730SCS 0 to +70 °C 8L SOIC SPT7730SCU* +25 °C Die* *Please see the die specification for guaranteed electrical performance.