SPT7722 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

  • TTL/CMOS/PECL input logic compatible
  • High conversion rate: 250 MSPS
  • Single +5V power supply
  • V ery low power dissipation: 425mW
  • 350 MHz full power bandwidth
  • Power-down mode: 24mW
  • +3.0V/+5.0V (LVCMOS) digital output logic compatibility
  • Single/demuxed output ports selectable
  • Improved replacement for AD9054

Applications

  • RGB video processing
  • Digital communications
  • High-speed instrumentation
  • Digital Sampling Oscilloscopes (DSO)
  • Projection display systems

Description

The SPT7722 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. It is a performance-enhanced version of the SPT7721, offering better linearity and dynamic performance. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 425mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5V common mode reference is provided on chip for the single-ended input mode to minimize external components. The SPT7722 digital outputs are demuxed (double-wide) with both dual-channel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0V and +5.0V compatible. The SPT7722 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40°C to +85°C. SPT7722 8-bit, 250 MSPS A/D Converter with Demuxed Outputs www.fairchildsemi.com Rev. 1.0.2 December 2002 Block Diagram /MT56/MT45/MT66/MT105/MT116 /MT50/MT53/MT48/MT32/MT77/MT83/MT80/MT83 /MT65/MT68/MT67 /MT67/MT76/MT75 /MT67/MT76/MT75 /MT68/MT66/MT48/MT150/MT68/MT66/MT55 /MT67/MT111/MT109/MT109/MT111/MT110/MT32/MT77/MT111/MT100/MT101 /MT86/MT111/MT108/MT116/MT97/MT103/MT101 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101 /MT43/MT50/MT46/MT53/MT32/MT86 /MT32/MT86/MT67/MT77 /MT65/MT86/MT67/MT67 /MT79/MT86/MT68/MT68/MT65/MT71/MT78/MT68/MT68/MT71/MT78/MT68 /MT68/MT65/MT48/MT150/MT68/MT65/MT55 /MT80/MT68 /MT67/MT76/MT75/MT67/MT76/MT75/MT82/MT101/MT115/MT101/MT116 /MT38 /MT86/MT73/MT78/MT43 /MT68/MT97/MT116/MT97/MT32/MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT76/MT97/MT116/MT99/MT104/MT101/MT115 /MT86/MT73/MT78/MT150 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT68/MT97/MT116/MT97/MT32/MT79/MT117/MT116/MT112/MT117/MT116 /MT77/MT111/MT100/MT101/MT32/MT67/MT111/MT110/MT116/MT114/MT111/MT108 /MT68/MT77/MT79/MT68/MT69/MT49/MT44/MT50 /MT50/MT50 /MT82/MT101/MT115/MT101/MT116

2 Rev. 1.0.2 December 2002 Absolute Maximum Ratings (beyond which damage may occur)1 25°C Parameter Min. Max. Unit Supply Voltages AVCC +6 V OVDD +6 V Input Voltages Analog Inputs -0.5 V CC +0.5 V Digital Inputs -0.5 V CC +0.5 V Temperature Operating Temperature -40 +85 °C Storage Temperature -65 +125 °C Note: 1. Operation at any absolute maximum rating is not implied. See Electrical Specifications table for proper nominal applied conditions in typical applications. Electrical Specifications (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) Parameter Conditions Test Min. Typ. Max. Unit Level Resolution 8 bits DC Performance (ƒIN = 1kHz) Differential Linearity Error (DLE) +25°C VI -0.68 ±0.4 0.68 LSB -40°C to +85°C IV -0.95 ±0.7 0.95 LSB Integral Linearity Error (ILE) +25°C VI ±1.2 ±1.90 LSB -40°C to +85°C IV ±1.4 ±2.15 LSB No Missing Codes @250 MSPS VI Guaranteed Analog Input Input Voltage Range with respect to V IN-V ± 5 1 2 m V pp Input Common Mode (VCM)I V 2.0 2.5 3.0 V Input Bias Current +25°C V 13 µA Input Resistance +25°C V 50 k Ω Input Capacitance +25°C V 5 pF Input Bandwidth +25°C (–3 dB of FS) V 350 MHz Gain Error +25°C VI -7.5 +3.5 %FS Offset Error +25°C VI -5 +5 LSB Offset Power Supply Rejection Ratio AVCC = 5V ±0.25V V <1 LSB Timing Characteristics Conversion Rate IV 25 250 MSPS Output Delay (Clock-to-Data) (tpd1) -40°C to +85°C IV 7.0 8 9.4 ns Output Delay Tempco V 16 ps/°C Aperture Delay Time (tap)V 0.3 ns Aperture Jitter Time V 2.0 ps-RMS NOTE: All electrical characteristics are subject to the following condition: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actual ly performed during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.

Rev. 1.0.2 December 2002 3 Electrical Specifications (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) Parameter Conditions Test Min. Typ. Max. Unit Level Pipeline Delay (Latency) Single Channel Mode V 2.5 Cycle Demuxed Interleaved Mode V 2.5 Cycle Demuxed Parallel Mode Channel B V 2.5 Cycle Channel A V 3.5 Cycle CLK to DCLKOUT Delay Time Single Channel Mode (tpd2)I V 5.0 5.18 5.3 ns Dual Channel Mode (tpd3)I V 5.6 5.73 5.9 ns Output Delay (Clock to DClock) V 18.1 ps/°C Dynamic Performance Effective Number of Bits (ENOB) ƒIN = 70MHz +25°C VI 6.4 7.0 Bits ƒIN = 70MHz -40°C to +85°C IV 6.25 6.8 Bits Signal-to-Noise Ratio (SNR) ƒIN = 70MHz +25°C VI 44.3 46.1 dB ƒIN = 70MHz -40°C to +85°C IV 42.6 45.4 dB Total Harmonic Distortion (THD) ƒIN = 70MHz +25°C VI -47 -41.5 dB ƒIN = 70MHz -40°C to +85°C IV -45.5 -40.3 dB Signal-to-Noise & Distortion(SINAD) ƒIN = 70MHz +25°C VI 40.2 43.7 dB ƒIN = 70MHz -40°C to +85°C IV 39.3 42.8 dB Power Supply Requirements AVCC Voltage (Analog Supply) IV 4.75 5.0 5.25 V OVDD Voltage (Digital Supply) IV 2.75 5.25 V AVCC Current VI 85 110 mA AVCC Current Powerdown +25°C VI 4.8 5.5 mA OVDD Current OV DD = 3.0V, 10pF load Single Mode V 35 mA Parallel Mode V 55 mA Interleave Mode V 55 mA Power Dissipation VI 425 550 mW Common Mode Reference Output Voltage VI 2.44 2.5 2.56 V Voltage Tempco V 84 ppm/°C Output Impedance I OUT = ±50 µAV 1 . 07 k Ω Power Supply Rejection Ratio V 47.5 mV/V NOTE: All electrical characteristics are subject to the following condition: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actual ly performed during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.

4 Rev. 1.0.2 December 2002 Electrical Specifications (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) Parameter Conditions Test Min. Typ. Max. Unit Level Clock and Reset Inputs (Diff & Single-Ended) Diff Signal Amplitude (VDIFF)I V 400 mV pp Diff High Input Voltage (VIHD)I V 1.4 AV CC V Diff Low Input Voltage (VILD)I V 0 3.9 V Diff Common Mode Input (VCMD)I V 1.2 4.1 V SE High Input Voltage (VIH)I V 1.8 V SE Low Input Voltage (VIL)I V 0 1.2 V Input Current High (IIH)V ID = 1.5V VI –100 43 +100 µA Input Current Low (IIL)V ID = 1.5V VI –100 43 +100 µA Power Down & Mode Control Inputs(Single-Ended) High Input Voltage IV 2.0 AV CC V Low Input Voltage IV 0 1.0 V Max Input Current Low VI –100 0.5 +100 µA Max Input Current High <4.0V VI –100 50 +100 µA Digital Outputs Logic “1” Voltage I OH = -0.5mA VI OV DD-0.2 V Logic “0” Voltage I OL = +1.6mA VI 0.2 V TR/TF Data 10pF load OVDD = 3V V 3.3/3.0 ns OVDD = 5V V 2.3/1.9 ns TR/TF DCLK 10pF load OVDD = 3V V 1.2/1.0 ns OVDD = 5V V 0.7/0.6 ns NOTE: All electrical characteristics are subject to the following condition: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actual ly performed during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL CODES: Level Test Procedure I 100% production tested at the specified temperature. II 100% production tested at T A = +25°C and sample tested at the specified temperatures. II QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characterization data. VP arameter is a typical value for information purposes only. VI 100% production tested at T A = +25°C. Parameter is guaranteed over specific temperature range.

Typical Operating Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) DLE vs. Sample Rate 0.7 0.1 0.0 -0.2 -0.5 LSB -0.3 -0.4 -0.6 -0.7 -0.1 0.2 0.3 0.4 0.5 0.6 200 225 250 260 Sample Rate (MSPS) ƒIN = 70.1 MHz DLE vs. Temperature -50 -25 25 75 100 0.8 0.1 0.0 -0.2 -0.5 Temperature (°C) LSB 05 0 -0.3 -0.4 -0.6 -0.7 -0.1 0.2 0.3 0.4 0.5 0.6 0.7 ƒIN = 70.1MHz ƒS = 250 MSPS DLE vs. AVCC 0.7 0.1 0.0 -0.2 -0.5 Volts LSB -0.3 -0.4 -0.6 -0.7 -0.1 0.2 0.3 0.4 0.5 0.6 ƒIN = 70.1MHz ƒS = 250 MSPS AVCC Current vs. Temperature -50 -25 0 50 100 100 Temperature (°C) AVCC Current (mA) 25 75 Powerdown mode ƒIN = 70.1MHz ƒS = 250 MSPS SNR, SINAD vs. Sample Rate 200 225 250 260 Sample Rate (MSPS) SNR, SINAD (dB) SINAD SNR ƒIN = 70.1 MHz SFDR, THD vs. Sample Rate 200 225 250 260 Sample Rate (MSPS) -30 -40 -50 -60 -70 SFDR, THD (dB) -35 -45 -55 -65 SFDR THD ƒIN = 70.1 MHz SNR, SINAD vs. Temperature Temperature (°C) SNR, SINAD (dB) SINAD SNR -50 -25 05 0 10025 75 ƒIN = 70.1 MHz ƒS = 250 MSPS THD vs. Temperature -30 -40 -50 -60 -70 Temperature (°C) THD (dB) -35 -45 -55 -65 -50 -25 05 0 10025 75 ƒIN = 70.1 MHz ƒS = 250 MSPS Rev. 1.0.2 December 2002 5

Typical Operating Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) SNR, SINAD vs. Duty Cycle % Duty Cycle SNR SINAD 35 40 50 55 60 45 ƒIN = 70.1 MHz ƒS = 250 MSPS SNR, SINAD (dB) -30 -40 -50 -60 -70 SFDR, THD vs. Duty Cycle % Duty Cycle SFDR, THD (dB) -35 -45 -55 -65 35 40 50 55 60 45 ƒIN = 70.1 MHz ƒS = 250 MSPS THD SFDR SNR, SINAD vs. AVCC Volts SNR, SINAD (dB) SNR SINAD ƒIN = 70.1 MHz ƒS = 250 MSPS -30 -40 -50 -60 -70 THD vs. AVCC Volts THD (dB) -35 -45 -55 -65 ƒIN = 70.1 MHz ƒS = 250 MSPS 6 Rev. 1.0.2 December 2002

THAs in series at the input, followed by three ADC blocks. through cancellation devices. reference ladder which also sets the full-scale input range. quarter and three-quarter scale, overrange, and underrange. polators that are latched one full clock cycle after the MSBs. bits at a time are decoded in any half clock cycle.

  • All data on bank A with clock rate limited to one-half maximum
  • Interleaved mode with data alternately on banks A and B on alternate clock cycles
  • Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can synchro- nize with the divided clock to select the desired output bank via the differential RESET input. The output logic family is CMOS with output OV DD supply adjustable from 2.7V to 5.25V . There are also differential clock output pins that can be used to latch the output data in single bank mode or to indicate the current output bank in demux mode. Finally, a power-down mode is available, which causes the outputs to become tri-state, and overall power is reduced to about 24mW. There is a 2V reference to supply common mode for single-ended inputs that is not shut down in power- down mode. VIN N–1N–2N–3 N CLK CLK D0–D7 (Bank A) DCLKOUT DCLKOUT N+2

2.5 CLK Cycles

Figure 1. Single Mode Timing Diagram

Figure 2. Dual Mode Timing Diagram

Figure 6. DC-Coupled Single-Ended to Differential All I/O pads are protected with an on-chip protection circuit. the typical interface circuit and as close to the ADC as possible. function. This function is controlled by the signal on pin PD. down mode the SPT7722 dissipates 24mW typically. tap of the RF transformer in fully differential applications. external 0.01µF capacitor, as shown in Figure 3. becomes an important consideration. output format is straight binary (table 1). Table 1. Output Data Format describes the mode switching options. Table 2. Output Data Modes

Rev. 1.0.2 December 2002 11 Pin Assignments Pin Definitions Pin Name Pin Number Pin Function Description VIN+4 0N on-Inverted Analog Input; nominally 1 VPP; 100k pullup to VCC and 100k pulldown to AGND, internally VIN-3 9I nverted Analog Input; nominally 1 VPP; 100k pullup to VCC and 100k pulldown to AGND, internally DA0–DA7 16–9 Data Output Bank A; 3V/5V LVCMOS compatible DB0–DB7 19–26 Data Output Bank B; 3 V/5V LVCMOS compatible DCLKOUT 28 Non-Inverted Data Output Clock; 3V/5V LVCMOS compatible DCLKOUT 27 Inverted Data Output Clock; 3V/5V LVCMOS compatible CLK 4 Non-Inverted Clock Input Pin; 100k pulldown to AGND, internally CLK 3 Inverted Clock Input Pin; 17.5k pullup to V CC and 7.5k pulldown to AGND, internally RESET 5 RESET synchronizes the data sampling and data output bank relationship when in Dual Channel Mode (DMODE1 = 0); 100k pulldown to AGND, internally RESET 6 Inverted RESET Input Pin; 17.5k pullup to V CC and 7.5 pulldown to AGND, internally DMODE1,2 32, 31 Internally: 100k pulldown to AGND on DMODE1 50k pullup to VCC on DMODE2 Data Output Mode Pins: DMODE1 = 0, DMODE2 = 0: Parallel Dual Channel Output DMODE1 = 0, DMODE2 = 1: Interleaved Dual Channel Output DMODE1 = 1, DMODE2 = X: Single Channel Data Output on Bank A (125 MSPS max) PD 2 Power Down Pin; PD = 1 for power-down mode. Outputs set to high impedance in power-down mode; 100k pulldown to AGND, internally VCM 37 2.5V Common Mode Voltage Reference Output AVCC 35, 36, 42, 43 +5V Analog Supply OVDD 7, 17, 30 +3V/+5V Digital Output Supply AGND 1, 33, 34, Analog Ground 38, 41, 44 DGND 8, 18, 29 Digital Ground 2123 AGND PD CLK RESET DGND OVDD DA6 DA7 (MSB) DA5 DA4 DA3 DA0 (LSB) OVDD DGND DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB7 (MSB) DB6 DGND AGND OVDD DMODE2 VIN+ VCM AVCC AGND AGND SPT7722 TOP VIEW 44L TQFP DA2 DA1 DCLKOUT DMODE1 AVCC VIN– AGND AGND AVCC AVCC CLK RESET DCLKOUT

www.fairchildsemi.com © 2002 Fairchild Semiconductor Corporation DATA SHEET SPT7722 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHE R DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgicalimplant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Ordering Information

SPT7722 SPT7722SIT TQFP-44 Temperature range for all parts: -40°C to +85°C. Index C D PIN1 E F G H I J K A B TQFP-44 INCHES MILLIMETERS SYMBOL MIN TYP MAX MIN TYP MAX A 0.472 12.00 B 0.394 10.00 C 0.394 10.00 D 0.472 12.00 E 0.031 0.80 F 0.012 0.018 0.300 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.018 0.030 0.45 0.75 J 0.039 1.00 K 0-7° 0-7° Package Dimensions