SPT7721 CADEKA | Alldatasheet

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8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS TECHNICAL D ATA NO VEMBER 8, 2001 GENERAL DESCRIPTION The SPT7721 is a high-speed, 8-bit analog-to-digital con- verter implemented in an advanced BiCMOS process. An advanced folding and interpolating architecture provides both a high conversion rate and very low pow er dissipation of only 310 mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5 V com- mon mode reference is provided on chip for the single- ended input mode to minimize external components. The SPT7721 digital outputs are demuxed (double-wide) with both dual-channel and single-channel selectable out- put modes. Dem uxed mode suppor ts either parallel aligned or interleaved data output. The output logic is both +3.0 V and +5.0 V compatible. The SPT7721 is available in a 44-lead TQFP surface mount package over the industrial temperature range of –40 to +85 °C. APPLICA TIONS RGB video processing Digital communications High-speed instrumentation Projection display systems FEA TURES TTL/CMOS/PECL compatible High conversion rate: 250 MSPS Single +5 V pow er supply Very low pow er dissipation: 310 mW Pow er-down mode +3.0 V/+5.0 V (LVCMOS) digital output logic compatibility Dem uxed output ports /MT56/MT45/MT66/MT105/MT116 /MT50/MT53/MT48/MT32/MT77/MT83/MT80/MT83 /MT65/MT68/MT67 /MT67/MT76/MT75/MT67/MT76/MT75 /MT68/MT66/MT48/MT150/MT68/MT66/MT55 /MT67/MT111/MT109/MT109/MT111/MT110/MT32/MT77/MT111/MT100/MT101 /MT86/MT111/MT108/MT116/MT97/MT103/MT101 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101 /MT43/MT50/MT46/MT53/MT32/MT86 /MT32/MT86/MT67/MT77 /MT65/MT86/MT67/MT67 /MT79/MT86/MT68/MT68/MT65/MT71/MT78/MT68/MT68/MT71/MT78/MT68 /MT68/MT65/MT48/MT150/MT68/MT65/MT55 /MT80/MT68/MT67/MT76/MT75/MT67/MT76/MT75/MT82/MT101/MT115/MT101/MT116 /MT38 /MT86/MT73/MT78/MT43 /MT68/MT97/MT116/MT97/MT32/MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT76/MT97/MT116/MT99/MT104/MT101/MT115 /MT86/MT73/MT78/MT150 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT68/MT97/MT116/MT97/MT32/MT79/MT117/MT116/MT112/MT117/MT116 /MT77/MT111/MT100/MT101/MT32/MT67/MT111/MT110/MT116/MT114/MT111/MT108 /MT68/MT77/MT79/MT68/MT69/MT49/MT44/MT50 /MT50/MT50 /MT82/MT101/MT115/MT101/MT116 BLOCK DIA GRAM

TA = TMIN to TMAX , AVCC = +5.0 V, ƒCLK = 250 MHz, VCM = 2.5 V, OVDD = 5.0 V, unless otherwise specified. TEST TEST SPT7721 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 8 Bits DC Performance ƒIN = 1 kHz Differential Linearity Error (DLE) +25 °C V –0.70/+1.05 LSB Integral Linearity Error (ILE) +25 °C V ±1.7 LSB Best Fit –40 °C to +85 °C V ±2.25 LSB No Missing Codes +25 °C, ƒ IN = 1 kHz I Guaranteed Analog Input Input Voltage Range (with respect to VIN–) +25 °C V ±470 mV P-P Gain Variation VI 2 % Input Common Mode (VCM ) IV 2.3 2.5 3.0 V Input Bias Current VI 10 µA Input Resistance +25 °C V 50 k Ω Input Capacitance +25 °C V 4 pF Input Bandwidth +25 °C (–3 dB of FS) V 220 MHz Offset Error VI ±10 mV Offset Power Supply Rejection Ratio V 0.5 mV/V Timing Characteristics Maximum Conversion Rate VI 250 MSPS Output Delay (Clock-to-Data) (tpd1) –40 °C to +85 °C IV 6 8 10.5 ns Output Delay Tempco V 22 ps/°C Aperture Delay Time (t ap) IV 0.5 ns Aperture Jitter Time IV 2 ps rms Pipeline Delay (Latency) Single Channel Mode V 2.5 Clocks Demuxed Interleaved Mode V 2.5 Clocks Demuxed Parallel Mode Channel B V 2.5 Clocks Channel A V 3.5 Clocks CLK to DCLKOUT Delay Time Single Channel Mode (tpd2) I V 467 n s Dual Channel Mode (tpd3) IV 5.3 6.16 7.8 ns Dynamic Performance Effective Number of Bits (ENOB) ƒIN = 70 MHz +25 °C VI 5.8 6.4 Bits ƒIN = 70 MHz –40 °C to +85 °C IV 5.5 6.0 Bits Signal-to-Noise Ratio (SNR) ƒIN = 70 MHz +25 °C VI 42 43 dB ƒIN = 70 MHz –40 °C to +85 °C IV 36 40 dB Temperatures Supply Voltages Input Voltages Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper applied conditions in typical applications. ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C

All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX , AVCC = +5.0 V, ƒCLK = 250 MHz, VCM = 2.5 V, OVDD = 5 V, unless otherwise specified. TEST TEST SPT7721 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Dynamic Performance Total Harmonic Distortion (THD) ƒIN = 70 MHz +25 °C VI –43 –40 dB ƒIN = 70 MHz –40 °C to +85 °C IV –42 –37 dB Signal-to-Noise and Distortion (SINAD) ƒIN = 70 MHz +25 °C VI 37 40 dB ƒIN = 70 MHz –40 °C to +85 °C IV 35 38 dB Power Supply Requirements AV CC Voltage (Analog Supply) IV 4.75 5.0 5.25 V OV DD Voltage (Digital Supply) IV 2.75 5.25 V AV CC Current VI 62 70 mA Power Dissipation with Internal Voltage Reference VI 310 350 mW Common Mode Reference Voltage VI 2.45 2.5 2.55 V Voltage Tempco V 100 ppm/°C Output Impedance I OUT = ±50 µA V 1 k Ω Power Supply Rejection Ratio V 63 mV/V Clock and Reset Inputs (Differential and Single-Ended) Differential Signal Amplitude (VDIFF) VI 400 mV P-P Differential High Input Voltage (VIHD) IV 1.4 5 V Differential Low Input Voltage (VILD) IV 0 3.9 V Differential Common-Mode Input (VCMD) IV 1.2 4.1 V Single-Ended High Input Voltage (VIH) IV 1.8 V Single-Ended Low Input Voltage (VIL) IV 1.2 V Input Current High (IIH) VID = 1.5 V VI –100 20 +100 µA Input Current Low (IIL) VID = 1.5 V VI –100 20 +100 µA Power Down and Mode Control Inputs (Single-Ended) High Input Voltage IV 2.0 AV CC V Low Input Voltage IV 0 1.0 V Maximum Input Current Low VI –100 10 +100 µA Maximum Input Current High <4.0 V VI –100 10 +100 µA Digital Outputs Logic "1" Voltage I OH = –0.5 mA VI OV DD – 0.2 OVDD – 0.06 V Logic "0" Voltage I OL = +1.6 mA VI 0.13 0.2 V TR /TF Data 10 pF load OV DD = 3 V V 3.5 ns OV DD = 5 V V 2.0 ns TR /TF DCLK = (10 pF load) OV DD = 3 V V 1.3 ns OV DD = 5 V V 0.7 ns LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range.

TYPICAL PERFORMANCE CHARACTERISTICS AC Performance vs Temperature /MT150/MT52/MT48/MT150/MT50/MT48/MT48 /MT50/MT48/MT52/MT48/MT54/MT48 /MT56/MT48 /MT51/MT53 /MT52/MT48 /MT52/MT53 /MT53/MT48 /MT53/MT53 /MT54/MT48 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT40/MT176/MT67/MT41 /MT83/MT70/MT68/MT82 /MT150/MT84/MT72/MT68 /MT83/MT78/MT82 /MT51/MT48 /MT49/MT48/MT48 /MT83/MT70/MT68/MT82/MT44/MT32/MT150/MT84/MT72/MT68/MT44/MT32/MT83/MT78/MT82/MT44/MT32/MT83/MT73/MT78/MT65/MT68/MT32/MT40/MT100/MT66/MT41 /MT83/MT73/MT78/MT65/MT68 /MT131/MT73/MT78/MT32/MT61/MT32/MT55/MT48/MT32/MT77/MT72/MT122 /MT48 /MT51/MT53 /MT52/MT48 /MT52/MT53 /MT53/MT48 /MT53/MT53 /MT54/MT48 /MT83/MT97/MT109/MT112/MT108/MT101/MT32/MT82/MT97/MT116/MT101/MT32/MT40/MT77/MT83/MT80/MT83/MT41 /MT51/MT48 /MT83/MT70/MT68/MT82/MT44/MT32/MT83/MT78/MT82/MT44/MT32/MT150/MT84/MT72/MT68/MT44/MT32/MT83/MT73/MT78/MT65/MT68/MT32/MT40/MT100/MT66/MT41 /MT53/MT48/MT49/MT48/MT48/MT49/MT53/MT48/MT50/MT48/MT48/MT50/MT53/MT48 /MT51/MT48/MT48 /MT83/MT73/MT78/MT65/MT68 /MT83/MT78/MT82 /MT150/MT84/MT72/MT68 /MT83/MT70/MT68/MT82 /MT131/MT73/MT78/MT32/MT61/MT32/MT55/MT48/MT32/MT77/MT72/MT122 AC Performance vs Sample Rate AV CC Current vs Temperature /MT150/MT52/MT48/MT150/MT50/MT48/MT48 /MT50/MT48/MT52/MT48/MT54/MT48 /MT56/MT48 /MT53/MT48 /MT53/MT53 /MT54/MT48 /MT54/MT53 /MT55/MT48 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT40/MT176/MT67/MT41 /MT52/MT53 /MT49/MT48/MT48 /MT65/MT86/MT67/MT67/MT32/MT40/MT109/MT65/MT41 /MT55/MT53 AV CC Current Power Down vs Temperature /MT150/MT52/MT48/MT150/MT50/MT48/MT48 /MT50/MT48/MT52/MT48/MT54/MT48 /MT56/MT48 /MT50/MT46/MT50 /MT50/MT46/MT52 /MT50/MT46/MT54 /MT50/MT46/MT56 /MT51/MT46/MT48 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT40/MT176/MT67/MT41 /MT50/MT46/MT48 /MT49/MT48/MT48 /MT65/MT86/MT67/MT67/MT32/MT40/MT109/MT65/MT41 Voltage Offset Error vs Temperature Percent Gain Error vs Temperature /MT150/MT52/MT48/MT150/MT50/MT48/MT48 /MT50/MT48/MT52/MT48/MT54/MT48 /MT56/MT48 /MT150/MT52/MT46/MT48 /MT150/MT50/MT46/MT48 /MT48/MT46/MT48 /MT50/MT46/MT48 /MT52/MT46/MT48 /MT54/MT46/MT48 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT40/MT176/MT67/MT41 /MT150/MT54/MT46/MT48 /MT49/MT48/MT48 /MT109/MT86 /MT150/MT52/MT48/MT150/MT50/MT48/MT48 /MT50/MT48/MT52/MT48/MT54/MT48 /MT56/MT48 /MT49/MT46/MT48/MT49 /MT49/MT46/MT48/MT50 /MT49/MT46/MT48/MT51 /MT49/MT46/MT48/MT52 /MT49/MT46/MT48/MT53 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT40/MT176/MT67/MT41 /MT49/MT46/MT48/MT48 /MT49/MT48/MT48 /MT37 /MT49/MT46/MT48/MT54

TYPICAL PERFORMANCE CHARACTERISTICS Input Bandwidth Common-Mode Reference Voltage vs V CC /MT48 /MT150/MT50 /MT150/MT49 /MT48 /MT49 /MT73/MT110/MT112/MT117/MT116/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT150/MT51/MT100/MT66 /MT49/MT48/MT48/MT50/MT48/MT48/MT51/MT48/MT48/MT52/MT48/MT48/MT53/MT48/MT48 /MT54/MT48/MT48 /MT150/MT52 /MT150/MT53 /MT52/MT46/MT53 /MT50/MT46/MT52/MT50 /MT50/MT46/MT52/MT53 /MT50/MT46/MT52/MT56 /MT50/MT46/MT53/MT48 /MT86/MT67/MT67/MT32/MT86 /MT50/MT46/MT52/MT48 /MT86/MT67/MT77/MT79/MT85/MT84/MT32/MT86 /MT52/MT46/MT55/MT52/MT46/MT57/MT53/MT46/MT49/MT53/MT46/MT51/MT53/MT46/MT53 /MT50/MT46/MT52/MT49 /MT50/MT46/MT52/MT51 /MT50/MT46/MT52/MT52 /MT50/MT46/MT52/MT57 /MT50/MT46/MT52/MT54 /MT50/MT46/MT52/MT55 /MT53/MT46/MT55 Total Power vs Clock Frequency with 6 pF loads /MT48 /MT52/MT48/MT48 /MT53/MT48/MT48 /MT54/MT48/MT48 /MT55/MT48/MT48 /MT56/MT48/MT48 /MT51/MT48/MT48 /MT53/MT48/MT49/MT48/MT48/MT49/MT53/MT48/MT50/MT48/MT48/MT50/MT53/MT48 /MT51/MT48/MT48 /MT80/MT111/MT119/MT101/MT114/MT32/MT68/MT105/MT115/MT115/MT105/MT112/MT97/MT116/MT105/MT111/MT110/MT32/MT40/MT109/MT87/MT41 /MT67/MT108/MT111/MT99/MT107/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT79/MT86/MT68/MT68/MT61/MT53/MT32/MT86 /MT49/MT48/MT48/MT48 /MT79/MT86/MT68/MT68/MT61/MT51/MT32/MT86 OV DD Current vs Clock Frequency, Dual Mode /MT48 /MT50/MT48 /MT52/MT48 /MT54/MT48 /MT56/MT48 /MT49/MT48/MT48 /MT49/MT50/MT48 /MT67/MT108/MT111/MT99/MT107/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT48 /MT109/MT65 /MT53/MT48/MT49/MT48/MT48/MT49/MT53/MT48/MT50/MT48/MT48/MT50/MT53/MT48 /MT51/MT48/MT48 /MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT86/MT68/MT68/MT61/MT51/MT32/MT86 /MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT86/MT68/MT68/MT61/MT53/MT32/MT86 OV DD Current vs Clock Frequency, Single Mode /MT48 /MT49/MT48 /MT50/MT48 /MT51/MT48 /MT52/MT48 /MT53/MT48 /MT54/MT48 /MT67/MT108/MT111/MT99/MT107/MT32/MT70/MT114/MT101/MT113/MT117/MT101/MT110/MT99/MT121/MT32/MT40/MT77/MT72/MT122/MT41 /MT48 /MT109/MT65 /MT50/MT53/MT53/MT48/MT55/MT53/MT49/MT48/MT48/MT49/MT50/MT53 /MT49/MT53/MT48 /MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT86/MT68/MT68/MT61/MT51/MT32/MT86 /MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT86/MT68/MT68/MT61/MT53/MT32/MT86 /MT150/MT52/MT48/MT150/MT50/MT48/MT48 /MT50/MT48/MT52/MT48/MT54/MT48 /MT56/MT48 /MT49 /MT50 /MT51 /MT52 /MT53 /MT54 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT40/MT176/MT67/MT41 /MT48 /MT49/MT48/MT48 /MT86/MT111/MT108/MT116/MT115 /MT150/MT53/MT48 /MT67/MT111/MT109/MT109/MT111/MT110/MT45/MT77/MT111/MT100/MT101/MT32/MT79/MT112/MT101/MT114/MT97/MT116/MT105/MT110/MT103/MT32/MT82/MT97/MT110/MT103/MT101 Differential Input Common-Mode Operating Range 400 mVP-P

The SPT7721 is a three-step subranger. It consists of two THAs in series at the input, followed by three ADC blocks. The first block is a three-bit folder with over/under range detection. The second block consists of two single-bit fold- ing interpolator stages. There are pipelining THAs between each ADC block. The analog decode functions are the input buffer, input THAs, three-bit folder, folding interpolators, and pipelining THAs. The input buffer enables the part to withstand rail- to-rail input signals without latchup or excessive currents and also performs single-ended to differential conversion. All of the THAs have the same basic architecture. Each has a differential pair buffer followed by switched emitter followers driving the hold capacitors. The input THA also has hold mode feedthrough cancellation devices. The three MSBs of the ADC are generated in the first three-bit folder block, the output of which drives a differen- tial reference ladder which also sets the full-scale input range. Differential pairs at the ladder taps generate midscale, quarter and three-quarter scale, overrange, and underrange. Every other differential pair collector is cross- coupled to generate the eighth scale zero crossings. The middle ADC block generates two bits from the folded sig- nals of the previous stages after pipeline THAs. Its outputs drive more pipeline THAs to push the decoding of the three LSBs to the next half clock cycle. The three LSBs are gen- erated in interpolators that are latched one full clock cycle after the MSBs. The digital decode consists of comparators, exclusive of cells for gray to binary decoding, and/or cells used for mostly over/under range logic. There is a total of 3.5 clock cycles latency before the output bank selection. In order to reduce sparkle codes and maintain sample rate, no more than three bits at a time are decoded in any half clock cycle. The output data mode is controlled by the state of the demux mode inputs. There are three output modes.  All data on bank A with clock rate limited to one-half maximum  Interleaved mode with data alternately on banks A and B on alternate clock cycles  Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can syn- chronize with the divided clock to select the desired output bank via the differential RESET input. The output logic family is LVCMOS with output VDD supply adjustable from 2.7 volts to 5.3 volts. There are also differ- ential clock output pins that can be used to latch the output data in single bank mode or to indicate the current output bank in demux mode. Finally, a power-down mode is available, which causes the outputs to become tri-state, and overall power is reduced to about 10 mW. There is a 2.5 V reference to supply com- mon mode for single-ended inputs that is not shut down in power-down mode. Figure 1 – Single Mode Timing Diagram /MT86/MT73/MT78 /MT78/MT150/MT49/MT78/MT150/MT50/MT78/MT150/MT51 /MT78 /MT32/MT67/MT76/MT75 /MT47/MT67/MT76/MT75 /MT68/MT48/MT150/MT68/MT55 /MT40/MT80/MT111/MT114/MT116/MT32/MT65/MT41 /MT47/MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT78/MT43/MT50 /MT32/MT50/MT46/MT53/MT32/MT67/MT76/MT75/MT32/MT67/MT121/MT99/MT108/MT101/MT115/MT32/MT111/MT102/MT32/MT76/MT97/MT116/MT101/MT110/MT99/MT121 /MT116/MT97/MT112 /MT78/MT43/MT52 /MT78/MT43/MT53/MT78/MT43/MT51/MT78/MT43/MT50 /MT78 /MT78/MT43/MT49 /MT116/MT112/MT100/MT50/MT116/MT112/MT100/MT50 /MT116/MT112/MT100/MT49 /MT78/MT43/MT49

Figure 2 – Dual Mode Timing Diagram /MT78/MT45/MT50 /MT80/MT111/MT114/MT116/MT32/MT65 /MT80/MT111/MT114/MT116/MT32/MT66 /MT32/MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT47/MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT80/MT111/MT114/MT116/MT32/MT65 /MT80/MT111/MT114/MT116/MT32/MT66 /MT78/MT45/MT49/MT73/MT110/MT118/MT97/MT108/MT105/MT100/MT32/MT68/MT97/MT116/MT97 /MT78/MT45/MT50/MT78/MT45/MT53 /MT80/MT65/MT82/MT65/MT76/MT76/MT69/MT76/MT32/MT68/MT65/MT84/MT65/MT32/MT79/MT85/MT84/MT80/MT85/MT84 /MT32/MT73/MT78/MT84/MT69/MT82/MT76/MT69/MT65/MT86/MT69/MT68/MT32/MT68/MT65/MT84/MT65/MT32/MT79/MT85/MT84/MT80/MT85/MT84 /MT73/MT110/MT118/MT97/MT108/MT105/MT100/MT32/MT68/MT97/MT116/MT97 /MT78/MT43/MT49/MT78/MT45/MT52 /MT78/MT45/MT53 /MT78/MT45/MT54 /MT78/MT45/MT54 /MT78/MT45/MT49 /MT78 /MT78 /MT82/MT101/MT115/MT101/MT116 /MT47/MT82/MT101/MT115/MT101/MT116 /MT86/MT105/MT110 /MT67/MT76/MT75 /MT47/MT67/MT76/MT75 /MT32/MT50/MT46/MT53/MT32/MT67/MT76/MT75/MT32/MT67/MT121/MT99/MT108/MT101/MT115/MT32/MT111/MT102/MT32/MT76/MT97/MT116/MT101/MT110/MT99/MT121 /MT116/MT97/MT112 /MT85/MT54/MT45/MT82/MT101/MT115/MT101/MT116 /MT78/MT43/MT50 /MT78/MT43/MT51 /MT78/MT43/MT52/MT78/MT43/MT49/MT78 /MT78/MT45/MT50 /MT78/MT45/MT49 /MT32/MT32/MT116/MT115/MT32/MT32/MT116/MT114/MT101/MT115/MT101/MT116 /MT32/MT32/MT116/MT112/MT100/MT49 /MT32/MT32/MT53/MT53/MT48/MT112/MT115/MT32/MT32/MT53/MT53/MT48/MT112/MT115 /MT82/MT101/MT115/MT101/MT116 /MT47/MT82/MT101/MT115/MT101/MT116 /MT86/MT105/MT110 /MT67/MT76/MT75 /MT47/MT67/MT76/MT75 /MT78/MT45/MT50 /MT78/MT45/MT49/MT80/MT111/MT114/MT116/MT32/MT65 /MT80/MT111/MT114/MT116/MT32/MT66 /MT47/MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT80/MT111/MT114/MT116/MT32/MT65 /MT80/MT111/MT114/MT116/MT32/MT66 /MT78/MT45/MT49/MT73/MT110/MT118/MT97/MT108/MT105/MT100/MT32/MT68/MT97/MT116/MT97 /MT78/MT45/MT50 /MT78/MT45/MT53 /MT78/MT45/MT52 /MT32/MT32/MT116/MT112/MT100/MT49 /MT32/MT50/MT46/MT53/MT32/MT67/MT76/MT75/MT32/MT67/MT121/MT99/MT108/MT101/MT115/MT32/MT111/MT102/MT32/MT76/MT97/MT116/MT101/MT110/MT99/MT121 /MT78/MT43/MT49 /MT116/MT97/MT112 /MT85/MT54/MT45/MT82/MT101/MT115/MT101/MT116 /MT78/MT45/MT53 /MT78/MT45/MT52 /MT78/MT45/MT54 /MT78/MT45/MT55 /MT78/MT45/MT54 /MT32/MT73/MT78/MT84/MT69/MT82/MT76/MT69/MT65/MT86/MT69/MT68/MT32/MT68/MT65/MT84/MT65/MT32/MT79/MT85/MT84/MT80/MT85/MT84 /MT78 /MT78 /MT78/MT43/MT50 /MT78/MT43/MT51 /MT78/MT43/MT52/MT78/MT43/MT49/MT78 /MT78/MT45/MT50 /MT78/MT45/MT49 /MT32/MT32/MT116/MT115 /MT80/MT65/MT82/MT65/MT76/MT76/MT69/MT76/MT32/MT68/MT65/MT84/MT65/MT32/MT79/MT85/MT84/MT80/MT85/MT84 /MT32/MT32/MT116/MT114/MT101/MT115/MT101/MT116 /MT32/MT32/MT116/MT112/MT100/MT51 /MT32/MT32/MT116/MT112/MT100/MT49 /MT32/MT32/MT116/MT112/MT100/MT50 /MT32/MT32/MT116/MT112/MT100/MT49 /MT32/MT32/MT116/MT112/MT100/MT50 /MT32/MT32/MT53/MT53/MT48/MT112/MT115/MT32/MT32/MT53/MT53/MT48/MT112/MT115 /MT68/MT97/MT116/MT97/MT32/MT79/MT117/MT116/MT112/MT117/MT116/MT32/MT80/MT111/MT115/MT115/MT105/MT98/MT105/MT108/MT105/MT116/MT105/MT101/MT115/MT32/MT119/MT47/MT111/MT32/MT82/MT101/MT115/MT101/MT116 /MT32/MT32/MT116/MT112/MT100/MT50 /MT32/MT32/MT116/MT112/MT100/MT49 /MT32/MT32/MT116/MT112/MT100/MT49 /MT32/MT32/MT116/MT112/MT100/MT49 /MT73/MT110/MT118/MT97/MT108/MT105/MT100/MT32/MT68/MT97/MT116/MT97 /MT82/MT101/MT102/MT101/MT114/MT32/MT116/MT111/MT32/MT65/MT78/MT55/MT55/MT50/MT50 /MT82/MT101/MT102/MT101/MT114/MT32/MT116/MT111/MT32/MT65/MT78/MT55/MT55/MT50/MT50

To save on power, the SPT7721 incorporates a power- down function. This function is controlled by the signal on pin PD. When pin PD is set high, the SPT7721 enters the power-down mode. All outputs are set to high impedance. In the power-down mode the SPT7721 dissipates 10 mW typically. REFERENCES To save on parts count, design time, and PC board real estate, the SPT7721 utilizes an internal reference. No other external components are required to implement this feature. COMMON MODE VOLTAGE REFERENCE CIRCUIT The SPT7721 has an on-board common-mode voltage reference circuit (V CM ). It is 2.5 volts and is capable of driv- ing 50 µA loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differen- tial applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. CLOCK INPUT The clock input on the SPT7721 can be driven by either a single-ended or double-ended clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the clock signal as close to 50% as possible. For TTL/CMOS single-ended clock inputs, the rise time of the signal also becomes an important consideration. DIGITAL OUTPUTS The output circuitry of the SPT7721 has been designed to be able to support three separate output modes. The demuxed (double-wide) mode supports either parallel aligned or interleaved data output. The single-channel mode is not demuxed and can support direct output at speeds up to 125 MSPS. The output format is straight binary (table I). Table I – Output Data Format Analog Input Output Code D7–D0 +FS 1111 1111 +FS – 1/2 LSB 1111 111Ø +1/2 FS ØØØØ ØØØØ –FS + 1/2 LSB 0000 000Ø –FS 0000 0000 Ø indicates the flickering bit between logic 0 and 1 The data output mode is set using the DMODE1 and DMODE 2 inputs (pins 32 & 31 respectively). Table II describes the mode switching options. Table II – Output Data Modes Output Mode DMODE 1 DMODE 2 Parallel Dual Channel Output 0 0 Interleaved Dual Channel Output 0 1 Single Channel Data Output (Bank A only 125 MSPS max) 1 X EVALUATION BOARD The EB7721/22 evaluation board is available to aid design- ers in demonstrating the full performance of the SPT7721. This board includes a clock driver and reset circuit, adjust- able references and common mode, a single-ended to dif- ferential input buffer and a single-ended to differential transformer (1:1). An application note (AN7721/22) de- scribing the operation of this board, as well as information on the testing of the SPT7721, is also available. Contact the factory for price and availability of the EB7721/22.

A 0.472 Typ 12.00 Typ B 0.394 Typ 10.00 Typ C 0.394 Typ 10.00 Typ D 0.472 Typ 12.00 Typ E 0.031 Typ 0.80 Typ F 0.012 0.018 0.300 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.020 0.030 0.500 0.750 J 0.039 Typ 1.00 Typ K 0-7° 0-7° Index A B C D Pin 1 E F G H I J K

/MT49 /MT50 /MT51 /MT52 /MT53 /MT54 /MT55 /MT56 /MT57 /MT49/MT48 /MT49/MT49 /MT49/MT50 /MT49/MT51 /MT49/MT52 /MT49/MT53 /MT49/MT54 /MT49/MT55 /MT49/MT57 /MT49/MT56 /MT50/MT48 /MT50/MT50 /MT50/MT49/MT50/MT51 /MT50/MT52 /MT50/MT53 /MT50/MT54 /MT50/MT55 /MT50/MT56 /MT50/MT57 /MT51/MT48 /MT51/MT49 /MT51/MT50 /MT51/MT51 /MT51/MT52 /MT51/MT53 /MT51/MT54 /MT51/MT55 /MT51/MT56 /MT51/MT57 /MT52/MT48 /MT52/MT49 /MT52/MT50 /MT52/MT51 /MT52/MT52 /MT65/MT71/MT78/MT68 /MT80/MT68 /MT67/MT76/MT75 /MT82/MT69/MT83/MT69/MT84 /MT68/MT71/MT78/MT68 /MT79/MT86/MT68/MT68 /MT68/MT65/MT54 /MT68/MT65/MT55/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT65/MT53 /MT68/MT65/MT52 /MT68/MT65/MT51 /MT68/MT65/MT48/MT32/MT40/MT76/MT83/MT66/MT41 /MT79/MT86/MT68/MT68 /MT68/MT71/MT78/MT68 /MT68/MT66/MT48/MT32/MT40/MT76/MT83/MT66/MT41 /MT68/MT66/MT49 /MT68/MT66/MT50 /MT68/MT66/MT51 /MT68/MT66/MT52 /MT68/MT66/MT53 /MT68/MT66/MT55/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT66/MT54 /MT68/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT79/MT86/MT68/MT68 /MT68/MT77/MT79/MT68/MT69/MT50 /MT86/MT73/MT78/MT43 /MT86/MT67/MT77 /MT65/MT86/MT67/MT67 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT83/MT80/MT84/MT55/MT55/MT50/MT49 /MT84/MT79/MT80/MT32/MT86/MT73/MT69/MT87 /MT52/MT52/MT76/MT32/MT84/MT81/MT70/MT80 /MT68/MT65/MT50 /MT68/MT65/MT49 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 /MT68/MT77/MT79/MT68/MT69/MT49 /MT65/MT86/MT67/MT67 /MT86/MT73/MT78/MT150 /MT65/MT71/MT78/MT68 /MT65/MT71/MT78/MT68 /MT65/MT86/MT67/MT67 /MT65/MT86/MT67/MT67 /MT67/MT76/MT75 /MT82/MT69/MT83/MT69/MT84 /MT68/MT67/MT76/MT75/MT79/MT85/MT84 DB 0–DB 7 Data output; Bank B. 3 V / 5 V LVCMOS compatible. DCLK OUT Non-Inverted data output clock. 3 V / 5 V LVCMOS compatib le. DCLK OUT Inverted data output clock. 3 V / 5 V LVCMOS compatible. CLK Non-Inverted clock input pin; 100k pulldown to AGND , internally CLK Inverted clock input pin; 17.5k pullup to VCC and 7.5k pulldown to AGND , internally RESET RESET synchronizes the data sampling and data output bank relationship when in Dual Channel Mode (DMODE 1 = 0); 100k pulldown to AG ND , internally RESET Inverted RESET input pin; 17.5k pullup to VCC and 7.5k pulldown to AG ND , internally DMODE 1,2 Internally: 100k pulldown to AGND on DMODE1 50k pullup to VCC on DMODE2 Data Output Mode pins: DMODE 1 = 0, DMODE2 = 0: Parallel Dual Channel Output DMODE 1 = 0, DMODE2 = 1: Interleaved Dual Channel Output DMODE 1 = 1, DMODE2 = X: Single Channel Data Output on Bank A (125 MSPS max) PD Pow er Down pin; PD = 1 for pow er-down mode . Outputs set to high impedance in pow er-down mode; 100k pulldown to AGND , internally VCM 2.5 V Common Mode Voltage Reference Output AV CC +5 V Analog Supply OV DD +3 V / +5 V Digital Output Supply AGND Analog Ground DGND Digital Ground ORDERING INFORMA TION PART NUMBER TEMPERATURE RANGE PACKAGE SPT7721SIT –40 to +85 °C 44L TQFP PIN FUNCTIONS Pin Name Description VIN+ Non-Inverted Analog Input; nominally 1 VP-P; 100k pullup to VCC and 100k pulldown to AG ND , internally VIN– Inverted Analog Input; nominally 1 VP-P; 100k pullup to VCC and 100k pulldown to AGND , internally DA 0–DA 7 Data output; Bank A. 3 V / 5 V LVCMOS compatible.