SPT7610SIQ

SPT7610 CADEKA | Alldatasheet

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6-BIT, 1 GSPS FLASH A/D CONVER TER JANU ARY 21, 2002 FEA TURES

• 1:2 demuxed ECL-compatible outputs 1.0 GSPS conversion rate Wide input bandwidth: 1.4 GHz Low input capacitance: 8 pF Metastable errors reduced to 1 LSB Monolithic construction Binary/Tw o’s complement output APPLICA TIONS R adar, EW, ECM D irect RF down-conversion Microw ave modems Industrial ultrasound Transient capture Test and measurement GENERAL DESCRIPTION The SPT7610 is a full parallel (flash) analog-to-digital con- verter capable of digitizing full-scale (0 to –1 V) inputs into six-bit digital words at an update rate of 1 GSPS. The ECL-compatible outputs are demultiplexed into two sepa- rate output banks, each with differential data-ready out- puts to ease the task of data capture. The SPT7610’s wide input bandwidth and low capacitance eliminate the need for external track-and-hold amplifiers for most applica- tions. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7610 operates from a single –5.2 V supply, with a nominal power dissipation of 2.75 W. The SPT7610 is available in a 44L hermetic cerquad surface-mount package in the industrial temperature range (–40 °C to +85 °C). CLOCK B UFFER

64 TO 6 BIT DECODER

WITH MET AST ABLE ERR OR CORRECTION DO (LSB) (MSB) (OVR) V RT Analog Input Preamp Compar ator VRM VRB CLK CLK DEMUX CLOCK B UFFER1:2 DEMUL TIPLEXER ECL OUTPUT B UFFERS AND LA TCHES DRB (DATA READ Y) DRB (DATA READ Y) D6B (OVR) D5B (MSB) D4B D3B D2B D1B D0B (LSB) DRA (DATA READ Y) DRA (DATA READ Y) D6A (OVR) D5A (MSB) D4A D3A D2A D1A D0A (LSB) D6B D5B D4B D3B D2B D1B D0B D6A D5A D4A D3A D2A D1A D0A BANK B BANK A V R1 V R3 MINV LINV TEST A- BILITY TEST BLOCK DIA GRAM

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Supply Voltages Negative Supply Voltage (AVEE TO GND) .–7.0 to +0.5 V Input Voltage Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Output Temperature ELECTRICAL SPECIFICATIONS TEST TEST SPT7610 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 6 Bits DC Accuracy Integral Linearity VI –0.5 +0.5 LSB Differential Linearity VI –0.5 +0.5 LSB No missing codes VI Guaranteed Analog Input Offset Error VRT VI –30 +30 mV Offset Error VRB VI –30 +30 mV Input Voltage Range VI –1 0.0 Volts Input Capacitance Over Full Input Range V 8 pF Input Resistance V 50 k Ω Input Bias Current VI 200 400 µA Bandwidth Small Signal V 1.4 GHz Input Slew Rate V 5 V/ns Clock Synchronous Input Currents V 2 µA Power Supply Requirements Supply Current VI 550 770 mA Power Dissipation VI 2.85 4.0 W Reference Inputs Ladder Resistance VI 60 80 120 Ω Reference Bandwidth V 100 MHz Digital Outputs Digital Output High Voltage R 1 = 50 Ω to –2 V VI –1.2 –0.9 Volts Digital Output Low Voltage R 1 = 50 Ω to –2 V VI –1.8 –1.5 Volts Digital Inputs Digital Input High Voltage (CLK, NCLK) VI –1.1 –0.7 Volts Digital Input Low Voltage (CLK, NCLK) VI –2.0 –1.5 Volts Clock Input Swing (CLK, NCLK) IV 100 700 mV Maximum Sample Rate VI 1000 1200 MSPS Clock Low Width, TPW0 VI 0.5 0.4 ns Clock High Width, TPW1 VI 0.5 0.4 ns

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Timing Characteristics Clock to Data Ready delay (tdr) Data Bank A +25 °C case V 1.68 ns Data Bank B +25 °C case V 1.73 ns Clock to Output Data (tod) Data Bank A +25 °C case V 2.14 ns Data Bank B +25 °C case V 2.00 ns Output Data to Data Ready (todr) Data Bank A –40 to 85 °C case IV 1.54 ns Data Bank B –40 to 85 °C case IV 1.73 ns Output Data Skew (tosk) –40 to 85 °C case IV –150 150 ps Aperture Jitter V 2 ps Acquisition Time V 250 ps Dynamic Performance Spurious Free Dynamic Range (SFDR) ƒIN = 250 MHz V 45 dB ƒIN = 400 MHz V 34 dB Signal-to-Noise and Distortion (SINAD) ƒIN = 250 MHz VI 31 34 dB ƒIN = 400 MHz VI 28 32 dB Signal to Noise Ratio (SNR) ƒIN = 250 MHz VI 33 36 dB ƒIN = 400 MHz VI 32 36 dB Total Harmonic Distortion (THD) ƒIN = 250 MHz VI –40 –37 dB ƒIN = 400 MHz VI –34 –30 dB TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all test are pulsed tests; therefore, T J = TC = TA. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range.

The SPT7610 is an ultra high-speed monolithic 6-bit parallel flash A/D converter. The nominal conversion rate is 1 GSPS, and the analog bandwidth is typically 1.4 GHz. A major advance over previous flash converters is the inclusion of 64 input preamplifiers between the reference ladder and input comparators. (See the block diagram.) This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges. This makes the part easier to drive than previous flash converters. The pre- amplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to “trip” into or out of the active state. This gain reduces metastable states that can cause errors at the output. The SPT7610 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The out- put drive capability of the device can provide full ECL swings into 50 Ω loads. Only one –5.2 V power supply is required. Two external references are applied across the internal reference lad- der that has a resistance of 80 Ω typical (60 Ω minimum). The top reference is typically 0 V or connected to AGND (analog ground). The device has top force and sense pins RFT and VRST ) that are internally connected together. These voltage force and sense pins can be used to mini- mize the voltage drop across the parasitic line resistance. The bottom reference is typically –1 V. The device also has bottom force and sense pins (V RFB and VRSB ) that are internally connected together. These can also be used to minimize the voltage drop across the parasitic line resis- tance. Three additional reference taps (V R3 = –0.25 V typ, VRM = –0.5 V typ, and VR1 = –0.75 V typ) are brought out. These taps can be used to control the linearity error. All logic levels are compatible with both 10K ECL or 100K ECL. It is recommended that the clock input be driven differentially (CLK and NCLK) to improve noise immunity and reduce aperture jitter. The digital outputs are split into two banks of 6-bit words and an overrange bit. Each bank is updated at 1/2 of the clock rate and is 180° out of phase from the other. The dif- ferential data ready signals for each bank are provided to accurately latch each data bank into the register. The out- put data is in a straight binary, inverted binary, two’s complement or inverted two’s complement format. Figure 1 shows a timing diagram of the device and shows the in- put-to-output relationship, clock-to-output delay and out- put latency. The SPT7610 has a built-in offset in the ÷2 clock divider (D Flip-Flop) to assure that output bank A will come up first after power turn on.

The typical interface circuit is shown in figure 3. External reference taps are provided for correcting integral nonlinearity errors. These taps can be actively driven to reduce these errors. (See the Reference Inputs discus- sion below.) The SPT7610 evaluation board application note contains more details on interfacing the SPT7610. The function of each pin and external connections to other components is as follows: POWER SUPPLY PINS: AV EE , AGND, DGND AV EE is the supply pin with AGND as ground for the de- vice. The AVEE power supply pin should be bypassed as close to the device as possible with a 10 µF tantalum ca- pacitor, in parallel with 100 pF and .01 µF chip capacitors. Place the 100 pF chip capacitor closest to the SPT7610. Digital ground (DGND) is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 3. ANALOG INPUT: V IN There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7610 is superior to similar de- vices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has con- stant capacitance and induces less slew rate distortion. CLOCK INPUTS: CLK, NCLK The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. Figure 3 – Typical Interface Circuit /MT86/MT73/MT78 /MT86/MT73/MT78 /MT86/MT82/MT84/MT70 /MT86/MT82/MT84/MT83 /MT42 /MT85/MT49 /MT43 /MT42 /MT85/MT49/MT43 /MT150 /MT150/MT53/MT46/MT50/MT32/MT86 /MT50/MT78/MT50/MT57/MT48/MT55 /MT86/MT82/MT66/MT83 /MT86/MT82/MT66/MT70 /MT53/MT48/MT32/MT87 /MT86/MT73/MT78 /MT150/MT50/MT46/MT48/MT32/MT86 /MT82/MT101/MT102/MT101/MT114/MT101/MT110/MT99/MT101 /MT67/MT111/MT110/MT118/MT101/MT114/MT116 /MT150/MT50/MT32/MT86 /MT80/MT117/MT108/MT108/MT100/MT111/MT119/MT110 /MT40/MT65/MT110/MT97/MT108/MT111/MT103/MT41 /MT67/MT76/MT75 /MT78/MT67/MT76/MT75 /MT86/MT82/MT77 /MT82 /MT82 /MT150/MT53/MT46/MT50/MT32/MT86 /MT65/MT86/MT69/MT69 /MT65/MT71/MT78/MT68 /MT68/MT71/MT78/MT68 /MT42 /MT70/MT66 /MT61/MT32 /MT70/MT101/MT114/MT114/MT105/MT116/MT101/MT32/MT98/MT101/MT97/MT100 /MT85/MT49 /MT61 /MT84/MT76/MT86/MT50/MT52/MT54/MT52/MT32/MT111/MT114/MT32/MT101/MT113/MT117/MT105/MT118/MT97/MT108/MT101/MT110/MT116/MT32/MT119/MT105/MT116/MT104/MT32/MT108/MT111/MT119/MT32/MT111/MT102/MT102/MT115/MT101/MT116/MT47/MT110/MT111/MT105/MT115/MT101/MT46 /MT82 /MT61 /MT49/MT32/MT107/MT87/MT59/MT32/MT48/MT46/MT48/MT53/MT37/MT32/MT109/MT97/MT116/MT99/MT104/MT101/MT100/MT32/MT111/MT114/MT32/MT98/MT101/MT116/MT116/MT101/MT114 /MT61 /MT65/MT71/MT78/MT68 /MT61 /MT68/MT71/MT78/MT68 /MT85/MT50 /MT61 /MT77/MT111/MT116/MT111/MT114/MT111/MT108/MT97/MT32/MT69/MT67/MT76/MT105/MT110/MT80/MT83/MT32/MT76/MT105/MT116/MT101/MT44/MT32/MT77/MT67/MT49/MT48/MT69/MT76/MT49/MT54/MT44/MT32/MT100/MT105/MT102/MT102/MT101/MT114/MT101/MT110/MT116/MT105/MT97/MT108/MT32/MT114/MT101/MT99/MT101/MT105/MT118/MT101/MT114/MT46 /MT42/MT32 /MT61 /MT50/MT46/MT50/MT32/MT181/MT70/MT32/MT84/MT97/MT110/MT116/MT97/MT108/MT117/MT109/MT32/MT67/MT97/MT112/MT97/MT99/MT105/MT116/MT111/MT114/MT44/MT32/MT48/MT46/MT49/MT32/MT181/MT70/MT32/MT97/MT110/MT100/MT32/MT49/MT48/MT48/MT32/MT112/MT70/MT32/MT99/MT104/MT105/MT112/MT32/MT99/MT97/MT112/MT97/MT99/MT105/MT116/MT111/MT114/MT115/MT46 /MT42/MT42 /MT61 /MT67/MT97/MT114/MT101/MT32/MT109/MT117/MT115/MT116/MT32/MT98/MT101/MT32/MT116/MT97/MT107/MT101/MT110/MT32/MT116/MT111/MT32/MT97/MT118/MT111/MT105/MT100/MT32/MT101/MT120/MT99/MT101/MT101/MT100/MT105/MT110/MT103/MT32/MT116/MT104/MT101/MT32/MT109/MT97/MT120/MT105/MT109/MT117/MT109/MT32/MT114/MT97/MT116/MT105/MT110/MT103 /MT102/MT111/MT114/MT32/MT116/MT104/MT101/MT32/MT105/MT110/MT112/MT117/MT116/MT44/MT32/MT101/MT115/MT112/MT101/MT99/MT105/MT97/MT108/MT108/MT121/MT32/MT100/MT117/MT114/MT105/MT110/MT103/MT32/MT112/MT111/MT119/MT101/MT114/MT32/MT117/MT112/MT32/MT115/MT101/MT113/MT117/MT101/MT110/MT99/MT105/MT110/MT103/MT32/MT111/MT102/MT32/MT116/MT104/MT101 /MT97/MT110/MT97/MT108/MT111/MT103/MT32/MT105/MT110/MT112/MT117/MT116/MT32/MT100/MT114/MT105/MT118/MT101/MT114/MT46 /MT85/MT50 /MT68/MT82/MT66/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT66/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT65/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT65/MT32/MT40/MT68/MT65/MT84/MT65/MT32/MT82/MT69/MT65/MT68/MT89/MT41 /MT68/MT82/MT66 /MT68/MT82/MT65 /MT68/MT82/MT66 /MT68/MT82/MT65 /MT42/MT42 /MT70/MT66 /MT42 /MT86/MT82/MT51 /MT42 /MT86/MT82/MT49 /MT53/MT48/MT32/MT87 /MT68/MT54/MT66/MT32/MT40/MT79/MT86/MT82/MT41 /MT68/MT53/MT66/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT52/MT66 /MT68/MT51/MT66 /MT68/MT50/MT66 /MT68/MT49/MT66 /MT68/MT48/MT66/MT32/MT40/MT76/MT83/MT66/MT41 /MT150/MT50/MT46/MT48/MT32/MT86 /MT80/MT117/MT108/MT108/MT100/MT111/MT119/MT110 /MT40/MT68/MT105/MT103/MT105/MT116/MT97/MT108/MT41 /MT53/MT48/MT32/MT87 /MT46/MT49/MT32/MT181/MT70 /MT68/MT54/MT65/MT32/MT40/MT79/MT86/MT82/MT41 /MT68/MT53/MT65/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT52/MT65 /MT68/MT51/MT65 /MT68/MT50/MT65 /MT68/MT49/MT65 /MT68/MT48/MT65/MT32/MT40/MT76/MT83/MT66/MT41 /MT84/MT101/MT115/MT116 /MT76/MT73/MT78/MT86 /MT77/MT73/MT78/MT86 /MT150/MT53/MT46/MT50/MT32/MT86 /MT150/MT53/MT46/MT50/MT32/MT86 /MT150/MT53/MT46/MT50/MT32/MT86 /MT83/MT80/MT84/MT55/MT54/MT49/MT48 /MT53/MT48/MT32/MT87 /MT150/MT53/MT46/MT50/MT32/MT86 /MT50/MT50/MT32/MT87 /MT150 /MT50/MT50/MT32/MT87 /MT53/MT48/MT32/MT87

DIGITAL OUTPUTS: D0 TO D6, DR, NDR (A AND B) The digital outputs can drive 50 Ω to ECL levels when pulled down to –2 V. When pulled down to –5.2 V, the out- using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times. BINAR Y AND TW O ’S COMPLEMENT OUTPUT : MINV , LINV Control pins are provided that enable selection of one of four digital output formats. (Table I shows selection of these output formats as a function of the MINV and LINV pins.) When the MINV pin is high, the MSB output is in- verted and when it is low, the it is noninverted. Likewise, when the LINV pin is high, the LSB output is inverted and when it is low, the it is noninverted. The user can select either binary, inverted binary, two’s complement or inverted two’s complement digital output format. REFERENCE INPUTS: VRBF , VRBS , VR1 , VRM , VR3 , VRT F, VRT S There are two reference inputs and three external refer- ence voltage taps. These are –1.0 V VRBF (bottom force) and VRBS (bottom sense), –0.75 V VR1 (1/4 tap), –0.5 V VRM (mid-point tap), –0.25 V VR3 (3/4 tap) and 0.0 V (AGND) VRT F (top force) and VRT S (top sense). The top ref- erence pin is normally tied to analog ground (AGND) and the bottom reference pin can be driven by an op amp as shown in figure 3. The reference voltage taps can be used to control integral linearity over temperature. The mid-point reference tap (VRM ) is normally driven by an op amp to insure tempera- ture stable operation or may be bypassed for limited tem- perature operation. The 1/4 (VR1 ) and 3/4 (VR3 ) reference ladder taps are typically bypassed to add noise suppres- sion as shown in figure 3 or may be driven with op amps to adjust integral linearity. SPT7610 TEST MODE FUNCTION: TEST PIN The SPT7610 supports a special test mode function that overrides the SPT7610’s internal data output latch stage and exercises the digital outputs in an alternating test pat- tern. This enables the user to test digital interface logic downstream from the SPT7610 with a known set of digital test patterns. Test mode pin 3 controls the SPT7610 mode of operation such that when it is low, the SPT7610 operates in normal mode . When test mode pin 3 is brought high, the SPT7610 will begin to output test pattern 1 (table II) on the next rising edge of the clock. (See figure 2.) It will output the test patterns alternating between test pattern 1 and test pattern 2 as long as test mode pin 3 is held high. The minimum set-up time (tsu) can be as low as 0 nsec. Only the digital output stage is involved in the test mode operation. All ADC stages before the digital output stage continue normal data conversion operation while the test mode is active. When test mode pin 3 is brought back low, the SPT7610 will resume output of valid data on the next rising edge of the clock. The valid data output will corre- spond to a two-clock-cycle pipeline delay as shown in figure 2. Table II – SPT7610 Test Mode Output Bit Patterns D6 D5 D4 D3 D2 D1 D0 Test Pattern 1 1010101 Test Pattern 2 0101010 BINAR Y TW O s COMPLEMENT TR UE INVER TED TR UE INVER TED MINV=LINV=0 MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1 –1 V + 1/2 LSB 0 000000 111111 100000 0 011111 1 0 00000 1 11111 0 100000 1 011111 0 –0.5 V 0 0111111 100000 111111 000000 100000 011111 000000 111111

0 V – 1/2 LSB 0 111111 000000 011111 100000

1 111111 000000 011111 100000

0 V 1 111111 000000 011111 100000

1 Tie MINV/LINV to GND for logic 1. 2 Float MINV/LINV for logic 0. (MINV/LINV are internally pulled down to –5.2 V.) Table I – Output Coding Table puts can drive 130 Ω to 1 kΩ loads. CADEKA recommends

Figure 3A – Input Circuit Figure 3B – Output Circuit Figure 3C – Clock Input Data Out AGND DGND AGND AV EE VIN Vr AGND AV EE CLK CLK THERMAL MANA GEMENT Adequate heat sinking and air flow must be provided to keep the die temperature below +150 °C . This device is packaged with the cavity up (the die is on the bottom of device be heat sinked by contacting the bottom of the package through a hole in the circuit board. The thermal coefficients of the SPT7610 (44L cerquad) are as follows: θja =+78 °C/W (junction to ambient in still air with no heat sink) θjc =+4 °C/W (junction to case) the package). Therefore, CADEKA recommends that the

INCHESINCHESINCHESINCHESINCHES MILLIMETERSMILLIMETERSMILLIMETERSMILLIMETERSMILLIMETERS SYMBOLSYMBOLSYMBOLSYMBOLSYMBOL MINMINMINMINMIN MAXMAXMAXMAXMAX MINMINMINMINMIN MAXMAXMAXMAXMAX A 0.551 typ 14.0 typ B 0.685 0.709 17.40 18.00 C 0.037 0.041 0.94 1.04 D 0.016 typ 0.41 typ E 0.008 typ 0.20 typ F 0.027 0.051 0.69 1.30 G 0.006 typ 0.15 typ H 0.080 0.150 2.03 3.81 /MT67 /MT68 /MT65/MT66 /MT65 /MT66 /MT48/MT150/MT53/MT176 /MT69 /MT70 /MT71 /MT72

PART NUMBER TEMPERATURE RANGE PACKAGE SPT7610SIQ –40 to +85 °C 44L Cerquad PIN ASSIGNMENTS PIN FUNCTIONS Name Function AV EE Negative Supply; nominally –5.2 V AG N D Analog Ground VRT F Reference Voltage Force Top; nominally 0 V VRT S Reference Voltage Sense Top VRM Reference Voltage Middle; nominally –0.5 V VRBF Reference Voltage Force Bottom; nominally –1.0 V VRBS Reference Voltage Sense Bottom VIN Analog Input Voltage; can be either Voltage or Sense DGND Digital Ground D0 –D5A Data Output Bank A D0 –D5B Data Output Bank B DRA Data Ready Bank A NDRA Not Data Ready Bank A DRB Data Ready Bank B NDRB Not Data Ready Bank B D6A O verrange Output Bank A D6B O verrange Output Bank B CLK Clock Input NCLK Clock Input MINV M SB Control Pin LINV LSB Control Pin TEST Test Control Pin VR1 Reference Voltage 1/4, nominally –0.75 V VR3 Reference Voltage 3/4, nominally –0.25 V VRTF AVEE VR3 AGND VIN VIN AGND VRM VR1 AVEE VRBF DGND D2B D3B D4B D5B D6B DGND DRA NDRA D0A D1A SPT7610 Top View 1VRBS MINV Test AGND AV EE D6A D5A D4A D3A DGND D2A VRT S AGND CLK NCLK AGND LINV AV EE DRB NDRB D0B D1B 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22