SPT5510SIM

SPT5510 CADEKA | Alldatasheet

Document overview

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Technical content

16-BIT, 200 MWPS ECL D/A CONVERTER

APPLICATIONS

• High-precision arbitrary waveform generation
• Test and measurement instrumentation
• Digital waveform synthesis
• Microwave and satellite modems
• Disk drive test equipment
• Industrial process control
• Military applications BLOCK DIAGRAM GENERAL DESCRIPTION The SPT5510 is a 16-bit, 200 MWPS digital-to-analog converter designed for high-resolution waveform synthesis for test and measurement instrumentation applications. It features true 16-bit linearity, with differential non-linearity of typically ±0.6 LSB and integral non-linearity of ±0.75 LSB. It

FEATURES

• 16-Bit, 200 MWPS digital-to-analog converter
• Differential linearity of ±0.6 LSB (typical)
• Integral linearity of ±0.75 LSB (typical)
• Fast settling time: 35 ns to 0.0008%; 25 ns to 0.01%
• Low glitch energy
• On-chip voltage reference
• ECL compatibility has a very high-speed update rate of up to 200 MHz and is ECL compatible. It has an ultrafast settling time of 25 ns to 0.01% and 35 ns to 0.0008%. The SPT5510 operates over an industrial temperature range of –40 °C to +85 °C and is available in a 10 x 10 mm, 44-lead metric quad flat pack (MQFP) plastic package. 16 16 12 12 IOUT IOUT CLK Digital Inputs D15–D0 Bandgap ReferenceBG OUT R SET AMP INB Ref Amp AMP OUT AMP CC Bias Reference Cell Bias Current Cells D15–D12 D11–D0 MSB Latch LSB Latch Input Latch MSB Decoder LSB Buffer IOUT IOUT REF IN

Differential Linearity VI –1.95 ±0.6 1.95 LSB Differential Linearity T MIN –TMAX IV –4.0 ±1.0 4.0 LSB Integral Linearity VI –1.95 ±0.75 1.95 LSB Integral Linearity T MIN –TMAX IV –4.0 ±1.5 4.0 LSB Integral Linearity Drift IV –0.2 0.2 LSB/ °C Offset Drift T MIN –TMAX IV –2.5 2.5 ppm FS/ °C Monotonicity V 15 Bits Output Capacitance V 10 pF Gain Error I –2 0.4 2 % FS Gain Error Tempco With Ext Reference V 50 ppm FS/ °C Gain Error Tempco With Internal Bandgap Ref V 50 ppm FS/ °C Offset Error I –4 4 µA Compliance Voltage IV –1.2 2 V Output Resistance IV 0.88 1.1 1.32 k Ω Dynamic Performance Conversion Rate IV 200 MHz Settling Time tST 2 Settling to ±0.01% V 25 ns Settling to ±0.0008% V 35 ns Delay Time tD V2 n s Glitch Energy V 30 pV-s Full Scale Output Current With On-Chip References V 19 mA Rise Time/Fall Time R L = 50 Ω V2 n s Spurious Free Dynamic Range ƒOUT =5 MHz; ƒCLOCK =30 MHz 10 MHz Span V 84 dB ƒOUT =10 MHz; ƒCLOCK =100 MHz 10 MHz Span V 76 dB ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 Supply Voltages Input Voltages EE to –2.5 V Output Currents Temperature ELECTRICAL SPECIFICATIONS TA= 25 °C, VEE =–5.2 V ±5%, 50% duty cycle clock, unless otherwise specified. TEST TEST SPT5510 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for nominal operating conditions. 1Measured at 0 V output using I-V. 2Measured as voltage settling for mid-scale transition; RL = 50 Ω .

TA= 25 °C, VEE =–5.2 V ±5%, 50% duty cycle clock, unless otherwise specified. TEST TEST SPT5510 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Power Supply Requirements Negative Supply Current (–5.2 V) TMIN –TMAX VI 115 150 mA Nominal Power Dissipation V 600 800 mW Power Supply Rejection Ratio ΔV Supply = ±5 % I –0.6 ±0.002 0.6 % FS Voltage Input and Control Bandgap Reference Voltage V –1.2 V Bandgap Output Current T A=25 °C ±10 °C IV –110 16 220 µA Ref Amp Bandwidth3 V 40 MHz Ref Amp Input Current V 16 µA Ref Amp Output Current V 200 µA Ref In Operating Voltage V –3.4 V Digital Inputs Logic 1 Voltage T MIN –TMAX VI –1.0 –0.8 V Logic 0 Voltage T MIN –TMAX VI –1.7 –1.5 V Logic 1 Current –0.8 V V 2.5 µA Logic 0 Current –1.8 V V 0 µA Input Capacitance V 3 pF Input Setup Time (tS) IV 3.0 ns Input Hold Time (tH ) IV 0.5 ns Clock Pulse Width (tPWH ) IV 1.5 ns 3Ref Amp Bandwidth is limited by its compensation network TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifi- cations are guaranteed. The Test Level column indicates the specific device testing actually performed during pro- duction and Quality Assurance inspec- tion. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at T A = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characterization data. V Parameter is a typical value for information purposes only. VI 100% production tested at T A = +25 °C. Parameter is guaranteed over specified temperature range.

The SPT5510 is a segmented 16-bit current-output DAC. The four MSBs, D15–D12, are decoded to fifteen unit cells (current sinks). The remaining bits (D11–D0) are binary; bits D9–D0 are derived from an R-2R ladder. All cells are laser trimmed for maximum accuracy. The block diagram shows the basic architecture. All output cells are always on, with the data determining whether a given cell’s current is routed from I OUT or IOUT . This provides nearly constant power dissipation indepen- dent of data and clock rate. It also reduces noise transients on power and ground lines. The reference loop utilizes an MSB-weighted cell and pro- vides a gain of about 16 to the output. The on-chip refer- ence amplifier has very high open-loop gain and is offset trimmed to provide a very low temperature drift (typically <10 ppm/°C gain drift). POWER SUPPLY AND GROUNDING The SPT5510 requires a single –5.2V power supply. All supply pins attach to a common on-chip power bus and should be treated as analog supplies. For best settling per- formance, each supply pin should be decoupled as shown in figure 1 – typical interface circuit. There are three separate on-chip ground busses. DGND pins should be tied together and connected to system ground through a ferrite bead. REFGND and OGND pins should be tied directly to the SPT5510’s ground plane and connected to system ground through a ferrite bead. It is critical that REFGND and OGND are very tightly coupled, as any differential signal (dc offset, noise, etc.) will be transmitted to the output. Two of the OGND pins can be disconnected from the ground plane and used as sense lines for a current-to-voltage converter, as shown in the OUTPUTS section. DGND DGND DGND DGND OGND OGND OGND OGND AV EE AV EE AV EE AV EE AV EE AV EE AV EE AV EE .01 µF .01 µF .01 µF .01 µF .01 µF C17 C16 C15 C14 2.2 µF 2.2 µF 2.2 µF 2.2 µF D15 D14 D13 D12 D11 D10 C6 .01 µF C11 47 pF C10 47 pF C9 47 pF C8 .01 µF C7 .01 µF C12 10 pF C13 20 pF R9 50 R8 1K R7 1K REFGND REFGND CLK BG OUT AMP INB R SET AMP CC AMP B AMP OUT REF IN IOUT IOUT C1–C13 — SURFACE MOUNT CERAMIC CHIP C14–C17 — TANTALUM R1–R6 — CARBON FILM 1/4 W R7–R10 — SURFACE MOUNT CERAMIC CHIP FB — FERRITE BEAD is to be located as closely to the device as possible. SPT5510 AV EE R10 FB AV EE Input Data Output Complementary Output Figure 1 – Typical Interface Circuit

As with all high-speed, high-resolution digital-to-analog con- verters, the initial accuracy of the device will degrade with both time and temperature. The graph shown in figure 7 can be used to determine the expected change in linearity per- formance over time when the device is operated at various ambient temperatures. This graph shows how long it will take for the SPT5510 linearity to change by 8 ppm (or 1/2 LSB) at any operating temperature. The top curve shown represents integral nonlinearity (ILE) changes; the bottom curve shows differential nonlinearity (DLE) changes. Figure 7 – Linearity Performance over Time Temperature (°C) Expected time required to produce an 8 ppm (1/2 LSB) linearity (ILE or DLE) shift as a function of temperature. 0 20 40 60 80 100 120 102 103 104 105 106 107 1 month 1 year 100 years 1000 years (Hours) ILE DLE around 300 MHz, the amplifier’s phase crossover point. The unity-gain bandwidth is roughly 700 MHz. Larger value capacitors exhibit lower self-resonance frequency and thus may not adequately compensate the reference amplifier. Large capacitors may also introduce low frequency tails which increase settling time. The DAC itself exhibits very broadband switching spikes (charge kickback) at the RSET node, which can contribute to amplifier instability if not sup- pressed. Note that the AMPINB input must not be directly bypassed, as this will short all feedback to ground, leading to severe oscillation. Compensation must be optimized for each application. As with any high-speed, high-resolution design, attention must be paid to grounding, decoupling, and parasitic elements that may cause instability. It may be wise to use a guard ring, and/or clear the board ground, around the reference amplifier’s inputs. All traces must be short, and capacitors with high self-resonance must be used. Compensation is perhaps the most challenging aspect of setting up the SPT5510. By slowly switching a full-scale data input (generating a low-frequency square wave), with appropriate clock timing, the DAC’s output can be observed using a suitable oscilloscope and spectrum analyzer to observe and suppress any oscillations caused by board and ther assistance if required. PACKAGE OUTLINE 44-Lead MQFP Index A B C D Pin 1 E F G H I J K INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.5098 0.5295 12.95 13.45 B 0.3917 0.3957 9.95 10.05 C 0.3917 0.3957 9.95 10.05 D 0.5098 0.5295 12.95 13.45 E 0.0311 0.0319 0.79 0.81 F 0.0118 0.0177 0.30 0.45 G 0.0768 0.0827 1.95 2.10 H 0.0039 0.0098 0.10 0.25 I 0.0287 0.0406 0.73 1.03 J 0.0630 REF 1.60 REF K0 ° 7° 0° 7° decoupling parasitics. Consult CADEKA Applications for fur-

D15–D0 Digital Input Bits – all inputs high sends all current to IOUT , none to IOUT CLK Clock – latches D flip-flops IOUT Analog Current Output IOUT Complementary Analog Current Output BG OUT Bandgap Voltage Reference AMP INB Ref Amp’s Inverting Input R SET Ref Amp’s Non-Inverting Input – connection for reference-current-setting resistor, nominally 1kΩ to ground AMP OUT Bias Voltage for Output Current Switches – drives REFIN (on-chip 20 Ω resistor for compensation) REF IN Bias Voltage Node for Output Current Switches – driven by AMPOUT AMP B Used to Decouple Ref Amp’s Circuits to AVEE AMP CC AMP OUT plus on-chip 10 Ω series resistor for compensation AV EE Negative Supply – –5.2 V DGND Digital Ground Return OGND Output Ground Return REFGND Reference Amplifier Ground Return

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE SPT5510SIM –40 to +85 °C 44L MQFP PIN ASSIGNMENTS DGND AVEE OGND OGND AVEE AVEE OGND IOUT OGND AVEE REFGND AVEE AVEE AMPB BGOUT RSET AMPINB AMPCC AMPOUT REFIN REFGND DGND D0 (LSB) DGND AV EE (MSB) D15 D14 D13 D12 D11 D10 CLK DGND AV EE 11 SPT5510 44-Pin MQFP IOUT