SPT5420SIM

SPT5420 CADEKA | Alldatasheet

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Technical content

/MT45 /MT43 /MT45 /MT43 /MT45 /MT43 /MT45 /MT43 /MT86/MT79/MT85/MT84/MT48 /MT86/MT79/MT85/MT84/MT49 /MT86/MT79/MT85/MT84/MT50 /MT86/MT79/MT85/MT84/MT51 /MT86/MT79/MT85/MT84/MT52 /MT86/MT79/MT85/MT84/MT53 /MT86/MT79/MT85/MT84/MT54 /MT86/MT79/MT85/MT84/MT55 /MT45 /MT43 /MT45 /MT43 /MT45 /MT43 /MT45 /MT43 /MT76/MT69 /MT68/MT81 /MT76/MT69/MT65/MT55 /MT76/MT69 /MT68/MT81/MT55/MT65 /MT55/MT66 /MT76/MT69 /MT68/MT81 /MT76/MT69/MT65/MT54 /MT76/MT69 /MT68/MT81/MT54/MT65 /MT54/MT66 /MT76/MT69 /MT68 /MT81 /MT76/MT69/MT65/MT53 /MT76/MT69 /MT68 /MT81/MT53/MT65 /MT53/MT66 /MT76/MT69 /MT68/MT81 /MT76/MT69/MT65/MT52 /MT76/MT69 /MT68/MT81/MT52/MT65 /MT52/MT66 /MT76/MT69 /MT68/MT81 /MT76/MT69/MT65/MT51 /MT76/MT69 /MT68/MT81/MT51/MT65 /MT51/MT66 /MT76/MT69 /MT68/MT81 /MT76/MT69/MT65/MT50 /MT76/MT69 /MT68/MT81/MT50/MT65 /MT50/MT66 /MT76/MT69 /MT68/MT81 /MT76/MT69/MT65/MT49 /MT76/MT69 /MT68/MT81/MT49/MT65 /MT49/MT66 /MT76/MT69 /MT68/MT81 /MT76/MT69/MT65/MT48 /MT76/MT69 /MT68/MT81/MT48/MT65 /MT48/MT66 /MT67/MT111/MT110/MT116/MT114/MT111/MT108 /MT76/MT111/MT103/MT105/MT99 /MT87/MT82 /MT67/MT83 /MT65/MT48/MT150/MT65/MT50 /MT76/MT68/MT65/MT67 /MT76/MT69/MT65/MT48/MT150/MT76/MT69/MT65/MT55 /MT56 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT49/MT51 /MT68/MT65/MT67/MT48 /MT68/MT65/MT67/MT49 /MT68/MT65/MT67/MT50 /MT68/MT65/MT67/MT51 /MT68/MT65/MT67/MT52 /MT68/MT65/MT67/MT53 /MT68/MT65/MT67/MT54 /MT68/MT65/MT67/MT55 /MT86/MT82/MT69/MT70/MT84/MT48/MT49/MT86/MT82/MT69/MT70/MT66/MT48/MT49 /MT67/MT76/MT82 /MT82/MT71/MT78/MT68/MT48/MT49/MT82/MT71/MT78/MT68/MT50/MT51 /MT82/MT71/MT78/MT68/MT54/MT55/MT82/MT71/MT78/MT68/MT52/MT53 /MT68/MT48/MT150/MT68/MT49/MT50 /MT76/MT68/MT65/MT67 /MT86/MT82/MT69/MT70/MT84/MT50/MT51/MT52/MT53/MT86/MT82/MT69/MT70/MT66/MT50/MT51/MT52/MT53/MT86/MT82/MT69/MT70/MT84/MT54/MT55/MT86/MT82/MT69/MT70/MT66/MT54/MT55 /MT76/MT68/MT65/MT67 /MT76/MT68/MT65/MT67 /MT76/MT68/MT65/MT67 /MT76/MT68/MT65/MT67 /MT76/MT68/MT65/MT67 /MT76/MT68/MT65/MT67 /MT76/MT68/MT65/MT67 /MT76/MT68/MT65/MT67 SPT5420 13-BIT, OCTAL D/A CONVER TER TECHNICAL D ATA JUNE 26, 2001 FEA TURES

• 13-bit resolution Pin compatible with AD7839 Eight DACs in one package Buffered voltage outputs Wide output voltage swing V DD –2.5 V to VSS +2.5 V 15 µs settling time to ±0.5 LSB Doub le-buffered digital inputs Microprocessor and TTL/CMOS compatible APPLICA TIONS Automatic test equipment Instrumentation Process control GENERAL DESCRIPTION The SPT5420 contains eight 13-bit digital-to-analog CMOS con verters designed primarily for automatic test equipment applications. It uses novel circuit topology to convert the 13-bit digital inputs into output voltages which are proportionate to the applied reference voltages. Each DAC’s full-scale output voltage and output voltage offset are adjustable with analog inputs (RGND, VREFB , VREFT ). The SPT5420 operates over an industrial temperature range of –40 °C to +85 °C and is available in a 10 x 10 mm, 44-lead metric quad flat pack (MQFP) plastic package. BLOCK DIA GRAM

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TEST TEST SPT5420 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Accuracy Resolution VI 13 Bits Integral Linearity Error (ILE) VI –2.0 ±0.5 +2.0 LSB Differential Linearity Error (DLE) VI –1.0 ±0.3 +1.0 LSB Zero-Scale Error VI –25 +25 mV Full Scale Error VI –25 +25 mV Gain Error VI –25 +25 mV Reference Inputs Input Current IV ±100 nA VREFT 1 VI 0 +3.5 +5.0 V VREFB 2 VI –5.0 –1.5 0 V RGND Inputs DC Input Impedance V 60 k Ω Input Range IV –2.0 2.0 V Output Characteristics Output Swing3,4 VI +7/–3 V Short Circuit Current IV 15 mA Resistive Load VI 5 k Ω DC Output Impedance IV 1.0 Ω Digital Inputs Logic 1 Voltage VI 2.4 V Logic 0 Voltage VI 0.8 V Maximum Input Current VI –10 10 µA/pin Input Capacitance V 10 pF Supply Voltages Input Voltages Temperature Notes: 1. VREFT < 8 V + (VSS x 0.5); e.g., if VSS = –8 V, then VREFT < 4 V VSS + 2.5 V ≤ VOUT ≤ VDD – 2.5 V for VDD – VSS ≤ 18.5 V 4. VOUT = 2 X (VREFB +[VREFT – VREFB ] X INPUT CODE 8192 ) – VRGND

All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. ELECTRICAL SPECIFICATIONS TEST TEST SPT5420 PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Power Requirements VCC Supply Voltage (Digital) IV 4.75 5 5.25 V VDD Supply Voltage (Analog)1,2 VI 5 11.5 12.5 V VSS Supply Voltage (Analog)1,2 VI –12.5 –8 –5V ICC Supply Current VI 0.5 mA IDD Supply Current Outputs Unloaded VI 5 10 mA ISS Supply Current Outputs Unloaded VI 5 10 mA Power Supply Rejection Ratio ∆VDD / ∆Full Scale IV 80 dB ∆VSS / ∆Full Scale IV 80 dB Dynamic Performance Output Settling Time3 (Full Scale Change to ±0.5 LSB) CL ≤ 220 pF IV 15 µs Slew Rate V 2.0 V/µs Glitch Impulse V 35 nV-s Channel to Channel Isolation V 100 dB DAC to DAC Crosstalk V 40 nV-s Digital Crosstalk V 1 nV-s Digital Feedthrough V 1 nV-s Timing Characteristics (See page 4) IV 1. Supplies should provide 2.5 V headroom above and below max output swing. 2. VDD – VSS ≤ 20 V 3. Output can drive 10,000 pF without oscillation, but with settling time degradation. DEFINITION OF SELECTED TERMINOLOGY Channel-to-Channel Isolation Channel-to-Channel isolation refers to the proportion of input signal from one DAC’s reference input that appears at the output of the other DAC. It is expressed in dBs. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is defined as the glitch impulse that appears at one DAC’s output due to both the digital change and subse- quent analog output change at any other DAC. It is specified in nV-s. Digital Crosstalk The glitch impulse transferred to one DAC’s output due to a change in digital input code of any other DAC. It is specified in nV-s. Digital Feedthrough Digital feedthrough is the noise at a DAC’s output caused by changes to D0–D12 while WR is high.

Three VREFTXX and three VREFBXX inputs set the output range of the three corresponding groups of DACs (0 and 1; 2 through 5; 6 and 7). Four RGND XX inputs set the output offset voltage of the four corresponding groups of DACs (0 and 1; 2 and 3; 4 and 5; 6 and 7). The formula for output swing and offset is presented in the “Analog Outputs” section below. DAC ADDRESSING AND LATCHING Each DAC has an input latch which receives data from the data bus, and a DAC latch which receives data from the input latch. The analog output of each DAC corresponds to the data in its DAC latch. One of the eight input latches is addressed by the address lines A(2:0) according to Table I. While CS and WR are low, the addressed input latch is transparent and the seven other input latches are latched. Bringing CS or WR high latches data into the ad- dressed input latch. While LDAC is low, all eight DAC latches are transparent. Bringing LDAC high latches data into the DAC latches. While CS , WR and LDAC are low, both latches are transparent and input data is transferred directly to the selected DAC. While CLR is low, all DAC out- puts are set to their corresponding RGNDXX . Bringing CLR high returns each DAC’s output to the voltage correspond- ing to the data in each DAC latch. Table II summarizes this information, and figures 1a and 1b should be referenced for timing limitations. POWER SUPPLY SEQUENCING The sequence in which VDD , VSS and VCC come up is not critical. The reference inputs, VREFTXX and VREFBXX , must come on only after VDD and VSS have been established. However, they may be turned on prior to VCC . The digital inputs must be driven only after VDD , VSS and VCC have been established. Reverse the power-on sequence for power-down. ANALOG OUTPUTS VS DIGITAL INPUT CODE The output voltage range is equal to twice the difference between VREFTXX and VREFBXX . The output voltage is given by: VOUT = 2 X (VREFB +[VREFT – VREFB ] X INPUT CODE 8192 ) – VRGND CODE = 0 – 8191 Table I – DAC Addressing Addressed Input A2 A1 A0 Latch DAC# 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Table II – Control Logic Table WR CS LDAC CLR Input Latch DAC Latch 0 0 x 1 transparent 1 x 1 x x 1 latched x x 1 x 1 latched x x x 0 1 x transparent x x 1 1 x latched x x x 0 DAC outputs at RGND XX Note: 1. Only the input latch addressed by A(2:0) is transparent. The other input latches are latched.

/MT49 /MT49/MT48 /MT49/MT48/MT48 /MT49/MT48/MT48/MT48 /MT49/MT48/MT48/MT48/MT48 /MT49/MT49/MT46/MT50/MT48 /MT49/MT49/MT46/MT55/MT48 /MT49/MT50/MT46/MT50/MT48 /MT49/MT51/MT46/MT57/MT48 /MT49/MT55/MT46/MT57/MT48 /MT50/MT54/MT46/MT53/MT48 /MT53/MT50/MT46/MT48/MT48 /MT55/MT48/MT46/MT48/MT48 /MT83/MT101/MT116/MT116/MT108/MT105/MT110/MT103/MT32/MT84/MT105/MT109/MT101/MT32/MT116/MT111/MT32/MT177/MT48/MT46/MT53/MT32/MT76/MT83/MT66/MT32/MT40/MT181/MT83/MT41 /MT67/MT97/MT112/MT97/MT99/MT105/MT116/MT97/MT110/MT99/MT101/MT32/MT40/MT112/MT70/MT41 TYPICAL PERFORMANCE CHARACTERISTICS /MT67/MT111/MT100/MT101 /MT73/MT76/MT69/MT32/MT40/MT76/MT83/MT66/MT115/MT41 /MT150/MT49/MT46/MT48/MT48 /MT150/MT48/MT46/MT56/MT48 /MT150/MT48/MT46/MT54/MT48 /MT150/MT48/MT46/MT52/MT48 /MT150/MT48/MT46/MT50/MT48 /MT48/MT46/MT48/MT48 /MT48/MT46/MT50/MT48 /MT48/MT46/MT52/MT48 /MT48/MT46/MT54/MT48 /MT48/MT46/MT56/MT48 /MT49/MT46/MT48/MT48 /MT48 /MT49/MT52/MT52/MT48 /MT50/MT56/MT56/MT48 /MT52/MT51/MT50/MT48 /MT53/MT55/MT54/MT48 /MT55/MT50/MT48/MT48 /MT84/MT101/MT109/MT112/MT101/MT114/MT97/MT116/MT117/MT114/MT101/MT32/MT176/MT67 /MT52 /MT53 /MT54 /MT55 /MT56 /MT150/MT52/MT48 /MT48 /MT50/MT53 /MT55/MT48 /MT56/MT53 /MT73/MT83/MT83 /MT73/MT68/MT68 /MT86/MT68/MT68/MT61/MT49/MT50/MT32/MT86 /MT86/MT83/MT83/MT61/MT150/MT56/MT32/MT86 /MT86/MT82/MT69/MT70/MT84/MT61/MT43/MT53/MT32/MT86 /MT86/MT82/MT69/MT70/MT66/MT61/MT150/MT53/MT32/MT86 /MT83/MT117/MT112/MT112/MT108/MT121/MT32/MT67/MT117/MT114/MT114/MT101/MT110/MT116/MT32/MT40/MT109/MT65/MT41 /MT50/MT32/MT181/MT83 /MT50/MT32/MT109/MT86/MT47/MT100/MT105/MT118 /MT111/MT117/MT116/MT112/MT117/MT116/MT32/MT103/MT108/MT105/MT116/MT99/MT104 /MT87/MT82 /MT99/MT111/MT100/MT101/MT32/MT48/MT70/MT70/MT70/MT72/MT32/MT116/MT111/MT32/MT49/MT48/MT48/MT48/MT72 /MT50/MT32/MT86/MT47/MT100/MT105/MT118 Integral Linearity Error vs Code Differential Linearity Error vs Code IDD /ISS vs Temperature Digital-to-Analog Glitch Impulse DAC to DAC Crosstalk Load Capacitance vs Settling Time VSWING =10 V /MT67/MT111/MT100/MT101 /MT68/MT76/MT69/MT32/MT40/MT76/MT83/MT66/MT115/MT41 /MT150/MT49/MT46/MT48/MT48 /MT150/MT48/MT46/MT56/MT48 /MT150/MT48/MT46/MT54/MT48 /MT150/MT48/MT46/MT52/MT48 /MT150/MT48/MT46/MT50/MT48 /MT48/MT46/MT48/MT48 /MT48/MT46/MT50/MT48 /MT48 /MT49/MT52/MT52/MT48 /MT50/MT56/MT56/MT48 /MT52/MT51/MT50/MT48 /MT53/MT55/MT54/MT48 /MT55/MT50/MT48/MT48 /MT50/MT32/MT181/MT83 /MT50/MT32/MT109/MT86/MT47/MT100/MT105/MT118 /MT99/MT111/MT100/MT101/MT32/MT48/MT70/MT70/MT70/MT72/MT32/MT116/MT111/MT32/MT49/MT48/MT48/MT48/MT72 /MT68/MT65/MT67/MT32/MT116/MT111/MT32/MT68/MT65/MT67/MT32/MT103/MT108/MT105/MT116/MT99/MT104

TYPICAL PERFORMANCE CHARACTERISTICS PACKAGE OUTLINE 44-Lead MQFP Index A B C D Pin 1 E F G H I J K INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.5098 0.5295 12.95 13.45 B 0.3917 0.3957 9.95 10.05 C 0.3917 0.3957 9.95 10.05 D 0.5098 0.5295 12.95 13.45 E 0.0311 0.0319 0.79 0.81 F 0.0118 0.0177 0.30 0.45 G 0.0768 0.0827 1.95 2.10 H 0.0039 0.0098 0.10 0.25 I 0.0287 0.0406 0.73 1.03 J 0.0630 REF 1.60 REF K0 ° 7° 0° 7° Slew and Settling TimeDigital Feedthrough /MT50/MT32/MT181/MT83 /MT50/MT32/MT109/MT86/MT47/MT100/MT105/MT118 /MT99/MT111/MT100/MT101/MT32/MT48/MT70/MT70/MT70/MT72/MT32/MT116/MT111/MT32/MT49/MT48/MT48/MT48/MT72 /MT100/MT105/MT103/MT105/MT116/MT97/MT108/MT32/MT102/MT101/MT101/MT100/MT116/MT104/MT114/MT111/MT117/MT103/MT104 /MT67/MT76/MT61/MT53/MT48/MT32/MT112/MT70 /MT82/MT76/MT61/MT49/MT48/MT32/MT107/MT87 /MT99/MT111/MT100/MT101/MT32/MT48/MT48/MT48/MT48/MT72/MT32/MT116/MT111/MT32/MT49/MT70/MT70/MT70/MT72 /MT111/MT117/MT116/MT112/MT117/MT116 /MT50/MT48/MT32/MT109/MT86/MT47/MT100/MT105/MT118 /MT111/MT117/MT116/MT112/MT117/MT116 /MT50/MT32/MT86/MT47/MT100/MT105/MT118 /MT49/MT32/MT181/MT83

PART NUMBER TEMPERATURE RANGE PACKAGE SPT5420SIM –40 to +85 °C 44L MQFP CLR (Active Low) Analog Clear. Sets the output voltages to RGND. (Each RGND is common to a DAC pair.) CLR does not reset the digital latches. When CLR is brought back high, the DAC outputs revert back to their original outputs as determined by the data in their DAC latches. LDAC When this logic input is taken low, the contents of the input latches are transferred to their respective DAC latches. (Active Low) Data is latched on rising edge. A0 – A2 Addresses DAC0 to DAC7 for loading the eight input latches. D0 – D12 Digital Inputs (D0 = LSB) ANALOG PINS VREFT01 Top Reference Voltage for DACs 0 and 1 VREFT2345 Top Reference Voltage for DACs 2, 3, 4 and 5 VREFT67 Top Reference Voltage for DACs 6 and 7 VREFB01 Bottom Reference Voltage for DACs 0 and 1 VREFB2345 Bottom Reference Voltage for DACs 2, 3, 4 and 5 VREFB67 Bottom Reference Voltage for DACs 6 and 7 RGND 01 Reference Ground for Output Amplifiers 0 and 1 RGND 23 Reference Ground for Output Amplifiers 2 and 3 RGND 45 Reference Ground for Output Amplifiers 4 and 5 RGND 67 Reference Ground for Output Amplifiers 6 and 7 VOUT0 –7 Output Voltage Pins for DAC0 – DAC 7 PO WER SUPPL Y PINS VCC Digital +5 V Supply VDD Analog +11.5 V Supply (Nominal) VSS Analog –8 V Supply (Nominal) GND Ground PIN ASSIGNMENTS /MT86/MT79/MT85/MT84/MT54 /MT86/MT79/MT85/MT84/MT53 /MT82/MT71/MT78/MT68/MT52/MT53 /MT86/MT79/MT85/MT84/MT52 /MT86/MT68/MT68 /MT86/MT82/MT69/MT70/MT84/MT50/MT51/MT52/MT53 /MT86/MT82/MT69/MT70/MT66/MT50/MT51/MT52/MT53 /MT86/MT79/MT85/MT84/MT51 /MT82/MT71/MT78/MT68/MT50/MT51 /MT86/MT79/MT85/MT84/MT50 /MT86/MT79/MT85/MT84/MT49 /MT68/MT55 /MT68/MT54 /MT68/MT53 /MT68/MT52 /MT68/MT51 /MT68/MT50 /MT68/MT49 /MT68/MT48/MT32/MT40/MT76/MT83/MT66/MT41 /MT71/MT78/MT68 /MT86/MT67/MT67 /MT87/MT82 /MT84/MT111/MT112/MT32/MT86/MT105/MT101/MT119 /MT52/MT52 /MT49/MT82/MT71/MT78/MT68/MT48/MT49 /MT86/MT79/MT85/MT84/MT48 /MT86/MT82/MT69/MT70/MT66/MT48/MT49 /MT86/MT82/MT69/MT70/MT84/MT48/MT49 /MT86/MT68/MT68 /MT86/MT83/MT83 /MT76/MT68/MT65/MT67 /MT65/MT50 /MT65/MT49 /MT65/MT48 /MT67/MT83 /MT82/MT71/MT78/MT68/MT54/MT55 /MT86/MT79/MT85/MT84/MT55 /MT86/MT82/MT69/MT70/MT66/MT54/MT55 /MT86/MT82/MT69/MT70/MT84/MT54/MT55 /MT86/MT83/MT83 /MT68/MT49/MT50/MT32/MT40/MT77/MT83/MT66/MT41 /MT68/MT49/MT49 /MT68/MT49/MT48 /MT68/MT57 /MT68/MT56 /MT67/MT76/MT82 PIN FUNCTIONS Name Function DIGITAL CONTR OL PINS CS Chip Select (Active Low) WR Level Triggered Wr ite Input (Active Low). Used in conjunction with CS to write data to the SPT5420 input data latches. Data is latched into selected input data latch on the rising edge of WR .