SPT5310SIP

SPT5310 CADEKA | Alldatasheet

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12-BIT, 250 MWPS ECL D/A CONVERTER FEATURES APPLICATIONS + 12-Bit, 250 MWPS Digital-to-Analog Converter + Fast Frequency Hopping Spread Spectrum Radios + ECL Compatibility + Direct Sequence Spread Spectrum Radios + Low Glitch Energy: 15 pV-s + Microwave and Satellite Modems + Low Power: 600 mW + Test & Measurement Instrumentation + 40 MHz Multiplying Bandwidth + Military Applications + Master-Slave Latches + Industrial Temperature Range GENERAL DESCRIPTION impulse energy of 15 pV-s that results in excellent spurious The SPT5310 is a 12-bit, 250 MWPS digital-to-analog con- free dynamic range characteristics. verter designed for direct digital synthesis, high resolution imaging and arbitrary waveform generation applications. The © The SPT5310is available in 28-lead plastic DIPs and 28-lead SPT5310is an ECL-compatible device. Itfeatures alowglitch | PLCCs in the industrial temperature range (-40 to +85 °C). BLOCK DIAGRAM Rset + Control Control Amp Amp Out Control Amp In - Internal Ref Out Voltage Reference Latch Enable aaa Ref In || use Li ro"? mz : - lout = ; ui Digital |] Decoders [] 8 J ; Inputs [—} and Sf Switch Di [—] Drives (5 Netvors through mz, Li CJ D12 mz, Yr) [J lout =z tL} || se) tL} (J

ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1 Supply Voltages Output Currents Input Voltages Temperature Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS Ta= Tmin - Tmax, VEE = -5.2 V, RSET = 7.5 kQ, Control Amp In = Ref Out, Vour = 0 V, unless otherwise specified. TEST TEST SPT5310 PARAMETERS CONDITIONS LEVEL MIN TYP MAX | UNITS DC Performance Resolution 12 Bits Differential Linearity 1 +1.0 $1.25 LSB Differential Linearity Max at Full Temp. vi 42.0 LSB Integral Linearity Best Fit 1 +1.0 315 LSB Integral Linearity Max at Full Temp. vi +2.0 LSB Output Capacitance +25 °C 10 pF Gain Errort +25 °C 1 1.0 5.0 %FS Full Temp. vi 8.0 | %FS Gain Error Tempco. Full Temp. Vv 150 PPM/’°C Zero-Scale Offset Error +25 °C 1 0.5 25 HA Full Temp. vi 5.0 HA Offset Drift Coefficient Full Temp. Vv 0.01 pAC Output Compliance Voltage +25 °C. IV 1.2 +2.0 Vv Equivalent Output Resistance +25 °C. lV 0.8 1.0 12) kQ Dynamic Performance Conversion Rate +25 °C lV 250 MWPS Settling Time tg72 +25 °C Vv 13 ns Output Propagation Delay tp 3 +25 °C Vv 1 ns Glitch Energy4 +25 °C Vv 15 pV-s Full Scale Output Currents +25 °C Vv 20.48 mA 1Gain is measured as a ratio of the full-scale current to IsET. The ratio is nominally 128. 2Measured as voltage at mid-scale transition to +0.024%; RL=50 2. 3Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band. 4Glitch is measured as the largest single transient. 5Calculated using Irg =128 a 8SFDRis defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at the fundamental frequency and covers the indicated span. SPT5310 2 4nis7

TAa= Tmin- Tmax. Vee = -5.2 V, Rset = 7.5 kQ, Control Amp In = Ref Out, Vout = 0 V, unless otherwise specified. TEST TEST SPT5310 Byanmic Performance Spurious-Free Dynamic Range 6] +25 °C

5.055 MHz; 20 MWPS 2 MHz Span Vv 63 dBc

10.055 MHz; 40 MWPS 2 MHz Span Vv 58 dBc

20.055 MHz; 80 MWPS 2 MHz Span Vv 56 dBc

40.055 MHz; 160 MWPS 2 MHz Span v 54 dBc

60.055 MHz; 240 MWPS 2 MHz Span Vv 46 dBc

Rise Time / Fall Time Ri =50Q Vv 2 ns Power Supply Requirements Negative Supply Voltage IV ~5.46 5.2 494) V Negative Supply Current (-5.2 V)]|_ +25 °C | 115 140 mA Full Temp vi 148 mA Nominal Power Dissipation Vv 600 mW Power Supply Rejection Ratio +5% of Vee | 30 100 HAV External Ref, +25 °C Voltage Input and Control Reference Input Impedance +25 °C Vv 3 kQ. Ref. Multiplying Bandwidth +25 °C v 40 MHz Internal Reference Voltage vi 1.15 1,20 1.25 | V Internal Reference Voltage Drift Vv 50 ppmicC Amplifier Input Impedance +25 °C Vv 3 MQ Amplifier Input Bandwidth +25 °C Vv 1 MHz Digital Inputs Logic 1 Voltage Full Temp. vi -1.0 0.8 Vv Logic 0 Voltage Full Temp. vi -1.7 1.5 Vv Logic 1 Current Full Temp. vi 20 | pA Logic 0 Current Full Temp. vi 10 pA Input Capacitance +25 °C Vv 3 pF Input Setup Time - ts +25 °C IV 3 2 ns Input Setup Time - ts Full Temp. IV 3.5 ns Input Hold Time - tH +25 °C IV 0.5 0 ns Input Hold Time - ty Full Temp. IV 0.5 ns Latch Pulse Width - tpwi, tpwH | +25 °C Vv 4.0 3.3 ns TEST LEVEL CODES TESTLEVEL TEST PROCEDURE All electrical characteristics are subject to the I 100% production tested at the specified temperature. following conditions: All parameters having min/ Il 100% production tested at Ta=25 °C, and sample max specifications are guaranteed. The Test tested at the specified temperatures. Level column indicates the specific device test- . ing actually performed during production and Ml QA sample tested only at the specified temperatures. Quality Assurance inspection. Any blank sec- IV Parameter is guaranteed (but not tested) by design tion in the data column indicates that the speci- and characterization data. fication is not tested at the specified condition. Vv Parameter is a typical value for information purposes only. Vi 100% production tested at Ta = 25 °C. Parameter is guaranteed over specified temperature range. SPT5310 3 ans?

THEORY OF OPERATION Referring to figure 1, datais latched into the DAC on the rising edge of the latch enable clock with the associated setup and The SPT5310 uses a segmented architecture incorporating _hold times. The output transition occurs after a typical 1 ns most significant bit (MSB) decoding. The four MSBs (D1-D4) propagation delay and settles to within +1 LSB in typically are decoded to thermometer code lines to drive 15 discrete 13s. Because of the SPT5310’s rising edge-triggering, no current sinks. For the eight least significant bits (LSBs), D5 timing changes are required when replacing an AD5310 and D6 are binary weighted and D7-D12 are applied to the 0perating in nontransparent mode. R-2R network. The 12-bit decoded data is input to internal master/slave latches. The latched data is input to the switche VOLTAGE REFERENCE ing network and is presented on the output pins as comple- mentary current outputs. When using the internal reference, Ref Out should be con- nected to Control Amp In and decoupled with a 0.1 uF TYPICAL INTERFACE CIRCUIT capacitor. Control Amp Out should be connected to Ref In and decoupled to the analog supply. (See figure 2.) The SPT5310 requires few external components to achieve the stated operation and performance. Figure 2 shows the Full-scale output currentis determined by Control Amp In and typical interface requirements when using the SPT5310 in _F’Set using the following formula: normal circuit operation. The following sections provide de- scriptions of the pin functions and outlines critical perfor- lout (FS) = (Control Amp In / Rget) x 128 mance criteria to consider for achieving optimal device per- (Current out is a constant 128 factor of the formance: reference current) The internal reference is typically -1.20 V with a tolerance of POWER SUPPLIES AND GROUNDING +0.05 V and a typical drift of 50 ppm/°C. If greater accuracy or temperature stability is required, an external reference can The SPT5310 requires the use of a single -5.2 V supply. All be utilized. supplies should be treated as analog supply sources. This means the ground returns of the device should be connected OUTPUTS to the analog ground plane. All supply pins should be by- The output of the SPT5310 is comprised of complementary passed with OTKF and 10)1F decoupling capacitors.as close currentsinks, loutand !Out. The output currentlevels at either to the device as possible. _ i aie lout or 'ui are based upon the digital input code. The sum The two grounds available on the SPT5310 are DGND and of the ‘wo is always equal to the full-scale output current AGND. These grounds are not tied together internal to the . device. The use of ground planes is recommended to achieve By terminating the output current through a resistive load to the best performance ofthe SPT5310. All ground, Teference ground, an associated voltage develops. The effective resis- and analog output pins should be tied to directly to the DAC tive load (Re#) is the output resistance of the device (Rout) in ground plane. The DAC and system ground planes should pe parallel with the resistive load (RL). The voltage which devel- separate from each other and only connected ata single point ops can be determined using the following formulas: through a ferrite bead to reduce ground noise pickup. Control Amp Out = -1.2 V, and Rget = 7.5 kQ DIGITAL INPUTS AND TIMING lout (FS) = (-1.2 V/7.5 kQ) x 128 = -20.48 mA RL =51Q The SPT5310 uses single-ended, 10K ECL-compatible in- Rout = 1.0 kQ puts for data inputs D1-D12 and Latch Enable. It also em- Regt = 51 Q || 1.0 kQ = 48.52 Q ploys master/slave latches to simplify digital interface timing Vout = Rest x lout (FS) = 48.52 Q x -20.48 mA requirements and reduce glitch energy by synchronizing the = -0.994 V current switches. This is an improvement over the AD5310, which typically requires external latches for digital input | The resistive load of the SPT5310 can be modified to incor- synchronization. porate a wide variety of signal levels. However, optimal device performance is achieved when the outputs are equiva- lently loaded. SPT5310 4 anit

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PIN ASSIGNMENTS PIN FUNCTIONS be D1 (MSB) . z ie Name Function fz] DGND os Ll ez Pe Out+ Analog Current Output oa [sl [28] etch Enable Out- ‘Complementary Analog Current Output os [4] [23] Analog Vee Di-Di2 Digital Input Bits (D712 is the LSB) pe [3] Rset Latch Enable Latch Control Line o7 NIC Ref In Voltage Reference Input DB Ref GND Ref Out Internal Voltage Reference Output ve Fa] Diba Veg Normally Connected to Control Amp In Ref GND Ground Return For Internal Voltage oo ial ato Reference and Amplifier o14 [2] [32] Control Amp tn Control Amp In Normally Connected to Ref Out If Not (LSB) D12 [78] Control Amp Out Connected to External Reference Digital Veg: [22] Ref In Control Amp Out Output of Internal Control Amplifier ‘Analog Return fe] ‘out Normally Connected to Ref In lout [i] [ra] Anslo9 Vee Rset! Connection for External Resistance Reference When Using Internal Amplifier e Nominally 7.5 kQ z & Analog Return —_ Analog Return Ground Fa geese ts A ‘Analog VEE ‘Analog Negative Supply (-5.2 V) Gl fl fl) fel Digital Vee Digital Negative Supply (-5.2 V) fo s—~»Y DGND Digital Ground Return 6 [a] [2JAnalog Ver NIC Not Connected o7[a [3Rset psf] [ne 1Full-Scale Current Out=128 (Control Amp In/Rset) | Blce [2] Ret GND o10La| [pista vee pit [2]Ref Out (uss) o12[44 [Control Amp in ERE) ERE gig peies Ee" g #8 3 2

ORDERING INFORMATION

PART NUMBER DNL/INL PACKAGE SPT5310 SIN £1.25/41.5 28L PDIP SPT5310 SIP E2515 28L PLCC For additional information regarding our products, please visit CADEKA at: cadeka.com (CADEKA Headquarters Loveland, Colorado . . sore i CADEKA T: 877.663.5452 (toll free) Amplify the Human Experience CCADEKA, the CADEKA ogo cesign, Cominear, and the Comlneat logo design are trademarks or registered trademarks of CADEKA Microcrcusts LLC. All other brand and product nares may be trademarks of thew respectiv> companies. CCADEKA «eserves the right to make changes to any product and services herein at any time vathout notice. CADEKA does nat assume cry responsibilty or habilty arising out ofthe application oF use of any product or service described herein, except 2s expressly agreed to in wering by CADEKA, nor docs the purchase, lease, ar use ofa product or service from CADEKA convey & lcense under any patent rights, copynghts, trademark rights, or any other of the intellectual property "ights of CADEKA or of third parties. Copyright ©2007-2009 by CADEKA Miciocrcuits LLC. All nghts reserved SPT5310 8 497