SPT5230 FAIRCHILD | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 7

Technical content

10-BIT, 36 MWPS TRIPLE VIDEO DAC Current Switch Cell Array (Cell 4) Current Switch Cell Array (Cell 255) Latch Decoder Latch R OUT CLKR VCS VREF Current Switch Cell Array (Cell 255) Latch Decoder Latch BOUT CLKB Latch Decoder Latch Current Switch Cell Array (Cell 255) G OUT CLKG AV DD IOR IOB VSSAIOG (LSB) DRØ DR1DR2DR3DR4DR5DR6DR7 (MSB) DR9 DR8 (LSB) DGØ DG1DG2DG3DG4DG5DG6DG7 (MSB) DG9 DG8 (LSB) DBØ DB1DB2DB3DB4DB5DB6DB7 (MSB) DB9 DB8 VREF1 Current Switch Cell Array (Cell 4) Current Switch Cell Array (Cell 4)VREF2 VCS2 VCS1 AV DD AV DD AV DD

FEATURES

  • 10-Bit Triple Video Digital-to-Analog Converter
  • Output Full-Scale Voltage 0.5 to 2.0 Vp-p
  • 36 MWPS Operation (typ)
  • Low Power: 280 mW (1 Vp-p Output)
  • 5 V Monolithic CMOS
  • 52-pin QFP Package (10mm x 10mm, 0.65 mm pitch)

APPLICATIONS

  • Desktop Video Processing
  • CCIR-601 Video Signal Processing
  • RGB Color Monitors
  • Image Processing
  • Direct Digital Synthesis the full-scale output current. The differential linearity errors of the DACs are guaranteed to be a maximum of ±1.0 LSB over the full temperature range. The device is available in a 52- lead QFP package over the commercial temperature range. GENERAL DESCRIPTION The SPT5230 is a 10-bit, 36 MWPS triple video digital-to- analog converter specifically designed for high performance, high resolution color graphics monitor applications and video processing applications. A single external resistor controls BLOCK DIAGRAM

Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 Supply Voltages Input Voltage Output Current Temperature ELECTRICAL SPECIFICATIONS fCLK = 27 MWPS, AVDD = 5.0 V, Output Pull-Up Load = 75 Ω , TA = 25 °C, AVSS = 0.0 V TEST TEST PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC Performance Resolution 10.0 Bits Differential Linearity T A = TMIN to TMAX I –1.0 1.0 LSB Integral Linearity I –2.5 2.0 LSB Analog Outputs Output Voltage Range V CS2 = +2.1 V I 3.0 5.0 V Conversion Rate I 27 36 MWPS Output Offset Voltage I 2.4 14 mV Signal-to-Noise Ratio I 46 52 dB Settling Time

1 I1 6 2 3 n s

Propagation Delay (tpd) V 10 12 ns Crosstalk I –49 –54 dB FS Control Voltage (VCS2 ) V 2.0 4.0 V Digital Inputs and Timing Input Current, Logic High V IH = 5 V I 5 µA Logic Low V IL = 0 V I –5 µA Set-Up Time, Data and Controls (tS)I 5 n s Hold Time, Data and Controls (th) I 10 ns Clock Duty Cycle V 40 60 % Power Supply Requirements Supply Voltage I 4.75 5.25 V Supply Current 1 Vp-p Output IV 56 mA

2 Vp-p Output I 100 mA

Power Dissipation 1 Vp-p Output IV 280 mW

2 Vp-p Output I 485 500 mW

1Full-scale settling time to within ±2% of full scale. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at T A=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at T A = 25 °C. Parameter is guaranteed over specified temperature range. TEST LEVEL I II III IV V VI

Figure 4 shows a typical interface circuit of the SPT5230 in normal circuit operation. SUPPLY AND GROUND CONSIDERATIONS Fairchild suggests that all power supply pins (AVDD ) be tied together and decoupled using a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. EXTERNAL REFERENCE VOLTAGE (V REF1 ) A +3 V (±10%) voltage reference should be externally gener- ated for the VREF1 pin using the simple voltage divider shown in figure 4. Connect a 0.1 µF bypass capacitor between VREF1 and AVSS as close to the pin as possible. EXTERNAL REFERENCE VOLTAGE (V REF2 ) VREF2 needs to be externally connected to AVDD through a 1.2 kΩ (5%) resistor. Connect a 0.1 µF bypass capacitor between VREF2 and AVSS as close to the pin as possible. CONTROL VOLTAGE DECOUPLING (V CS1 ) This is a decoupling pin for the control voltage internal circuitry. An external 0.1 µF capacitor should be connected between VCS1 and AVSS as close to the pin as possible. FULL-SCALE ADJUST CONTROL (V CS2 ) VCS2 is an external control voltage input that controls the peak-to-peak full scale output voltage. This is the only exter- nal voltage that has direct control over the SPT5230 output voltage. The voltage output swings between AV DD (+5 V) and a value controlled by VCS2 . Assuming that an output load resistor of 75 Ω is connected between the output and AVDD , figure 2 shows what the output voltage will be for the digital inputs all equal to logic 0, as VCS2 is varied from 2 V to 4 V. Figure 3 shows the peak-to-peak output voltage versus V CS2 and table I shows an example in which VCS2 is equal to 2.1 V. CURRENT OUTPUTS Each red, green and blue current output should have a load resistor connected to AVDD . The resistors are typically 75Ω and should be kept in the 72 Ω to 85 Ω range. The outputs should drive a high impedance load such as a voltage follower. OUTPUT LEVEL SHIFTING CIRCUIT The SPT5230 voltage output will swing from +3.0 V to +4.99 V for V CS2 = 2.1 V as shown in table I. If level shifting of the output is desired, Fairchild recommends use of the circuit shown in figure 5. The desired –FS voltage is fed into the collector of the emitter to achieve the desired level shift. (Note the phase inversion that will occur due to the common emitter.) Choose any appropriate video op amp with ad- equate power supply head room. Table I – Binary Codes 1 LSB = 1.953 mV, V CS2 ≈ 2.1 V Digital Input Analog Step A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Out (V) (MSB) (LSB) 0 0000000000 3.000000 1 0000000001 3.001953 2 0000000010 3.003906 3 0000000011 3.005859 . . . . . . . . . 1022 1111111110 4.996094 1023 1111111111 4.998047

A B C D E F G H I J INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.507 0.523 13.0 13.4 B 0.386 0.394 9.9 10.1 C 0.507 0.523 13.0 13.4 D 0.386 0.394 9.9 10.1 E 0.070 0.090 1.80 2.30 F 0.025 typ 0.65 typ G 0.008 0.016 0.2 0.4 H 0.062 typ 1.6 typ I 0.004 0.008 0.1 0.2 J 0.023 0.039 0.6 1.0

PIN ASSIGNMENTS PIN FUNCTIONS Name Function R OUT Red Analog Current Output G OUT Green Analog Current Output BOUT Blue Analog Current Output R0–R9 Red Data Inputs G0–G9 Green Data Inputs B0–B9 Blue Data Inputs CLKR Red Clock Input CLKG Green Clock Input CLKB Blue Clock Input VREF1 Voltage Reference Input 1 (A 0.1 µF ceramic capacitor should be used.) VREF2 Voltage Reference Input 2 (A 0.1 µF ceramic capacitor should be used.) VCS1 Control Voltage Decoupling (A 0.1 µF ceramic capacitor should be used.) VCS2 Full-Scale Adjust Control Voltage (A 0.1 µF ceramic capacitor should be used.) AV SS Analog Ground AV DD Analog Power Supply Voltage N/C No Connection QFP 27282930313233343536373839 13121110987654321 G8G9 (MSB)N/CRØ (LSB)R1R2R3R4R5R6R7R8R9 (MSB) B9 (MSB) AV SS N/C GØ (LSB) B6B5B4B3B2B1 BØ (LSB) CLKBCLKGCLKRAV SS AV DD VREF2 VCS2 VCS1 AV DD VREF1 AV SS BOUT AV SS G OUT AV SS R OUT AV SS AV DD AV DD

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE SPT5230SCT 0 to +70 °C 52L QFP LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation