SPT5220

SPT5220 CADEKA | Alldatasheet

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10-BIT, 80 MWPS VIDEO DAC FEATURES APPLICATIONS + 80 MWPS Pipelined Operation . High Resolution Color Graphics + +5 V CMOS Monolithic Construction + Medical Electronics: CAT, PET, MR Imaging Displays + +0.4 LSB Differential Linearity Error + CADICAE Workstations + +0.6 LSB Integral Linearity Error + General Purpose High-Speed D/A Conversion + TTL-Compatible Inputs + Direct Digital Synthesis (DDS) + RS-343A/RS-170 Compatible Outputs + Digital Radio Transmitters/Modulators + Binary or Two's Complement Input Data Format + High Definition Television (HDTV) + Low Power Dissipation of 260 mW + Internal/External Voltage Reference GENERAL DESCRIPTION The SPT5220 is a monolithic 10-bit, 80 MWPS CMOS D/A ~—_—RS170-compatible video outputs (capable of driving a singly- converter for high-resolution color graphics and video terminated 75 Q load) without the need for external buffers. system applications. The device operates from a single The datalatches minimize the data time skew and reduce the +5 V power supply and all digital inputs are TTL/CMOS _ glitches that can adversely affect many applications. compatible. The device is available in a 28-lead plastic DIP package over The SPT5220 generates RS343A-compatible video outputs —_ the commercial temperature range. (capable of driving a doubly-terminated 75 Q load) and BLOCK DIAGRAM Syne Oy Blank = Ae) pe | 36 DB-D9 > Digital First Second DAC S lour | Input | Latch LJ a | Latch Buffer vere J | @ Comp Clock et o o 0 S d 6 3 PVpp PVss Ves AVpp AVss VREF Rset

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1,2,3 BV Ginvneosseeseencersennsensensssovestassassnassuvesrsersenses SOTO FOV: DV 9 vresssesseeseeersesssecsseeseesessseessessseesseeseess 0.5 tO +7.0V Temperature Notes: 1. Operation at any absolute maximum rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. 2. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is not implied. 3. Applied voltage must be current limited to the specified range. ELECTRICAL SPECIFICATIONS4 Ta=Tmin to Tmax, AVoD=DVpp=VeB=t5.0 V, AVss=DVss=0.0 V, VREF=1.235 V, RsET=165 , unless otherwise specified. TEST TEST SPT5220 PARAMETERS CONDITIONS LEVEL MIN TYP MAX | UNITS DC CHARACTERISTICS Resolution 10 Bits Differential Linearity Error vi 40.4 +1.0 LSB Integral Linearity Error vi 40.6 +1.0 LSB Gray Scale Error vi +5.0 % Gray Monotonicity vi Guaranteed Digital Input High Current Vin=2.4V vi TO [pA Digital Input Low Current Vin=0.4 V Vi -1.0 HA Digitial Input Capacitance fin=1 MHz IV 20 40 pF Analog Outputs Gray Scale Current Vi 22 mA Output Current Bright to White vi 1.0 1.90 3.0 mA White to Black vi 18.1 19.05 20.0 mA Black to Blank vi 0.5 1.43 25 mA Blank to Syne vi 6.5 7.62 8.5 mA Sync Level vi 0 5 50 | pA LSB Size Vv 18.62 pA Output Compliance vi -1.0 +15 | V Output Impedence Vv 11 kQ Output Capacitance fin=1 MHz Vv 14 30 pF Internal Reference Voltage es 1.16 1.235 1.36 | V Power Supply Rejection Ratio fin=1 kHz, comp=0.1 pF ee dB Digital Input Voltage High Vi 20 Voo+0.3 | V Low vi Vss-0.3 08 | V Data Input Setup Time IV 2.0 ns Data Input Hold Time IV 2.0 ns Clock Cycle Time IV 12.5 ns Clock Pulse Width High IV 5 ns Clock Pulse Width Low IV 5 ns Note: 4. To avoid power latch-up, drive all supply pins (AVpp, DVpp, and Vgp) from the same source. SPT5220 2 12/30/98

Ta=Tmin to Tmax, AVoD=DVpp=Vep=+5.0 V, AVss=DVss=0.0 V, VreF=1.235 V, RsET=165 Q, unless otherwise specified. TEST TEST SPT5220 PARAMETERS CONDITIONS LEVEL MIN TYP MAX | UNITS AC CHARACTERISTICS Clock Rate Po Ts Analog Output Delay Vv 7 ns Analog Output Rise Time Vv 4 ns Analog Output Fall Time Vv 4 ns Analog Output Settling Time5 to+1 LSB IV 100 150 ns to+2LSB IV 70 100 ns Clock and Data FeedthroughS Vv -34 dB Glitch Impulse5 IV 30 pv-sec Differential Gain Error Vv 0.8 % Differential Phase Error Vv 0.9 Degree Note: 5. Clock and data feedthrough are functions of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 kQ resistor to ground driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough. 6. At fax, IDD (typ) at AVpp=DVpp=5.25 V, CLK=0 V to 3 V (80 MWPS), NC2=High, Data (D-D9)=0 V to 3 V (40 MWPS), Inverse=Sync=Blank=Bright=Low. TEST LEVEL CODES TESTLEVEL TEST PROCEDURE All electrical characteristics are subject to the | 100% production tested at the specified temperature. following conditions: ii} 100% production tested at T,=+25 °C, and sample All parameters having min/max specifications tested at the specified temperatures. are guaranteed. The Test Level column indi- Ml QA sample tested only at the specified temperatures. cates the specific device testing actually per- IV Parameter is guaranteed (but not tested) by design formed during production and Quality Assur- and characterization data. ance inspection. Any blank section in the data Vv Parameter is a typical value for information purposes column indicates that the specification is not only. tested at the specified condition. - 7 PS vi 100% production tested at T, = 25 °C. Parameter is guaranteed over specified temperature range. SPT5220 3 12/30/98

CIRCUIT DESCRIPTION AND OPERATION CLOCK INPUT The SPT5220 contains a 10-bit DAC, input buffers and CLK is the device clock input and is typically the pixel clock rate latches, internally or externally generated voltage refer- of the system. Itis TTL compatible. The digital data DO-D9 and ence and complete video controls. The followingdescribes _ alll video controls (SYNC, BLANK, BRIGHT) are all latched on the main operation of the device and outlines several __ the rising edge of CLK. See figure 1. considerations that should be noted to achieve the best performance. Figure 1: Timing Waveform7:8:9 toL—K—— >] tpwH>/<tpwi>| ~ | De~p9_ Nt Data |X Na |) <—'s tH tp tser Pipeline Dela Note: 7. Output delay (t,) is measured from the 50% point of the rising edge of CLK to the full scale transition. 8. Settling time (t,,,) is measured from the 50% point of full scale transition to the output remaining within +1, +2 LSB. 9. Output rise/fall time (t,, t,) is measured between the 10% and 90% points of full scale transition. DIGITAL INPUTS AND VIDEO CONTROLS A logic 1 on the SYNC input generates the sync level. A logic 1 onthe BLANK input generates the pedestal level. BRIGHT is the All ten bits of data (DO-D9, DO is the LSB) are latched into bright signal input. These inputs are pipelined to maintain the device on the rising edge ofeach clock cycle. There are synchronization with the digital input data. These video controls also three video control inputs to generate composite produce the output levels needed to be compatible with video video outputs. They are SYNC, BLANK and BRIGHT. — systemstandards. Table | shows the video control effects on the analog output. Table | - Video Output Truth Table a SS a SS a Black Level a Wie Level A a Enhanced We Leva SPT5220 4 12/30/98

There are two different input data formats available: binary __ either normal or inverted. The video control truth table for and two’s complement. In addition, these formats can be __ these options are given in table Il. Table Il - Video Control Truth Table‘? INVERSE DATA (D9-D0) OUTPUT (I/O) DESCRIPTION 1 0000000000 Black Level Binary

1419411111 White Level

1 1 0000000000 White Level Inverse Binary

4111111111 Black Level

1000000000 Black Level Two's Complement

0111141111 White Level

1 1000000000 White Level Inverse Two's Complement

0114111111 Black Level

Note: 11. Doubly-terminated load of 75 Q, Sync=Blank=Bright=Low REFERENCE The SPT5220 can be used with either an internal or external © bypass capacitor. The COMP capacitor should be kept as voltage reference. The typical interface circuits areshownin _ close as possible to the device to keep the lead lengths to an figures 2 and 3. When using an external reference (figure 2), absolute minimum. the input voltage supplied must be 1.235 volt (typ). When using the internal reference (figure 3), the Var pin should _Rset is the full scale adjust control. A resistor (Rset) con- not drive any external circuitry except for the decoupling nected between this pin and ground controls the magnitude capacitor. A bypass capacitor of 0.1 uF with the shortest of the full-scale video signal. The value for Rsetis determined possible lead lengths should be connected between Veer __ by the relationship: and Vgg. With either configuration, the COMP pin (compen- Rset=4.1 x Veeg/loyt- sation capacitor) should be connected to Vpp through the _—The electrical specifications are given with an Rset value of 165 ohms. Figure 2 - Typical Interface Circuit (External Reference) ui [I O Yop le at cal, c4 | cs _ R2 Diving Logie Component Description i syne 1 Yop Ves AVoo C1, C2 10 wF Capacitor t i {Blank >—+ VREF C3 - C6 0.1 uF Ceramic i ‘ i | re ee To Video G {Bright louT e) Capacitor } po~po comp c f assyasey~ | SPT5220 L1,L2,L3 Ferrite Bead | eco RI 75 Q 1% Metal {inverse >—+ Raat ce Film Resistor | ouK>—+t DVgg AVsg ae z4 R2 1 kQ 5% Resistor “TCrR Rf Rset 165 Q 1% Film Resistor . 12 (180 Q//2 kQ) °Vop ft — O Veg Z, 1.235 V Voltage Reference V (ICL8069CCSQ2) SPT5220 5 12/30/98

Figure 3 - Typical Interface Circuit (Internal Reference) uy ipti —— © Vpo Component Description ct * ¢3 cal, C1, C2 10 uF Capacitor ca Tes C3 -C6 0.1 HF Ceramic Capacitor Fae L1,L2,L3 Ferrite Bead |g i Vpn View AVoD i syne. i y R1 75 Q 1% Metal | Blank ‘ REF Film Resistor | Bright + lout a © To Video po-pso—t comp| | Connector Rset 165 Q 1% Film | se) ese) i SPT5220 Resistor (180 Q//2 kQ) 1 tnverse>—t Reet ; oK>— DVsg AVsg cd | See | Do la bo) 4 — O Veg V Note 12: AVpp, DVpp and Vg must be supplied from the same source (Analog +5 V) to prevent a latch-up condition due to power supply sequencing. Note 13: For applications requiring minimal signal distortion, use of the external reference is recommended. ANALOG OUTPUT The SPT5220 generates RS-343A compatible video outputs driving a singly-terminated 75 ohm load without the need for capable of directly driving a doubly-terminated 75 ohm load, external buffers. Figure 4 shows the video waveforms asso- and RS-170 compatible video outputs capable of directly ciated with the output driving the doubly-terminated 75 ohm load. Figure 4 - Composite Video Output Wave Form“ Bright [30.00] 7.125] 10 1RE White | 28.10] 1.054

100 IRE

Black | 9.05 | 0.340 Blank | 7.62 |0.286| ”°'RE

40 IRE

Sync_| 0.00 | 0.00 SPT5220 6 12/30/98

PC BOARD CONSIDERATIONS DIGITAL SIGNAL INTERCONNECT LAYOUT CONSIDERATIONS The PCBline between the TTL driver (that drives the SPT5220) and the input to the SPT5220 will have a low impedance To minimize noise on the powerlines and groundlines, shield Source and be terminated with a high impedance. It behaves and decouple the digital inputs. Keep the trace length be- _like a low impedance transmission line so signal transitions tween groups of Vpp (AVpp; DVpp) and Vgg (AV gg, DV sg) willbe reflected from the high impedance input ofthe SPT5220. as short as possible to minimize inductive ringing. To reduce ringing caused by transmission line mismatch, shorten the line length or terminate the line. Both serial and SUPPLY AND GROUND CONSIDERATIONS parallel termination methods will work, but serial is preferred. Serial termination is achieved by installing a resistor of Use a 0.1 yl ceramic capacitor in parallel with a 10 uF approximately 50 © between the TTL driver output and the tantalum capacitor for decoupling between the power line | SPT5220 digital input. and the ground line. The digital power plane (DVpp) and the analog power plane (AVpp) are connected through a ferrite © ANALOG SIGNAL INTERCONNECT ground plane (AVgg) are also connected through a ferrite To minimize noise pickup and reflections due to impedance bead. (See figures 3 and 4). Locate these ferrite beads within mismatch, locate the SPT5220 as closely as possible to the three inches of the SPT5220. output connector. The line between the DAC output and the monitor input should be regarded as a transmission line since itcan cause problems in transmission line mismatch. Use the double-termination method to avoid these problems. By using the double terminated method, the transmission lines are matched, providing an ideal, nonreflective system. 28-LEAD PLASTIC DIP (PDIP) PACKAGE OUTLINE [___ INCHES [MILLIMETERS] —| K [srmsou am af a [a [Poses tye [508 ye | RADAR AAARA RANA [me] “one —oaze [an | 0 | 28 a a YT eC 1 [ « [7 fo.cotye [| 2.04 ye | peeeeee J eee T + A —+ lla L a ; ike > fe SPT5220 7 4280/08

PIN ASSIGNMENTS PIN FUNCTIONS Name Function Noo L1]° |28] comp AVpp Analog Power we [2] Rser NIC No Connection Vi Substrate Power (Connected to AV; Vee L3| [26] Veer BB ( pp) AVss Analog Ground Avon L4] [25] Nac D9 - DO Digital Inputs (D9=MSB, DO=LSB) AVss [5] lout SYNC Sync Signal Input (Logic 1 Generates Level) (uss) pe [ 6 | [23] AVgs BLANK Blank Signal Input (Logic 1 Generates Level) bs PDIP. INVERSE = IGHT corn Input DD Z o7 La] CLK DVss Digital Ground vs [9| |20] DVgs CLK Clock input (TTL-Compatible) DS [ 19] DVpp INVERSE Inverse Signal Input pa eRicHY lout nalog Current Output : N2C Two's Complement Signal Input (Active Low) bee BLADE. VRer Voltage Reference (Externally Driven) v2 [13 | SYNC = Full-Scale Adjust Control D1 D® (LSB) COMP Compensation Capacitor

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT5220SCN 0 to +70 °C 28L Plastic DIP For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado . are EX CADEKA T; 877.663.5452 (toll free) Amplify the Human Experience CADEKA, the CADEKA logo design, Comincay, and the Comnear fogo design are trademarks of registered trademarks of CADEKA Miroencunts LLC. All ather brand and product names may be trademarks of thei respect? companies, CADEKA.csenes the night to make changes to any products and services herein at any Ue without notice. CADEKA does nat assume any responsibilty or habilty arising out ofthe application cr use of any product or service descnbed herein, except as expressly agreed to vzuting by CADEKA; nor does the purchase, lease, or use ofa product or service From CADEKA convey a license under any patent rights, copynghts, trademark rights, or any other of the intellectual property nights of CADEKA or ofthrd parties Copyright 12007-2009 by CADEKA Mirociruts LLC. All ights reserved SPT5220 8 12/80/98