SPT1175ACN

SPT1175 CADEKA | Alldatasheet

Document overview

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Technical content

8-BIT, 20 MSPS CMOS A/D CONVERTER

FEATURES

• 20 MSPS Maximum Conversion Rate
• Internal Sample-and-Hold Function
• 90 mW Power Dissipation
• Internal Voltage Reference
• Single +5.0 V Power Supply
• Three-State TTL-Outputs
• CMOS Compatible Clock

APPLICATIONS

• Video Digitizing
• Image Scanners
• Personal Computer Video
• Medical Ultrasound
• Multimedia
• Digital Television Data Latches and 3-State Output Buffer Error Correction Circuit Latch Coarse Sampling Amplifier Reference Matrix Timing Generator LatchAnalog Mux Fine Sampling Amplifier Fine Sampling Amplifier Encoder Encoder DGNDDV DDVRBSVRB VIN VRT VRT S AGND AV D DV DD AGND DØ (LSB) D7 (MSB) CLK OE GENERAL DESCRIPTION The SPT1175 is a CMOS two-step A/D converter capable of digitizing full scale analog input signals into 8-bit digital words at a sample rate of 20 MSPS. For most applications, no external sample-and-hold or video driving amplifiers are required due to the device's narrow aperture time, wide bandwidth, and low input ca- pacitance. The SPT1175 operates from a single +5.0 V power supply and has an internal voltage reference which eliminates the need for external reference circuitry. All digital inputs are CMOS compatible and the tri-state outputs are TTL-compat- ible. The SPT1175 is ideal for most video and image pro- cessing applications that require low power dissipation and low cost. The SPT1175 is available in 24-lead plastic SOIC, plastic DIP, and PLCC packages over the commercial tem- perature range (0 to +70 °C). It is also available in die form. BLOCK DIAGRAM

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Resolution 8 Bits DC Accuracy (+25 °C) Integral Nonlinearity I ±0.8 ±1.2 LSB Differential Nonlinearity I ±0.6 ±1.0 LSB No Missing Codes I Guaranteed Analog Input Input Voltage Range I VRB VRT V Input Bias Current I ±5.0 µA Input Resistance VI 100 200 kΩ Input Capacitance V 15 pF Input Bandwidth V 12 MHz Reference Input Reference Ladder Resistance I 200 300 400 Ω Reference Current I 5.0 6.7 10.0 mA Reference Input Voltage VRB IV 0 0.6 - V VRT IV - 2.6 2.8 V Internal Bias VRB I 0.55 0.60 0.65 V VRT -VRB I 1.9 2.0 2.1 V Short VRT and VRTS Short VRB and VRBS Offset Voltage Error Top I -18 -25 -68 mV Bottom I 0 10 40 mV Timing Characteristics Maximum Conversion Rate 1 MHz Input Sine Wave I 20 30 MSPS Output Data Delay (td) IV 18 30 ns Output Data Delay (High Z) IV 100 ns (Tdish, Tdisl) Data Valid Time Tri-State Circuit IV 100 ns (Teneh, Tenel) Sampling Time Offset IV 5 10 ns ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) (1) 25 °C Supply Voltages Input Voltages Temperature Notes: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. 2. 100 pF discharged through a 1.5 kΩ resistor (human body model). NOTE: It is strongly recommended that all of the supply pins (AVDD , DVDD ) be powered from the same source. 2 6/24/97

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS Dynamic Performance Signal-To-Noise Ratio fS= 20 MSPS fIN=1.0 MHz I 44 46 dB fIN=3.58 MHz I 43 45 dB fIN=10 MHz V 39 dB Spurious Free Dynamic Range fS= 20 MSPS fIN=1.0 MHz I 44 47 dB fIN=3.58 MHz I 41 44 dB fIN=10 MHz V 33 dB Differential Phase NTSC 20 IRE Mod Ramp V 0.7 Degrees Differential Gain fS = 14.3 MSPS V 1.0 % Digital Inputs Input Current, Logic High VDD = 5.25 V, VIH = VDD I 1.0 µA Input Current, Logic Low VDD = 5.25 V, VIL = DGND I 1.0 µA Pulse Width High (CLK) IV 15 ns Pulse Width Low (CLK) IV 15 ns Voltage, Logic High I 4.0 V Voltage, Logic Low I 1.0 V Digital Outputs Output Current, High VDD = 4.75 V IV -1.1 mA Output Current, Low VDD = 4.75 V IV 3.5 mA Output Current, High Z VDD = 5.25 V, OE = VDD IV 16 µA Voltage High I 4.0 V Voltage Low I 0.4 V Power Supply Requirements Analog Supply Voltage (AVDD ) IV +4.75 +5.0 +5.25 V Digital Supply Voltage (DVDD ) IV +4.75 +5.0 +5.25 V Supply Voltage Difference (AVDD -DVDD ) IV -0.1 0.0 0.1 V Supply Current fS=20 MSPS I 18 27 m A Power Dissipation I 90 135 mW TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. TEST LEVEL I II III IV V VI TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guar- anteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. 3 6/24/97

The SPT1175 is an 8-bit analog-to-digital converter which uses a two-step, ping-pong architecture to perform conver- sions up to 20 MSPS. Figure 2 shows the typical interface requirements when using the SPT1175 in normal operation. The following sections describe the function and operation of the device. POWER SUPPLIES AND GROUNDING The SPT1175 operates from a single +5 V power supply. AV DD and DVDD must be supplied from the same source (analog +5 V) to prevent a latch-up condition due to power supply sequencing. Each power supply pin should be by- passed as closely as possible to the device. For optimal performance, both the AGND and DGND should be con- nected to the system's analog ground plane. ANALOG INPUT AND VOLTAGE REFERENCE The SPT1175 input voltage range is VRT >V IN>VRB . Two reference voltages (VRT and VRB ) are required for device operation. These voltages may be generated externally or the SPT1175's internal reference may be used. Inside the SPT1175, reference resistors are placed between AV DD and VRTS and between AGND and VRBS so that VRTS and VRBS generate the 2.6 V and 0.6 V references respec- tively. (See figure 3.) In order to utilize the internal self-bias reference voltage, VRTS is to be shorted with VRT and the VRBS pin is to be shorted to the VRB pin. The self-bias internal reference is not as stable over temperature and supply variations as externally generated reference voltages but will perform well in many commercial video applications. Figure 3 - Reference Circuit Diagram SPT1175 2.6 V 0.6 V VRTS VRT VRB VRBS AGND 0 V AV DD 5.0V DIGITAL INPUTS AND OUTPUTS The analog input is sampled and tracked on the first 'H' cycle of the external clock and is held from the falling edge of CLK. The output remains valid (output hold time), and the new data becomes valid (output delay time) after the rising edge of CLK, delayed by 2.5 clock cycles. The clock input and output enable input must be driven at CMOS-compatible levels. EVALUATION BOARD The EB1175 evaluation board is available to aid designers in demonstrating the full performance of the SPT1175. This board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction DAC. An appli- cation note describing the operation of the board is available. Contact the factory for price and delivery. Figure 2 - Typical Interface Circuit R10 DV DD AV DD AV DD VRT S VRT AV DD VIN AGND AGND VRBS VRB DGND CLK DV DD DGND +5 V 10(MSB) 3 (LSB) +5 V -15 +15 C28 C29 U2+ -15 +15 C61C8 10 k 7.5 k C58 -15 VIN 750 R35 750 R36 R37 750

6 R15

U1=Eleantec, EL2030 U2=OP .07 D1=D2=RCA, SK9091 Q1=Q2=2N2222A FR=FairRite, 2743001111 All capacitors are 0.01 µF unless otherwise specified. 3-ST EN Outputs +15 -15 GND 10 + +15 -15 GND ++5 -5 -5 NOTE: AVDD and DVDD must be supplied from the same source (Analog +5 V) to prevent a latch-up condition due to power supply sequencing. 5 6/24/97

A B CD E F G I H A B C D E J F G H K I INCHES MILLIMETERS SYMBOL MIN M A X MIN M A X A 0.130 0.230 3.30 5.84 B 0.115 0.200 2.92 5.08 C 0.014 0.023 0.36 0.58 D 0.045 0.070 1.14 1.78 E .100 typ 2.54 0.00 F 0.008 0.015 0.20 0.38 G 0.115 0.195 2.92 4.95 H .30 typ 7.62 0.00 I 0.240 0.310 6.10 7.87 J 1.180 1.285 29.97 32.64 K .005 typ 0.13 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.587 0.606 14.90 15.40 B C .050 typ 1.27 typ D 0.014 0.022 0.35 0.55 E 0.006 0.012 0.15 0.30 F 0.067 0.089 1.70 2.25 G 0.012 0.028 0.30 0.70 H 0.295 0.327 7.50 8.30 I 0.205 0.220 5.20 5.60 6 6/24/97

A B Pin 1 C D E F G H TO P VIEW Pin 1 BO TTOM VIEW I INCHES MILLIMETERS SYMBOL MIN M A X MIN M A X A 0.450 0.456 11.43 11.58 B 0.485 0.495 12.32 12.57 C4 5° 45° D 0.165 0.175 4.19 4.45 E 0.010 0.25 F 0.022 typ .56 typ 0.00 G 0.18 typ 4.57 typ 0.00 H 0.05 typ 1.27 typ 0.00 I 0.039 0.430 0.99 10.92 7 6/24/97

25 AGND

21 AV DD

19 VRT S11D6

DGNDN/CDGNDDØ OE AGND22

23 VIN

DØ (LSB) D7 (MSB) DV DD CLK DGND VRB VRBS AGND AGND VIN AV DD VRT VRTS AV DD AV DD DV DD PIN ASSIGNMENTS DIP and SOIC PLCC PIN FUNCTIONS Name Function OE Tri-State Output Enable Tri-State WhenO E = DVDD , Enable When O E = DGND DGND Digital Ground D0 Digital Output Data (LSB) D1-6 Digital Output Data D7 Digital Output Data (MSB) DV DD Digital Supply CLK CMOS Digital Clock Input AV DD Analog Supply VRTS Internal Self-Biased Reference Top Shorted with VRT (pin 17). Generates 2.6 V. VRT Reference Resistor Top Side VIN Analog Input AGND Analog Ground VRBS Internal Self-Biased Reference Bottom Shorted with VRB (pin 23). Generates 0.6 V. VRB Reference Resistor Bottom Side

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT1175ACN 0 to +70 °C 24L Plastic Dip SPT1175ACP 0 to +70 °C 28L PLCC SPT1175ACS 0 to +70 °C 24L SOIC SPT1175ACU +25 °C Die* *See the die specification for guaranteed electrical performance. 8 6/24/97