SPT1018AIN

SPT1018 CADEKA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 11

Technical content

8-BIT, HIGH SPEED D/A CONVER TER Sync, Blank, Bright, Ref - High D0 - D3 D4 - D7 (MSBs)

4 To 15

FEATURES

• 275 MWPS Conversion Rate - Version A
• 165 MWPS Conversion Rate - Version B
• Compatible with TDC1018 and HDAC10180 with Improved Performance
• RS-343-A Compatible
• Complete Video Controls: Sync, Blank, Bright and Reference White (Force High)
• 10KH, 100K ECL Compatible
• Single Power Supply
• Registered Data and Video Controls
• Differential Current Outputs
• ESD Protected Data and Control Inputs

APPLICATIONS

• High Resolution Color or Monochrome Raster Graphics Displays
• Medical Electronics: CAT, PET, MR Imaging Displays
• CAD/CAE Workstations
• Solids Modeling
• General Purpose High-Speed D/A Conversion
• Digital Synthesizers
• Automated Test Equipment
• Digital Transmitters/Modulators GENERAL DESCRIPTION The SPT1018 is a monolithic 8-bit digital-to-analog converter capable of accepting video data at a 165 or 275 MWPS rate. Complete with video controls (Sync, Blank, Reference White [Force High], Bright), the SPT1018 directly drives doubly- terminated 50 or 75 ohm loads to standard composite video levels. The standard set-up level is 7.5 IRE. The SPT1018 is pin-compatible with the HDAC10180 and the TDC1018, with improved performance. The SPT1018 contains data and control input registers, video control logic, reference buffer, and current switches. The SPT1018 is available in a 24-lead PDIP package in the industrial temperature range. Contact the factory for military temperature and /883 versions. BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATING (Beyond which damage may occur) 1 Supply Voltages Input Voltages (measured to VCC ) Temperature Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS VCC =ground, VEE = -5.2 V ±0.3 V, TA =TMIN to TMAX , CC = 0 pF, ISet = 1.105 mA, unless otherwise specified. TEST TEST PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC ELECTRICAL CHARACTERISTICS Integral Linearity Error 1.0 mA<I Set<1.3 mA VI -.37 +.37 % Full Scale -.95 +.95 LSB Differential Linearity Error 1.0 mA<ISet<1.3 mA VI -0.2 +0.2 % Full Scale -0.5 +0.5 LSB Gain Error VI -6.5 +6.5 % Full Scale Gain Error Tempco V 150 PPM/ °C Input Capacitance, REF+, REF- V 5 pF Compliance Voltage, +Output VI -1.2 1.5 V Compliance Voltage, -Output VI -1.2 1.5 V Equivalent Output Resistance VI 20 kΩ Output Capacitance V 12 pF Maximum Current, + Output IV 45 mA Maximum Current, - Output IV 45 mA Output Offset Current VI 0.05 0.5 LSB Input Voltage, Logic HIGH VI -1.0 V Input Voltage, Logic LOW VI -1.5 V Convert Voltage, IV -0.5 -2.5 V Common Mode Range (V ICM ) Convert Voltage, Differential (VIDF) IV 0.4 1.2 V Input Current, Logic LOW, VI 35 120 µA Data and Controls Input Current, Logic HIGH, VI 40 120 µA Data and Controls Input Current, Convert VI 2 60 µA 2 5/14/97

VCC =ground, VEE = -5.2 V ±0.3 V, TA =TMIN to TMAX , CC = 0 pF, ISet = 1.105 mA, unless otherwise specified. TEST PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS DC ELECTRICAL CHARACTERISTICS Input Capacitance, V 3.0 pF Data and Controls Power Supply Sensitivity VI -120 20 +120 µA/V Supply Current VI 155 220 mA DYNAMIC CHARACTERISTICS ( RL = 37.5 ohms, CL = 5 pF, TA = 25 °C, ISet = 1.105 mA) Maximum Conversion Rate B Grade IV 165 MWPS A Grade IV 275 MWPS Rise Time 10% to 90% G.S. IV 1.6 ns TA = TMIN to TMAX IV 2.0 ns Rise Time 10% to 90% G.S. V 1.0 ns R L = 25 ohms Current Settling Time, Clocked ModeTo 0.2% G.S. V 7.0 ns Current Settling Time, Clocked ModeTo 0.8% G.S. V 5.5 ns Current Settling Time, Clocked ModeTo 0.2% G.S. V 4.5 ns tSI R L = 25 Ω Clock to Output Delay, Clocked Mode IV 2.2 4.0 ns tDSC TA = TMIN to TMAX IV 4.5 ns Data to Output Delay, IV 3.2 6.0 ns Transparent Mode tDST TA = TMIN to TMAX IV 6.0 ns Convert Pulse Width, ( Low or High)B Grade IV 3.0 ns tPWL , tPWH A Grade IV 1.8 ns Glitch Energy Area = 1/2 VT V 4 pV-s Reference Bandwidth, -3 dB V 1.0 MHz Set-up Time, Data and Controls IV 1.0 ns tS TA = TMIN to TMAX IV 1.0 ns Hold Time, Data and Controls IV 0.5 ns tH TA = TMIN to TMAX IV 0.5 ns Slew Rate 20% to 80% G.S. IV 390 V/µS TA = TMIN to TMAX IV 325 V/µS Clock Feedthrough IV -48 dB TA = TMIN to TMAX IV -48 dB TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/ max specifications are guaranteed. The Test Level column indicates the specific device test- ing actually performed during production and Quality Assurance inspection. Any blank sec- tion in the data column indicates that the speci- fication is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. 3 5/14/97

Figure 1 - Functional Diagram

APPLICATION INFORMATION

The SPT1018 is a high speed video digital-to-analog con- verter capable of conversion rates of up to 275 MWPS. This makes the device suitable for driving 1500 X 1800 pixel displays at 70 to 90 Hz update rates. The SPT1018 is separated into different conversion rate categories as shown in table I. The SPT1018 has 10 KH and 100K ECL logic level compat- ible video controls and data inputs. The complementary analog output currents produced by the devices are propor- tional to the product of the digital control and data inputs in conjunction with the analog reference current. The SPT1018 is segmented so that the four MSBs of the input data are separated into a parallel thermometer code. From here, fifteen identical current sinks are driven to fabricate sixteen coarse output levels. The remaining four LSBs drive four binary weighted current switches. The MSB currents are then summed with the LSBs, which provide a one-sixteenth of full scale contribution, to provide the 256 distinct analog output levels. The video control inputs drive weighted current sinks that are added to the output current to produce composite video output levels. These controls, Sync, Blank, Reference White (Force High), and Bright are needed in video applications. Another feature that similar video D/A converters do not have is the Feedthrough Control. This pin allows registered or unregistered operation of the video control and data inputs. In the registered mode, the composite functions are latched to the pixel data to prevent screen-edge distortions generally found on unregistered video DACs. Decoding Logic Data Registers Current Sources And Switches Current Source Biasing Amp Out + Out - Composite Video Controls Feedthrough D0 - D7 CONV CONV Ref+VEE VCC Ref- Table I - The SPT1018 Family and Speed Designations PART NUMBER UPDATE COMMENTS SPT1018A 275 MWPS Suitable for 1200 X 1500 to 1500 X 1800 displays at 60 to 90 Hz update rate. SPT1018B 165 MWPS Suitable for 1024 X 1280 to 1200 X 1500 displays at 60 to 90 Hz update rate. 4 5/14/97

750 Ω OutputCurrentSwitches 500 Ω ISet ISet* 1 kΩ – 5.2 V .01 µF LM113/313 FT FH Blank BR T Sync D0 (LSB) D7 (MSB) CONV CONV 2 kΩ Register Video Monitor Out+ R 3 50/75 Ω R 4 50/75 Ω 50/75 Ω CO AX NO TES: Out- Ref+ Ref- V- = -1.2 V (typical) for LM113. V+ = -1.2 V R L = R3 / / R4 K = 15.8069 K1 = 1.7617 K2 = 10.0392 FB = Ferrite bead, Fair-rite P/N 217430011 or equivalent. = ECL Terminationx ISet = V+ αT(R1+R 2) VSync = (K x ISet x RL) + (K2 x ISet x RL) All reference resistors 1/8 W 1% metal film pow er supply decoupling 50 V ceramic disc. 255-Digital Input CodeVOut- =  255 x ISet R L +[]KI x ISet x RL (Bright) K = VCC = AGND See figure 8 for detail on Ref Buffer. VEEVCC COMP -5.2 V .01 µF 10 µF FB 10. 11. 10. = DGND (digital input drivers). Figure 2 - Typical Interface Circuit TYPICAL INTERFACE CIRCUIT GENERAL A typical interface circuit using the SPT1018 in a color raster application is shown in figure 2. The SPT1018 requires few external components and is extremely easy to use. The very high operating speeds of the SPT1018 require good circuit layout, decoupling of supplies, and proper design of trans- mission lines. The following considerations should be noted to achieve best performance. INPUT CONSIDERATIONS Video input data and controls may be directly connected to the SPT1018. Note that all ECL inputs are terminated as closely to the device as possible to reduce ringing, crosstalk and reflections. A convenient and commonly used microstrip impedance is about 130 ohms, which is easily terminated using a 330 ohm resistor to VEE and a 220 ohm resistor to Ground. This arrangement gives a Thevenin equivalent ter- mination of 130 ohms to -2 volts without the need for a -2 volt supply. Standard SIP (Single Inline Package) 220/330 resistor networks are available for this purpose. It is recom- mended that stripline or microstrip techniques be used for all ECL interface. Printed circuit wiring of known impedance over a solid ground plane is recommended. OUTPUT CONSIDERATIONS The analog outputs are designed to directly drive a dual 50 or 75 ohm load transmission system as shown. The source impedances of the SPT1018 outputs are high impedance current sinks. The load impedance (RL) must be 25 or 37.5 ohms to attain standard RS-343-A video levels. Any deviation from this impedance will affect the resulting video output levels proportionally. As with the data interface, it is important that the analog transmission lines have matched impedance throughout, including connectors and transitions between printed wiring and coaxial cable. The combination of matched source termination resistor RS and load terminator R L minimizes reflections of both forward and reverse travel- ing waves in the analog transmission system. The return path for analog output current is VCC which is connected to the source termination resistor RS. 5 5/14/97

Table II - Video Control Operation (Output values for set-up = 10 IRE and 75 ohm standard load) Sync Blank Ref White Bright Data Input Out - (mA) Out - (V) Out - (IRE) Description 1 X X X X 28.57 -1.071 -40 Sync Level 0 1 X X X 20.83 -0.781 0 Blank Level 0 0 1 1 X 0.00 0.000 110 Enhanced High Level 0 0 1 0 X 1.95 -0.073 100 Normal High Level The SPT1018 is usually configured in the synchronous mode. In this mode, the controls and data are synchronized to prevent pixel dropout. This reduces screen-edge distor- tions and provides the lowest output noise while maintaining the highest conversion rate. By leaving the Feedthrough (FT) control open (low), each rising edge of the convert (CONV) clock latches decoded data and control values into a D-type internal register. The registered data is then converted into the appropriate analog output by the switched current sinks. When FT is tied high, the control inputs and data are not registered. The analog output asynchronously tracks the input data and video controls. Feedthrough itself is asynchro- nous and usually used as a DC control. The controls and data have to be present at the input pins for a set-up time of ts before, and a hold time of th after, the rising edge of the clock (CONV) in order to be synchronously registered. The set-up and hold times are not important in the asynchronous mode. The minimum pulse widths high (tPWH ) and low (tPWL ) as well as settling time become the limiting factors. (See figure 3.) The video controls produce the output levels needed for horizontal blanking, frame synchronization, etc., to be com- patible with video system standards as described in RS-343-A. Table II shows the video control effects on the analog output. Internal logic governs Blank, Sync, and Force High so that they override the data inputs as needed in video applications. Sync overrides both the data and other controls to produce full negative video output (figure 9). Reference White video level output is provided by Force High, which drives the internal digital data to full scale output or 100 IRE units. Bright gives an additional 10% of full scale value to the output level. This function can be used in graphic displays for highlighting menus, cursors or warning mes- sages. Again, if the devices are used in non-video applica- tions, the video controls can be left open. CONVERT CLOCK For best performance, the clock should be ECL driven, differentially, by utilizing CONV and CONV (figure 4). By driving the clock this way, clock noise and power supply/ output intermodulation will be minimized. The rising edge of the clock synchronizes the data and control inputs to the SPT1018. Since the actual switching threshold of CONV is determined by CONV, the clock can be driven single-ended by connecting a bias voltage to CONV . The switching thresh- old of CONV is set by this bias voltage. ANALOG OUTPUTS The SPT1018 has two analog outputs that are high imped- ance, complementary current sinks. The outputs vary in proportion to the input data, controls and reference current values so that the full scale output can be changed by setting ISet as mentioned earlier. In video applications, the outputs can drive a doubly termi- nated 50 or 75 ohm load to standard video levels. In the standard configuration of figure 5, the output voltage is the product of the output current and load impedance and is between 0 and -1.07 V. The Out- output (figure 9) will provide a video output waveform with the Sync pulse bottom at the -1.07 V level. The Out+ is inverted with Sync up. 7 5/14/97

Figure 4 -CONVert, CONVert Switching Levels VIDF VICM MAX 0.0 V -1.3 V CONV CONV VICM MIN Figure 5A -Standard Load OUT + Video Monitor Inverse Video OUT - R L 75 Ω 75 Ω COAX R S 75 Ω R L 75 Ω 75 Ω COAX R S 75 Ω SPT1018 Figure 5B -Test Load Video Out 0 to -1 Volt OUT + OUT - R L 37.5Ω C L <5 pF TYPICAL RGB GRAPHICS SYSTEM In an RGB graphics system, the color displayed is determined by the combined intensities of the red, green and blue (RGB) D/A converter outputs. A change in gain or offset in any of the RGB outputs will affect the apparent hue displayed on the CRT screen. Thus, it is very important that the outputs of the D/A convert- ers track each other over a wide range of operating condi- tions. Since the D/A output is proportional to the product of the reference and digital input code, a common reference should be used to drive all three D/As in an RGB system to minimize RGB DAC-to-DAC mismatch and improve TC tracking. The SPT1019 contains an internal precision bandgap refer- ence which completely eliminates the need for an external reference. The reference can supply up to 50 µA to an external load, such as two other DAC reference inputs. (See the SPT1019 data sheet). The circuits shown in figure 6 illustrate how a single SPT1019 may be used as a master reference in a system with multiple DACs (such as RGB). The other DACs are simply slaved from the SPT1019’s reference output. The SPT1018s shown are especially well-suited to be slaved to a SPT1019 for a better TC tracking from DAC-to-DAC, since they are essentially SPT1019s without the reference. The SPT1018 is pin-com- patible with the TDC1018, that does not have an internal reference. Although either the TDC1018 or the SPT1018 may be slaved from an SPT1019, the higher performance SPT1018 and the above mentioned DAC-to-DAC TC track- ing is the best choice for new designs. No external reference is required for operation of the SPT1019, as this function is provided internally. The internal reference is a bandgap type and is suitable for operation over extended temperature ranges. The SPT1018 must use an external reference. Figure 6 - Typical RGB Graphics System Ref-Ref+ 750 Ω500 Ω 750 Ω500 Ω R G 1 kΩ Ref-Ref+ B 1 kΩ Ref OutISet R 2 750 Ω R 1 500 Ω IRef ISet ISetISet SPT1019 (Master) SPT1018 (Slave) SPT1018 (Slave) Figure 7 - Burn-In Circuit CONV 1 kΩ 100 Ω 6.5 Ω -1.2 V (Max 1.5 mA) 1 kΩ

24 Pin DIP

All Resistors Are 5% 1/4 W cc Clock = -0.9 to -1.7 V, 100 kHz Ref+ CONV 1 kΩ VCC Clock (Max 60 µA) -5.9 V (Max 200 mA) (Max 50 mA) Out- Ref- VEE Out+ -1.3 V (Max 60 µA) 1 kΩ 6.5 Ω 100 Ω (Max 50 mA) (Max 1.5 mA) 8 5/14/97

Figure 9 - Video Output Waveform for Standard Load Figure 10 -Equivalent Input Circuits - Data, Clock, Controls and Reference IBias VEE Conv Conv IBias VEE VCC Reference Segment Switch Ref- Ref+ IBias IBias 80 kΩ IBias VEE VData and Controls

256 Gray Levels

Normal Low (Black) Sync Video Blank Bright Normal High (White)110 100 7.5 -40 IRE 0 mV -73 mV -728 mV -781 mV -1071 mV ISeg Out+ Out- VEE ISeg Current Sink #1 Current Sink #N Reference Amplifier Ref- Ref+ Reference Current Comp Figure 8 - DAC Output Circuit 9 5/14/97

A B C D E F G H K I J INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A B C D E F G H I J 0.190 0.135 0.022 0.012 0.550 1.255 K 0.125 0.015 0.100 typ 0.055 0.008 0.150 typ 0.600 0.530 1.245 0.070 3.18 0.38 2.54 typ 1.40 0.20 3.81 typ 15.24 13.46 31.62 1.78 4.83 3.43 0.56 1.65 0.30 15.88 13.97 31.88 2.03 0.065 0.625 0.080 10 5/14/97

ORDERING INFORMATION

PART NUMBER DESCRIPTION TEMPERATURE RANGE PACKAGE SPT1018AIN 8-BIT, 275 MWPS DAC -25 to +85 °C 24L PDIP SPT1018BIN 8-BIT, 165 MWPS DAC -25 to +85 °C 24L PDIP PIN ASSIGNMENTS PIN FUNCTIONS Name Function D3 Data Bit 3 D2 Data Bit 2 D1 Data Bit 1 D0 Data Bit 0 (LSB) VEE Negative Supply CONV Convert Clock Input CONV Convert Clock Input Complement FT Register Feedthrough Control VCC Positive Supply FH Data Force High Control Blank Video Blank Input BRT Video Bright Input Sync Video Sync Input Ref- Reference Current - Input Ref+ Reference Current + Input COMP Compensation Input Out- Output Current Negative Out+ Output Current Positive D7 Data Bit 7 (MSB) D6 Data Bit 6 D5 Data Bit 5 D4 Data Bit 4 V Out + Out - VCC Ref- Sync EE VEE CONV FT VCC FH Blank BRT CONV Comp Ref+ PDIP 11 5/14/97