Power Management

SPSB100

STMicroelectronics

Automotive power management IC for highly integrated processors 07-Oct-2024

Manufacturer: STMicroelectronics

Document: 213 Pages / 15Mb

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SPSB100_V01 STM | Alldatasheet

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Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 213

Technical content

Datasheet sections

1 Block diagram and pin description
1.1 Block diagram
1.2 Pin description
2 Maximum ratings
2.1 Operating range
2.1.1 Supply voltage ranges
2.2 Absolute maximum ratings
2.3 ESD robustness
2.4 Temperature ranges and thermal data
3 Functional description
3.1 Supply configurations
3.1.1 System supply configuration
3.1.2 System supply configuration
3.1.3 Digital interface supply: VIO
3.2 Boost controller
3.2.1 Power-up/down and voltage drop behavior
3.3 BUCK converters
3.3.1 BUCK1 converter
3.3.2 BUCK2 converter
3.3.3 BUCK3 converter
3.4 Linear voltage regulators
3.4.1 LDO1
3.4.2 LDO2
3.5 Operating modes
3.5.1 Wake-up from DEEP-SLEEP to ACTIVE state
3.5.2 Wake-up events in ACTIVE mode
3.6 Functional overview - State machine
3.6.1 State machine without fault transitions
3.6.2 State machine focusing on fault transitions
3.6.3 States and transitions description
3.7 Power-up and power-down sequence
3.7.1 Power-up sequence
3.7.2 Power-down sequence
3.8 User's NVM modification procedure
3.8.1 Starts-up with valid NVM data and NVM faults management

Features

AEC-Q100 qualified
2 configurable (6.5 V, 5 V, 3.3 V) BUCK converters and typ peak switching current limit of 3.0 A at 2.4 MHz or 400 kHz peak switching current limit up to 6.0 A at 2.4 MHz, with fine-tuning configurability around 0.98 V (0.95 V to 1.01 V)
Overcurrent detection and limitation for all BUCKs
Integrated soft start on BUCK stages
Boost controller 8-9.5 V and typ peak switching current limit of 4.2 A at 400 kHz, for sustaining low battery condition occurring for a transitory time and deep cranking pulse (external power components can be optionally populated)
One 5 V voltage regulator (120 mA, 2% acc.)
One configurable (5 V or 3.3 V) low drop voltage tracker of all regulators (10 mA, ±10 mV)
One high side driver for contact monitoring (RON = 55 Ω) with open-load and overcurrent diagnosis
Dedicated interrupt pin for failure communication
Device operates in low power mode
Very low quiescent current in DEEP-SLEEP state
MCU reset generator
Configurable window watchdog with extended long open window up to 9 s and enable/disable function through NVM bit
Device contains temperature warning and protection
Thermal clusters
A/D conversion of supply voltages and internal temperature sensors
STMicroelectronics standard serial peripheral interface (32 Bit/ST_SPI) including 4-bit CRC
1 fail-safe output
1 input pin supporting static and dynamic error signal reporting
Programmable periodic system wake-up feature
Documentation available for customers that need support when dealing with ASIL requirements as per ISO26262
VFQFN56+4L 8x8x0.9 with wettable flank, 0.8 mm package

Description

The SPSB100 is a fully integrated automotive power management system IC, especially designed for highly integrated application processors (for example, Stellar G and P MCU families), offering low power mode and high current capability: the device comes with enhanced system power supply functionality. It combines a 3-switch mode power supply together with two integrated linear voltage regulators. The device integrates a further 2 wake-up inputs and advanced fail-safe functionalities. VFQFN56 + 4L 8x8x0.9 mm Product status link SPSB100 Product summary Order code Packing Description SPSB100BTR Tape and reel System supply configuration SPSB100PTR System supply configuration Automotive power management IC for highly integrated processors SPSB100 Datasheet DS14640 - Rev 2 - October 2024 For further information contact your local STMicroelectronics sales office.

The boost controller is intended only to sustain cold cranking pulses, start stop and weak battery conditions for a transitory time. Different combinations enable to supply the system microcontroller, external peripheral loads and sensors in several and adjustable voltage and current ranges. SPSB100 is delivered out of ST factory with default values (rails, power-up and down sequences) stored in USER-NVM space as reported in system supply configuration 1 for SPSB100B and in system supply configuration 2 for SPSB100P, but can be also reprogrammed by customers based on different application needs. The ST standard SPI interface allows control and diagnosis of the device and enables generic software development. The device offers a set of features to support applications that need to fulfill functional safety requirements as defined by Automotive Safety Integrity Level (ASIL). SPSB100 DS14640 - Rev 2 page 2/213

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram

1.2 Pin description

Figure 2. Pin connection (top view) Table 1. Pin function

1 FB2 BUCK2 feedback voltage (to internal voltage monitors) I

3 LDO1 5 V voltage regulator 1 output O

5 GND DS monitoring ground -

8 GBY Gate driver of external MOS bypass BOOST O

9 FBB BOOST feedback pin and supply for LDO1 and LDO2, OUT_HS, VREG, WU and IGN blocks I

10 VS Boost input I

11 OUT_HS High-side-driver output to supply contacts O

12 WU Wake-up input for static or cyclic monitoring of external contact I

13 IGN Wake-up input for static or cyclic monitoring of external contact with KL15 feature I

14 DLB Drain monitoring of external low-side MOS of BOOST I

# Name Description I/O type

15 GLB Gate driver of external low-side MOS of BOOST O

16 PGND3 BUCK3 power ground -

17 PGND3, 2nd pin Current capability (pin description see above) -

18 PGND3, 3rd pin Current capability (pin description see above) -

19 PH3 Switching node BUCK3 I/O

20 PH3, 2nd pin Current capability (pin description see above) O

21 PH3, 3rd pin Current capability (pin description see above) O

22 PH3, 4th pin Current capability (pin description see above) O

23 BST3 Boot-strap capacitor to supply BUCK3 high-side MOS gate-driver circuitry -

24 VIN3 Input voltage BUCK3 I

25 VIN3, 2nd pin Current capability (pin description see above) I

26 VIN3, 3rd pin Current capability (pin description see above) I

27 FB3 BUCK3 feedback voltage (to internal voltage monitors) I

28 COMP3 BUCK3 error amplifier compensation network -

29 NFSO1 Fail-safe output (active low, open drain) O

30 SWDBG Debug input to deactivate the window watchdog (active high) and entering pin for NVM

31 FIN1 FCCU sequence input I

32 N.C.(1) Not connected - 33 N.C.(1) Not connected -

34 SGND Signal ground (analog and digital reference) -

35 VIO I/O power supply (3.3 V or 5 V) I

36 IRQ Interrupt (open drain) O

37 SDO SPI serial data output O

38 CSN SPI chip select not input I

39 CLK SPI serial clock input I

40 SDI SPI serial data input I

41 NRST Reset output to microcontroller, internal pull-up (open drain) O

42 FB1 BUCK1 feedback voltage (to internal voltage monitors) I

43 COMP1 BUCK1 error amplifier compensation network -

44 PGND1 BUCK1 power ground -

45 PGND1, 2nd pin Current capability (pin description see above) -

46 PH1 Switching node BUCK1 I/O

47 PH1, 2nd pin Current capability (pin description see above) O

48 BST1 Boot-strap capacitor to supply BUCK1 high-side MOS gate-driver circuitry -

49 VIN12 Input voltage BUCK1 and BUCK2 I

50 VIN12 Current capability (pin description see above) I

51 BST2 Boot-strap capacitor to supply BUCK2 high-side MOS gate-driver circuitry -

52 PH2 Switching node BUCK2 I/O

53 PH2, 2nd pin Current capability (pin description see above) O

54 PGND2 BUCK2 power ground -

Block diagram and pin description DS14640 - Rev 2 page 5/213

# Name Description I/O type

55 PGND2, 2nd pin Current capability (pin description see above) -

56 COMP2 BUCK2 error amplifier compensation network -

It is suggested to connect the N.C. pins to ground. SPSB100 Block diagram and pin description DS14640 - Rev 2 page 6/213

2 Maximum ratings

2.1 Operating range

operate properly if maximum operating conditions are exceeded. All voltages are related to the potential at substrate ground pin. Table 2. Operating conditions

VS operating range from 3 V up to Vfbb_regx is intended as a transitory time during cranking conditions.

2.1.1 Supply voltage ranges

SPI thresholds
Oscillator frequency (delay times correctly elapsed)
Internal register status correctly kept (reset at default values for VS < VPORVS_F)
Reset threshold correctly detected

2.2 Absolute maximum ratings

All voltages are related to the potential at substrate ground pin. Table 3. Absolute maximum ratings

Symbol Parameter Condition Min Typ Max Unit VGBY Bypass gate driver voltage range VGBY < VFBB + 0.3 V -0.3 - 40 V VREG 3.3 V regulator output for bucks bootstrap -0.3 - 4.6 V VIN12_JS BUCK1 and 2 input voltage range Jump start VIN12 < VFBB + 0.3 V -0.3 - 29 V VIN12_LD BUCK1 and 2 input voltage range VIN12 < VFBB + 0.3 V Load dump 400 ms max -0.3 - 40 V VFB1 BUCK1 input voltage range VFB1 < VFBB + 0.3 V -0.3 - 20 V VFB2 BUCK2 input voltage range VFB2 < VFBB + 0.3 V -0.3 - 20 V VPH1(1) BUCK1 input voltage range -0.3 - 40 V VPH2(1) BUCK2 input voltage range -0.3 - 40 V VBST1 BUCK1 input voltage range -0.3 - 40 V VBST2 BUCK2 input voltage range -0.3 - 40 V VCOMP1 BUCK1 input voltage range -0.3 - 4.6 V VCOMP2 BUCK2 input voltage range -0.3 - 4.6 V VIN3 BUCK3 input voltage range -0.3 - 20 V VFB3 Buck3 feedback voltage range -0.3 - 20 V VPH3(1) Buck3 feedback voltage range -0.3 - 20 V VBST3 Buck3 feedback voltage range -0.3 - 20 V VCOMP3 Buck3 feedback voltage range -0.3 - 4.6 V VLDO1 Stabilized supply voltage 1 VLDO1 < VFBB -0.3 - 6.5 V VLDO2 Stabilized supply voltage 2 VLDO2 < VFBB -0.3 - 20 V VIO I/O supply voltage -0.3 - 20 V VSDI Logic input -0.3 - 20 V VCLK Logic input -0.3 - 20 V VCSN Logic input -0.3 - 20 V VSDO Logic output -0.3 - 20 V VNRST Open drain output (with internal pull up) -0.3 - 20 V VIRQ Open drain output (with internal pull up) -0.3 - 20 V VSWDBG Debug input pin voltage range -0.3 - 20 V VFIN1 FIN1 input voltage range -0.3 - 20 V VNFSO1 Open drain output (without internal pull up) -0.3 - 40 V VWU_JS DC wake-up input voltage Jump start -0.3 - 29 V VIGN_JS DC wake-up input voltage Jump start -0.3 - 29 V VWU_LD DC wake-up input voltage Load dump 400 ms max -0.3 - 40 V VIGN_LD DC wake-up input voltage Load dump 400 ms max -0.3 - 40 V IInput(2) Current injection into FBB related input pins WU, IGN -20 - 20 mA Iout_inj(2) Current injection into FBB related outputs OUT_HS -20 - 20 mA VOUT_HS Output voltage -0.3 - 40 V IOUT_HS Current injection OUT_HS(2) -20 - 20 mA SPSB100 Maximum ratings DS14640 - Rev 2 page 8/213

Transients on this pin can be tolerated for a duration < 100 ns, not exceeding -3 V.
Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power

dissipation or other limits. Guaranteed by design.

2.3 ESD robustness

Table 4. ESD protection

HBM (human body model, 100 pF, 1.5 kΩ) according to the AEC-Q100-0022.
HBM with all none zapped pins grounded.
CDM (charged device model) according to the AEC-Q100-011.

2.4 Temperature ranges and thermal data

Table 5. Temperature ranges and thermal data

is still operative and functional up to 185 °C. The device functionality over 150 °C is guaranteed by characterization. thermal profiles are described below in a 4 layers board. Figure 3. VFQFN56+4L printed circuit board 4 layers - Top layer

LDO1 (5 V): charged with 100 mA (DC activation)
LDO2 (5 V): charged with 5 mA (DC activation)
OUT_HS: Iload = 20 mA (DC activation)
BUCK1 (3.3 V): charged with 1 A (DC activation) at 400 kHz
BUCK2 (5.0 V): charged with 1 A (DC activation) at 400 kHz
BUCK3 (0.98 V): charged with 2 A (DC activation) at 2.4 MHz Case B
LDO1 (5 V): charged with 100 mA (DC activation)
LDO2 (5 V): charged with 5 mA (DC activation)
OUT_HS: Iload = 20 mA (DC activation)
BUCK1 (3.3 V): charged with 1 A (DC activation) at 2.4 MHz SPSB100 Maximum ratings DS14640 - Rev 2 page 10/213

BUCK2 (5.0 V): charged with 1 A (DC activation) at 2.4 MHz
BUCK3 (0.98 V): charged with 2 A (DC activation) at 2.4 MHz Note: 1. BUCK3 load current is already considered in the power dissipation calculation, so 1 A is referred to BUCK1 external loads current. 2. Selecting the switching frequency at 2.4 MHz for BUCK1 and BUCK2 will lower the regulators efficiency and this extra power to be dissipated can generate a faster thermal shut-down. In case the application requires a high DC current load, it is strongly suggested using the switching frequency at 400 kHz for BUCK1 and BUCK2. The following curves show the relationship between max power dissipation vs ambient temperature:

Figure 4. Max power dissipation vs ambient temperature for case "A" and case "B"

3 Functional description

3.1 Supply configurations

the two main configurations where it is required to provide direct or indirect supply to the microcontroller core.

3.1.1 System supply configuration 1

Figure 5. Configuration 1: direct supply of the microcontroller core a switching frequency of 400 kHz. Boost supplies always LDO1 and LDO2, both providing 5 V for external loads.

Turn ON BUCK1 at 3.3 V, wait PG (BUCK1_PG_OK flag);
Turn ON BUCK3 at 0.98 V, wait PG (BUCK3_PG_OK flag);
Turn ON BUCK2 at 5 V, wait PG (BUCK2_PG_OK flag);
Turn ON LDO2 in tracker of buck 2, wait PG (LDO2_PG_OK flag);
Turn ON LDO1, wait PG (LDO1_PG_OK flag).
Turn OFF LDO2 and LDO1, wait 2 ms;
Turn OFF BUCK3, wait 2 ms;
Turn OFF BUCK1 and BUCK2, wait 2 ms;
Turn OFF VREG after 10 ms.

3.1.2 System supply configuration 2

Figure 6. Configuration 2: direct supply of the microcontroller core by internal SMPS

Turn ON BUCK1 at 5 V, wait PG (BUCK1_PG_OK flag);
Turn ON BUCK2 at 5 V, wait PG (BUCK2_PG_OK flag);
Turn ON BUCK3 at 3.3 V, wait PG;
Deassert NRST, wait 0 ms;
Turn ON LDO2 in tracker of BUCK3, wait 0 ms;
Turn ON LDO1, wait PG (LDO1_PG_OK flag).
Turn OFF LDO1, wait 0 ms;
Turn OFF LDO2, wait 0 ms;
Turn OFF BUCK3, wait 2 ms;
Turn OFF BUCK2, wait 2 ms;
Turn OFF BUCK1, wait 0 ms;
Turn OFF VREG after 10 ms.

low power mode allowing SPI communication.

3.1.3 Digital interface supply: VIO

VIO pin supplies the SPI interface, and pins IRQ, FIN1, NRST, RxD_C, TxD_C. VIO can be supplied from one of SPSB100’s BUCK, or from an external regulator. Digital pins functionalities are guaranteed when VIO > VVIO_UV_R (VIO_UV flag not raised).

3.2 Boost controller

only during low battery conditions for a transitory time, or for sustaining deep cranking. The block diagram of the boost is shown in the figure below. Figure 7. Boost controller block diagram overall losses during normal operation. BYPASS_DIS = 1 in the USER-NVM space.

At power-up, the bypass control is enabled when the state machine enters in INIT state (after successful safety checks). If VS > VTH_BYPASS_R, the external bypass switch is turned on (BYPASS_STATUS = 1) while the boost pwm is forced low. When VS < VTH_BYPASS_F, the external switch is turned off (BYPASS_STATUS = 0) and the boost switching is activated.
In ACTIVE–FULL-POWER mode and in RECOVERY-1 state, when VS > VTH_BYPASS_R, the external bypass switch is turned on after tF_BYPASS_EN timing (BYPASS_STATUS = 1) and the boost pwm is forced low if FBB > FBB_REG1 (or FBB_REG2) threshold. When VS < VTH_BYPASS_F, the bypass switch is turned off after tF_BYPASS_DIS timing (BYPASS_STATUS = 0) and the boost switching is activated if FBB < FBB_REG1 (or FBB_REG2) threshold.
In ACTIVE–LOW-POWER mode, the BYPASS controller is disabled, turning off the external switch (BYPASS_STATUS = 0): the consumption on the battery is limited to a few mAmps so no dissipation issue is expected in the external diode.
In ACTIVE–LOW-POWER mode, the BOOST IP is disabled to reduce the overall SPSB100 consumption. It is woken up when the monitored VFBB becomes close to the minimum operating supply (FBB_OK_LP_F1 or FBB_OK_LP_F2) for the remaining active BUCK with duty cycle BOOST_DC_LP.
In RECOVERY-2 or DEEP-SLEEP state, the boost is always OFF and the BYPASS controller is always disabled (BYPASS_STATUS = 0). SPSB100 Functional description DS14640 - Rev 2 page 14/213

At power-up, the bypass control is enabled, turning on the external switch (BYPASS_STATUS = 1), as soon as the state machine reaches the INIT state and following successful safety checks.
In ACTIVE–FULL-POWER mode and in RECOVERY-1 state, the BYPASS switch is turned on whatever the VS voltage (BYPASS_STATUS = 1).
In ACTIVE–LOW-POWER mode, DEEP-SLEEP or RECOVERY-2 state, the BYPASS controller is disabled, turning off the external switch (BYPASS_STATUS = 0). The block diagram of the device when boost is not used is shown in the figure Figure 8. Note: The D1_rev_protection diode is needed only if there is not a reverse battery protection solution already implemented in the application.

Figure 8. Boost controller disabled block diagram

3.2.1 Power-up/down and voltage drop behavior

voltage supply should be clearly defined. General behavior is described in the following figures. Figure 9. Battery plug/unplug behavior (1)Digital comparator in ACTIVE–Full-Power & REC-1, programmable threshold.

Figure 10. Battery drop behavior (1)Digital comparator in ACTIVE– Full-Power & REC-1, programmable threshold.

Figure 11. Behavior on battery over voltage (1) Digital comparator in ACTIVE– Full-Power & REC-1, programmable threshold.

3.3 BUCK converters

3.3.1 BUCK1 converter

compensation network is external. Output voltages are programmable via USER-NVM through the bit BUCK1_PU_VALUE. The spread spectrum feature is configurable by SPI bit BUCK1_SPREAD_ENA (disabled by default). efficiency in active low power mode. (BUCK1 is a mandatory regulator in active low power mode). active low power mode, the action of enable BUCK1 is not allowed. The live bit VBUCK1_ENA_STATUS reflects the state of BUCK1 output. current value associated in DCR1.

UV detection to monitor the output voltage (flag is BUCK1_UV). BUCK1 is therefore switched off after timing tbuck1_UV_TO except if SPI bit MASK_BUCK1_UV_POWER_OFF is set.
Undervoltage detection generates an IRQ except if MASK_BUCK1_IRQ is set.
OV detection to monitor the output voltage (flag is BUCK1_OV bit) BUCK1 is therefore switched off after timing tbuck1_OV_TO. Status register bit BUCK1_OV must be read and cleared before switching ON the regulator by SPI bit VBUCK1_ENA to allow a proper start-up (only when BUCK1 is not critical for MCU).
Overvoltage detection generates an IRQ except if MASK_BUCK1_IRQ is set. SPSB100 Functional description DS14640 - Rev 2 page 17/213

Power-good used to signal BUCK power on success (flag is BUCK1_PG_OK bit and IRQ is generated except if MASK_BUCK1_PG_IRQ is set): – If not, after TBUCK1_PG_TO timing, BUCK1 is switched off and flag BUCK1_PG_TIMEOUT is set.
Not successful power-good detection generates an IRQ except if MASK_BUCK1_PG_TIMEOUT_IRQ is set.
Configurable over current protection through U-NVM BUCK1_IPEAK (flag is BUCK1_OC bit). BUCK1 is therefore switched off after timing tbuck1_OC_TO except if MASK_BUCK1_OC_POWER_OFF is set.
Overcurrent detection generates an IRQ except if MASK_BUCK1_OC_IRQ is set.
Warning temperature detection by a local thermal sensor (flag is TW_CL1).
Warning temperature detection generates an IRQ except if MASK_CL1_TW_IRQ is set.
Overtemperature detection by a local thermal sensor (flag is TSD_CL1, see also the Section 4.7: Temperature monitoring) and buck1 is switched off.
BUCK1 internal regulators detection flag is BUCK1_INT_FAIL and the BUCK1 is switched off.
Internal fail generates an IRQ except if MASK_BUCK1_IRQ is set
After a fault detection (UV, OV,OC, FBLOSS, TSD_CL1 or PG timeout), BUCK1 can be re enabled by setting BUCK1_ENA = 0 followed by BUCK1_ENA = 1.
BUCK1 feedback (FB1) pin disconnection, flag is BUCK1_FBLOSS and the BUCK1 is switched off.
FB1 pin disconnection generates an IRQ except if MASK_BUCK1_IRQ is set.
Overtemperature detection by a central thermal sensor (flag is TSD_CL0, see also the Section 4.7: Temperature monitoring) and device is executed power down sequence. In active low power, BUCK1 converter provides the following diagnostics:
UV detection to monitor the output voltage (flag is BUCK1_UV). BUCK1 is therefore switched off except if SPI bit MASK_BUCK1_UV_POWER_OFF is set.
Undervoltage detection generates an IRQ except if MASK_BUCK1_IRQ is set.
OV detection to monitor the output voltage (flag is BUCK1_OV bit) BUCK1 is therefore switched off.
Overvoltage detection generates an IRQ except if MASK_BUCK1_IRQ is set.
Overcurrent protection (flag is BUCK1_OC bit). BUCK1 is therefore switched off except if MASK_BUCK1_OC_POWER_OFF is set.
Overcurrent detection generates an IRQ except if MASK_BUCK1_OC_IRQ is set.
BUCK1 feedback (FB1) pin disconnection, flag is BUCK1_UV and the BUCK1 is switched off.
FB1 pin disconnection generates an IRQ except if MASK_BUCK1_IRQ is set.
Overtemperature detection by central thermal sensor (flag is TSD_CL0, see also the Section 4.7: Temperature monitoring) and device is executed power down sequence. In active and REC-1 states, when BUCK1_REGFAIL_GO_REC is set at 1 in USER-NVM, in case of PG timeout, OV, UV, INT_FAIL, OC, FBLOSS, or TSD events the device executes a power down sequence, enters in REC-2 state and makes an automatic retry. PG_TIMEOUT, OV, UV, OC, INT_FAIL, FBLOSS or TSD flags are not blocking to re-enable the BUCK1 after a fail event. According to a suitably configured output voltage, it can be also used to supply other BUCKs. It is not recommended to use MASK_BUCK1_OC_POWER_OFF and MASK_BUCK1_UV_POWER_OFF in the same time.

3.3.2 BUCK2 converter

The BUCK2 converter is the same as the BUCK1. The BUCK2 regulator is a synchronous converter compatible to battery level, with integrated power mos. Stability compensation network is external. Output voltages are programmable via USER-NVM through the bit BUCK2_PU_VALUE. The switching frequency can be selected either at 400 kHz or 2.4 MHz, by USER-NVM BUCK2_FREQ. To limit emission in audio bandwidth, refresh frequency can be forced at 25 kHz by USER-NVM bit BUCK2_REFRESH_FREQ set low (1 kHz when high). The draw back will be an extra consumption in low power mode. The spread spectrum feature is configurable by SPI bit BUCK2_SPREAD_ENA (disabled by default). BUCK2 integrates a low power mode (automatically set by LOW_POWER_SET by SPI) that optimizes its efficiency in active low power mode. (BUCK2 can be optionally enabled in active low power mode). SPSB100 Functional description DS14640 - Rev 2 page 18/213

BUCK2 can be disabled by the SPI bit VBUCK2_ENA. (only after SPI_PROTECT_ACCESS has been set). In active low power mode, the action of enable BUCK2 is not allowed. The live bit VBUCK2_ENA_STATUS reflects the state of BUCK2 output. Note: After the first power up is needed to align the live bit associated in DSR18 (VBUCK2_ENA_STATUS) with the current value associated in DCR1. In active full power BUCK2 converter provides the following diagnostics:

UV detection to monitor the output voltage (flag is BUCK2_UV). BUCK2 is therefore switched off after tbuck2_UV_TO except if SPI bit MASK_BUCK2_UV_POWER_OFF is set.
Undervoltage detection generates an IRQ except if MASK_BUCK2_IRQ is set.
OV detection to monitor the output voltage (flag is BUCK2_OV bit) BUCK2 is therefore switched off after tbuck2_OV_TO. Status register bit BUCK2_OV must be read and cleared before switching ON the regulator by SPI bit VBUCK2_ENA to allow a proper start-up (only when BUCK2 is not critical for MCU).
Overvoltage detection generates an IRQ except if MASK_BUCK2_IRQ is set.
Power-good used to signal BUCK power on success (flag is BUCK2_PG_OK bit and IRQ is generated except if MASK_BUCK2_PG_IRQ is set): – If not, after TBUCK2_PG_TO timing, BUCK2 is switched off and flag BUCK2_PG_TIMEOUT is set.
Not successful power-good detection generates an IRQ except if MASK_BUCK2_PG_TIMEOUT_IRQ is set.
Configurable overcurrent protection through U-NVM BUCK2_IPEAK(flag is BUCK2_OC bit). BUCK2 is therefore switched off after tbuck2_OC_TO except if MASK_BUCK2_OC_POWER_OFF is set.
Overcurrent detection generates an IRQ except if MASK_BUCK2_OC_IRQ is set.
Warning temperature detection by a local thermal sensor (flag is TW_CL2).
Warning temperature detection generates an IRQ except if MASK_CL2_TW_IRQ is set.
Overtemperature detection by a local thermal sensor (flag is TSD_CL2, see also the Section 4.7: Temperature monitoring) and BUCK2 is switched off.
BUCK2 internal regulators detection, flag is BUCK2_INT_FAIL and the BUCK2 is switched off.
Internal fail generates an IRQ except if MASK_BUCK2_IRQ is set.
BUCK2 Feedback (FB2) pin disconnection, flag is BUCK2_UV and the BUCK2 is switched off.
FB2 pin disconnection generates an IRQ except if MASK_BUCK2_IRQ is set.
After a fault detection (UV, OV,OC, FBLOSS, TSD_CL2 or PG timeout), BUCK2 can be re‑enabled by setting BUCK2_ENA = 0 followed by BUCK2_ENA = 1. In active low power, BUCK2 converter provides the following diagnostics:
UV detection to monitor the output voltage (flag is BUCK2_UV). BUCK2 is therefore switched off except if SPI bit MASK_BUCK2_UV_POWER_OFF is set.
Undervoltage detection generates an IRQ except if MASK_BUCK2_IRQ is set.
OV detection to monitor the output voltage (flag is BUCK2_OV bit) BUCK2 is therefore switched off.
Overvoltage detection generates an IRQ except if MASK_BUCK2_IRQ is set.
Overcurrent protection (flag is BUCK2_OC bit). BUCK2 is therefore switched off except if MASK_BUCK2_OC_POWER_OFF is set.
Overcurrent detection generates an IRQ except if MASK_BUCK2_OC_IRQ is set.
BUCK2 feedback (FB2) pin disconnection, flag is BUCK2_FBLOSS and the BUCK2 is switched off.
FB2 pin disconnection generates an IRQ except if MASK_BUCK2_IRQ is set.
Overtemperature detection by a central thermal sensor (flag is TSD_CL0, see also the Section 4.7: Temperature monitoring) and device is executed power down sequence. In active and REC-1 states, when BUCK2_REGFAIL_GO_REC is set at 1 in USER-NVM, in case of PG timeout, OV, UV, INT_FAIL, OC, FBLOSS or TSD events the device executes a power down sequence, enters in REC-2 state and makes an automatic retry. PG_TIMEOUT, OV, UV, OC, INT_FAIL, FBLOSS or TSD flags are not blocking to re-enable the BUCK2 after a fail event. It is not recommended to use MASK_BUCK2_OC_POWER_OFF and MASK_BUCK2_UV_POWER_OFF in the same time.

3.3.3 BUCK3 converter

BUCK3 is a postregulator and needs to be supplied by BUCK1 or BUCK2 through the VIN3 pin. SPSB100 Functional description DS14640 - Rev 2 page 19/213

The BUCK3 converter is similar to BUCK1 but with double current capability. Moreover, if the output voltage is configured at 0.98 V, a further SPI fine-tuning in steps of 10 mV is available (BUCK3_FTUNE[2..0] control bits), covering the range between 0.95 V and 1.01 V. Output voltages are programmable via USER-NVM through the bit BUCK3_PU_VALUE. The spread spectrum feature is configurable by SPI bit BUCK3_SPREAD_ENA (disabled by default). To limit emission in audio bandwidth, refresh frequency can be forced at 25 kHz by USER-NVM bit BUCK3_REFRESH_FREQ set low (1 kHz when high). BUCK3 can be disabled by the SPI bit VBUCK3_ENA. (only after SPI_PROTECT_ACCESS has been set. BUCK3 must be disabled before entering in active low power mode and must not be enabled in this mode). The live bit VBUCK3_ENA_STATUS reflects the state of BUCK3 output. Note: After the first power up is needed to align the live bit associated in DSR18 (VBUCK3_ENA_STATUS) with the current value associated in DCR1. The BUCK3 converter provides the following diagnostics:

UV detection to monitor the output voltage (flag is BUCK3_UV). BUCK3 is therefore switched off after tbuck3_UV_TO except if SPI bit MASK_BUCK3_UV_POWER_OFF is set.
Undervoltage detection generates an IRQ except if MASK_BUCK3_IRQ is set.
OV detection to monitor the output voltage (flag is BUCK3_OV bit) BUCK3 is therefore switched off after tbuck3_OV_TO. It must be read and cleared before switching ON the regulator by SPI bit VBUCK3_ENA to allow a proper start-up (only when BUCK3 is not critical for MCU).
Overvoltage detection generates an IRQ except if MASK_BUCK3_IRQ is set.
Power-good used to signal BUCK power on success (flag is BUCK3_PG_OK bit and IRQ is generated except if MASK_BUCK3_PG_IRQ is set): – If not, after TBUCK3_PG_TO timing, BUCK3 is switched off and flag BUCK3_PG_TIMEOUT is set.
Not successful power-good detection generates an IRQ except if MASK_BUCK3_PG_TIMEOUT_IRQ is set.
Configurable overcurrent protection voltage (flag is BUCK3_OC bit). BUCK3 is therefore switched off after tbuck3_OC_TO except if MASK_BUCK3_OC_POWER_OFF is set.
Overcurrent detection generates an IRQ except if MASK_BUCK3_OC_IRQ is set.
Warning temperature detection by a local thermal sensor (flag is TW_CL3).
Warning temperature detection generates an IRQ except if MASK_CL3_TW_IRQ is set.
Overtemperature detection by local thermal sensor (flag is TSD_CL3, see also the Section 4.7: Temperature monitoring) and BUCK3 is switched off.
BUCK3 internal regulators detection, flag is BUCK3_INT_FAIL and the BUCK3 is switched off.
Internal fail generates an IRQ except if MASK_BUCK3_IRQ is set.
After a fault detection (UV, OV,OC, INT_FAIL, TSD_CL3 or PG timeout), BUCK3 can be re‑enabled by setting BUCK3_ENA = 0 followed by BUCK3_ENA = 1. In active and REC-1 states, when BUCK3_REGFAIL_GO_REC is set at 1 in USER-NVM, in case of PG timeout, OV, UV, OC, INT_FAIL or TSD events the device executes a power down sequence, enters in REC-2 state and makes an automatic retry. PG_TIMEOUT, OV, UV, OC, INT_FAIL or TSD flags are not blocking to re-enable the BUCK3 after a fail event. It is not recommended to use MASK_BUCK3_OC_POWER_OFF and MASK_BUCK3_UV_POWER_OFF in the same time.

3.4 Linear voltage regulators

3.4.1 LDO1

The LDO1 is dedicated to supply external loads. It is supplied by FBB pin. LDO1 has a 5 V output and 120 mA current capability. It can be enabled/disabled through the LDO1_ENA control bit (only after SPI_PROTECT_ACCESS has been set). The voltage regulator is protected against undervoltage (flag is LDO1_UV) and LDO1 is switched off. The undervoltage detection generates an IRQ except if it is masked with MASK_LDO1_IRQ the live bit LDO1_ENA_STATUS reflects the state of LDO1 output. SPSB100 Functional description DS14640 - Rev 2 page 20/213

current value associated in DCR1.

Power-good used to signal LDO1 power on success (flag is LDO1_PG_OK bit): – If not, after TLDO1_PG_TO timing, LDO1 is switched off and flag LDO1_PG_TIMEOUT is set.
The power on success generates an IRQ except if it is masked with MASK_LDO1_PG_IRQ.
Not successful power-good detection generates an IRQ except if MASK_LDO1_PG_TIMEOUT_IRQ is set.
After a fault detection (UV or PG timeout), LDO1 can be re‑enabled by setting LDO1_ENA = 0 followed by LDO1_ENA = 1, even if fail flags are not cleared. Current limitation ILDO1_Cmax of the regulator ensures fast charge of external decoupling capacitors. The output voltage is stable for ceramic load capacitors CLDO1_load ≥ 1 µF. Warning temperature detection by a local thermal sensor (flag is TW_CL0). Warning temperature detection generates an IRQ except if MASK_CL0_TW_IRQ is set. In case the device temperature exceeds the TSD_CL0 threshold, the device executes a power down sequence before entering in REC-2 state.

3.4.2 LDO2

must be disabled before entering in active low power mode and must not be enabled in this mode). if related output voltages are 5 V or 3.3 V (see the Table 6). Table 6. Voltage regulators configuration

3.3 V or 5 V Tracks buck1

6.5 V OFF what ever LDO2_ENA

3.3 V or 5 V Tracks buck2

3.3 V Tracks buck3

The live bit LDO2_ENA_STATUS reflects the state of LDO2 output. Note: After the first power-up is needed to align the live bit associated in DSR18 (LDO2_ENA_STATUS) with the current value associated in DCR1.
Overvoltage detection to monitor the output voltage (flag is LDO2_OV bit) and LDO2 is therefore switched off.
Overvoltage detection generates an IRQ except if MASK_LDO2_IRQ is set.
Undervoltage detection (the flag is LDO2_UV bit) and LDO2 are therefore switched off.
Undervoltage detection generates an IRQ except if MASK_LDO2_IRQ is set.
Power-good used to signal LDO2 power on success (flag is LDO2_PG_OK bit).
If not, after TLDO2_PG_TO timing, LDO2 is switched off and flag LDO2_PG_TIMEOUT is set.
The power-on success generates an IRQ except if it is masked with MASK_LDO2_PG_IRQ.
Not successful power-good detection generates an IRQ except if MASK_LDO2_PG_TIMEOUT_IRQ is set.
Warning temperature detection by a local thermal sensor(flag is TW_CL4).
Warning temperature detection generates an IRQ except if MASK_CL4_TW_IRQ is set. SPSB100 Functional description DS14640 - Rev 2 page 21/213

Overtemperature detection by local thermal sensor (flag is TSD_CL4, see also the Section 4.7: Temperature monitoring) and LDO2 is switched off.
After a fault detection (UV, OV, TSD_CL4 or PG timeout), LDO2 can be re‑enabled by setting LDO2_ENA = 0 followed by LDO2_ENA = 1, even if fail flags are not cleared.
LDO2 is switched off if a fault on the track regulator is detected.
In active and REC-1 states, when LDO2_REGFAIL_GO_REC is set at 1 in USER-NVM, in case of PG timeout, OV, UV or TSD events the device executes a power down sequence, enters in REC-2 state and makes an automatic retry.

3.5 Operating modes

mode (ACTIVE state - LOW-POWER mode). SET control bit, only after SPI_PROTECT_ACCESS has been set). In ACTIVE state the device is fully controllable and configurable through SPI. CLR_DEEP_SLEEP_FROM_DO_POWER_DOWN bit.

3.5.1 Wake-up from DEEP-SLEEP to ACTIVE state

and transitions description. SPI_ALL_WAKEUP_DISABLE is set and generates an IRQ except if MASK_SPI_ERROR_IRQ is set. Table 7. Wake-up events description

Wake-up event can be missed during SPI writing to DO_POWER_DOWN = 1.

3.5.2 Wake-up events in ACTIVE mode

interrupt request on IRQ pin.

3.6 Functional overview - State machine

Section 3.6.3: States and transitions description).

3.6.1 State machine without fault transitions

Figure 12. State machine without fault transitions released and START-SM state is reached where oscillators start and NVM is read and checked. Refer to the Section 3.8: User's NVM modification procedure for details of USER-NVM space programming. supervision to the MCU. Later the MCU can reconfigure the SPSB100 in FULL-POWER mode by SPI.

3.6.2 State machine focusing on fault transitions

3.6.2.1 NVM faults management

3.6.2.2 Watchdog trig and FCCU monitor faults management

dedicated to watchdog and FCCU monitor faults management. Figure 13. State machine details with WD trig and FCCU monitor faults management window timeout will initiate a transition to ACTIVE state. watchdog runs with normal window timings.

Increment the watchdog trig fault counter (only on watchdog trig fault);
Assert NRST pin low;
Disable and reset the FCCU monitor;
Initiate a power-up sequence: this is mandatory to power backup regulators that could have been switched off by SPI. Then the NRST pin remains asserted for 4 ms, at least, in case of watchdog trig fault, 6 ms at least, in case of FCCU monitor fault, before being released, watchdog starts a long open window timeout and SPSB100 reaches RECOVERY-1 state. In case of successive faults in servicing the watchdog in a long open window the watchdog trig fault counter is incremented, a power-up sequence is run, a 4 ms NRST pulse is generated and a long open window timeout is restarted. If the watchdog is properly served during the long open window, then the watchdog trig fault counter is reset and SPSB100 enters in ACTIVE state. The 8 successive watchdog trig faults force SPSB100 to initiate a power cycle through RECOVERY-2 and INIT states. And in case of 15 successive watchdog trig faults SPSB100 will enter in a DEEP-SLEEP state. Note: In this specific case, the IVDS current consumption is higher (worst case 4.8 mA max) than expected (40 μA max). The FCCU monitor is disabled and its configuration reset after the first watchdog trig fault. FCCU monitor can be reconfigured and enabled through SPI in RECOVERY-1 or ACTIVE state. SPSB100 Functional description DS14640 - Rev 2 page 24/213

3.6.2.3 Power-up fault management

counter runs, it is longer than the maximum rising time of SPSB100 regulators. PU_LOOP_FOR_EVER bit is set SPSB100 retries to power-up forever. has its REGFAIL_GO_REC configuration bit set to 1. See the Section 3.7.1: Power-up sequence for details. Figure 14. State machine details on power-up fault (1) watchdog trig fault or a FCCU monitor fault detection as shown in the following figure.

Figure 15. State machine details on power-up fault (2)

3.6.2.4 Central thermal sensor fault management

run and SPSB100 reaches RECOVERY-2 state. status register flag FORCED_SLEEP_TSD. bit. This counter is incremented after a TSD event on any of the clusters.

Figure 16. State machine details onTSDC fault

3.6.2.5 Regulator faults management

Temperature sensor with a warning threshold (TW) and a shut-down threshold (TSD)
Undervoltage comparator (UV) except for LDO1
Overvoltage comparator (OV)
Power-good comparator (PG_TIMEOUT)
Overcurrent comparator (OC) on BUCKs
Internal regulator comparator (INT_FAIL) on BUCKs
FB pin disconnection (FBLOSS for BUCK1 and BUCK2) The user can decide how SPSB100 shall react on an event of those monitors, this is done through the USER- NVM bit REGFAIL_GO_REC of each of them. A TW event sets the associated flag and generates an interruption, while the reaction to a TSD, UV, PG_TIMEOUT, OC, INT_FAIL, FBLOSS and OV event depends on the regulator REGFAIL_GO_REC bit. When REGFAIL_GO_REC is set to ‘1’, a fault detected on regulator TSD, UV, PG_TIMEOUT, OC, INT_FAIL, FBLOSS and OV monitors will initiate a power-down sequence, then the state machine transits to INIT state and runs a power-up sequence: if a fault is detected then the retry sequence described in the Section 3.6.2.3: Power- up fault management is executed. In the case of TSD the SPSB100 reaction is the same as for the TSDC event described in the Section 3.6.2.4: Central thermal sensor fault management. A fault event counter REG_FAIL_CNT is incremented when a power-down sequence is initiated by a regulator fault event. When the counter reaches 3, SPSB100 transits to DEEP-SLEEP state where the counter is reset and the SPI flag FORCED_SLEEP_REGFAIL is set. REG_FAIL_CNT is cleared by SPI bit CLR_REG_FAIL_CNT. SPSB100 Functional description DS14640 - Rev 2 page 27/213

Figure 17. Regulator faults reaction with REGFAIL_GO_REC = 1

Set the associated flag.
Send an interruption. The interruption can be masked for UV, OC, INT_FAIL, FBLOSS and OV and TW, not for TSD.
Switch OFF the regulator if the action is not masked. Action of UV and OC is maskable, while an INT_FAIL, FBLOSS, OV and TSD event always switch OFF the regulator. TW event never switches OFF the regulator. The state machine does not change its state if REGFAIL_GO_REC is reset to ‘0’. SPSB100 Functional description DS14640 - Rev 2 page 28/213

Figure 18. Regulator faults reaction with REGFAIL_GO_REC = 0

3.6.2.6 FBB voltage drop management

INIT state SPSB100 restarts when the FBB pin voltage rises above VFBB_OK_R. Figure 19. FBB pin voltage fault reaction Figure 20. VS pin voltage fault reaction

3.6.3 States and transitions description

The following figure shows the entire state machine. Figure 21. State machine SPSB100 states can be read by status register bits DEV_STATE.

3.6.3.1 Power-OFF state

Power-OFF state is the default state when SPSB100 is not powered. This state is entered unconditionally when VS pin voltage drops below VPORVS_F.

3.6.3.2 START-UP state

START-UP state is entered from Power-OFF state when VS pin voltage reaches VPORVS_R. In this state internal power supplies are established, and the digital core reset is released. SPSB100 transits to START-SM state.

3.6.3.3 START-SM state

START-SM state is entered after the START-UP completion when the digital core reset is released. programming mode, refers to the Section 3.8: User's NVM modification procedure for details.

3.6.3.4 INIT state

After completion of START-SM state and NVM is loaded without error.
From a DEEP-SLEEP state upon a wake-up event. SPSB100 Functional description DS14640 - Rev 2 page 31/213

From RECOVERY-2 state when: – MCU sent a SPI command DO_POWER_CYCLE (only after SPI_PROTECT_ACCESS has been set) in ACTIVE or RECOVERY-1 state. – FBB pin voltage is below VFBB_UV_F and VS pin voltage above VPORVS_F. – One thermal sensor detected a TSD event, the chip temperature cooled down and the TSD counter does not reached 3. – A fault has been detected on a critical regulator output voltage (REGFAIL_GO_REC = 1). – 8 successive watchdog trigger faults have been detected
In case a fault has been detected during the power-up sequence and the power-up retry counter does not reach 3, or LOOP_FOR_EVER bit is set to 1. In INIT state, when FBB pin voltage rises above VFBB_OK_R (the minimum voltage allowing SPSB100 to power‑up), SPSB100 executes the digital BIST before initiating a power-up sequence.

3.6.3.5 ACTIVE state

ACTIVE state is the state reached after a successful power-up sequence, after the MCU did a read and clear of SPI error flags in RECOVERY-1 state and trig the watchdog in long open window timeout. In ACTIVE state the SPSB100 can be configured in FULL- or LOW- POWER modes. In both modes the MCU can configure the watchdog timings and control NFSO1 pin through SPI. Reactions to fault detection are independent of the POWER modes.

3.6.3.5.1 FULL-POWER mode

FULL-POWER mode is the default mode when entering ACTIVE state from RECOVERY-1 state. In FULL-POWER mode, all features of SPSB100 are accessible and configurable by SPI registers, in particular MCU can switch OFF some regulators to optimize ECU power consumption. In FULL-POWER mode, regulator monitors are active and analog and digital BIST can be run on demand by the MCU. Watchdog is running and must be served, except if LOW_SET = 1111. NFSO1 pin is controllable by SPI register.

3.6.3.5.2 LOW-POWER mode

LOW-POWER mode is accessible by SPI in ACTIVE state from FULL-POWER mode. In this mode the SPSB100 power consumption is reduced by:

Turning OFF low-level hardware monitors.
Turning OFF the redundant voltage and current bias blocks.
Turning OFF NVM runtime checks.
Turning OFF the ADC.
Analog and digital BIST shall not be executed on demand. In LOW-POWER mode:
The watchdog is running and must be served (except if WD_LP_ENA is set at 0), its timing is configurable to further reduce power consumption.
Central thermal monitoring is active,
If BUCK 1 and/or BUCK 2 and/or LDO 1 is/are kept ON in its/their low power setting then OV and UV monitoring are active (see the Section 3.8: User's NVM modification procedure for functional safety details).
Other regulators must be turned OFF before entering in LOW-POWER mode, MCU can decide to leave this mode by SPI command and return to FULL-POWER mode. In LOW-POWER mode the VIO must be supplied and SPSB100 offers three possibilities:
All regulators are turned OFF: in this case VIO must be supplied by an external regulator.
Only BUCK1 is kept ON in its low-power configuration. BUCK1, or an external regulator, is used to supply VIO.
BUCK1 and 2 are kept ON in their low-power configuration. BUCK1 or 2, or an external regulator, are used to supply VIO.

3.6.3.5.3 Transitions between FULL-POWER and LOW-POWER modes

Transitions between the two modes are under the responsibility of the MCU. SPSB100 Functional description DS14640 - Rev 2 page 32/213

To transit to LOW-POWER mode the following sequence must be played by the MCU:

Assert low NFSO1 output (optional).
Reconfigure watchdog timing (optional).
Disable the watchdog by setting WD_LP_ENA = 0 (optional).
Turn off the FCCU monitoring feature.
Turn OFF regulators BUCK3 and LDO2.
BUCK1 and/or BUCK2 can be kept ON if one of it is used to supply VIO.
Configure wake-up sources and IRQ generation (optional). Until this step, the SPSB100 is still in FULL-POWER mode, but with tuned settings.
Set to 1 SPI bit LOW_POWER_SET (only after SPI_PROTECT_ACCESS has been set). This last action sets SPSB100 in LOW-POWER mode, SPSB100 generates an interruption to confirm the proper entrance in LOW-POWER mode (except if MASK_LP_READY_IRQ is set) and sets status bit LP_READY. To transit from LOW-POWER to FULL-POWER mode the following sequence must be played by the MCU:
Clear to 0 SPI bit LOW_POWER_SET (only after SPI_PROTECT_ACCESS has been set). This first action sets SPSB100 in FULL-POWER mode, SPSB100 generates an interruption to confirm the proper entrance in FULL-POWER mode and sets status bit FP_READY. MCU must wait for this confirmation before continuing, then:
Clear low power setting of regulator(s) 1 and/or 2 kept ON before its/their load current increases.
Turn ON other regulator(s) as per application needs.
Reconfigure watchdog timing to satisfy functional safety requirements (optional).
Turn ON the FCCU monitoring feature.
Trigger watchdog during LOW if WD_LP_ENA = 0 (optional).
Configure wake-up sources and IRQ generation (optional).
Deassert NFSO1 output. The low-level hardware monitoring is turned back ON when SPI bit LOW_POWER_SET is cleared. If a hardware fault is detected, SPSB100 transits asynchronously to DEEP-SLEEP state. LOW_POWER_SET, FP_READY and LP_READY are not automatically cleared in case of transition due to hard fail.

3.6.3.6 RECOVERY-1 state

SPSB100 enters in RECOVERY-1 state in two cases:

From INIT state after the power-up sequence ended successfully.
From ACTIVE state after a WD trigger issue or a FCCU fault is detected. When entering the RECOVERY-1 state:
NFSO1 output is asserted low.
FCCU monitoring is turned OFF.
WD starts a LOW, except if LOW_SET = 1111. In this state all voltage regulators are set according to the power-up sequence settings stored in USER-NVM. If some of the voltage regulators configured in the power-up sequence were switched off in ACTIVE state through the SPI, they are enabled upon entering in RECOVERY-1 state. The transition from RECOVERY-1 to ACTIVE state is started after the MCU has read and cleared error flags (if any, see the Section 9.8: Status register that must be cleared to enter into active FP mode) and trigged the WD in LOW. In RECOVERY-1 state, the MCU cannot deassert NFSO1 output. A further WD trigger fault generates a NRST low pulse of at least 4 ms long. See the Section 3.10: Configurable time-out window watchdog for further details. If FCCU is enabled by MCU and a FCCU fault is detected then SPSB100 remains in RECOVERY-1 state and generates a NRST low pulse of at least 6 ms long. See the Section 3.11: FIN1 input for details.

3.6.3.7 RECOVERY-2 state

SPSB100 enters in RECOVERY-2 state from ACTIVE state and generates status register bit FSM_TO_REC2 = 0 in case of:

DO_POWER_CYCLE SPI command (only after SPI_PROTECT_ACCESS has been set).
The temperature of the central sensor overpassed the TSDC threshold. SPSB100 Functional description DS14640 - Rev 2 page 33/213

A fault on one of the regulators occurred and its REGFAIL_GO_REC configuration bit is set to 1.
FBB pin voltage falls below its power down threshold. SPSB100 enters in RECOVERY-2 state from ACTIVE state and generates status register bit REC2_FROM_DO_POWER_CYCLE = 01 in case of DO_POWER_CYCLE SPI command (only after SPI_PROTECT_ACCESS has been set) REC2_FROM_DO_POWER_CYCLE can be cleared by CLR_REC2_FROM_DO_POWER_CYCLE bit. SPSB100 enters in RECOVERY-2 state from RECOVERY-1 state and generates status register bit FSM_TO_REC2 = 1 in case of:
DO_POWER_CYCLE SPI command (only after SPI_PROTECT_ACCESS has been set).
The temperature of the central sensor overpassed the TSDC threshold.
A fault on one of the regulators occurred and its REGFAIL_GO_REC configuration bit is set to 1.
8 consecutive WD trigger faults.
FBB pin voltage falls below its power down threshold. SPSB100 enters in RECOVERY-2 state from RECOVERY-1 state and generates status register bit REC2_FROM_DO_POWER_CYCLE = 1X in case of DO_POWER_CYCLE SPI command (only after SPI_PROTECT_ACCESS has been set) REC2_FROM_DO_POWER_CYCLE can be cleared by CLR_REC2_FROM_DO_POWER_CYCLE bit. When entering RECOVERY-2 state:
The NFSO1 output is asserted low.
FCCU monitoring is turned OFF.
NRST is asserted low and regulators are turned off according to the programmed power-down sequence.
In case of a TSD event the TSD counter is incremented and SPSB100 waits that the temperature cools down. From RECOVERY-2 state SPSB100 transits to DEEP-SLEEP state for unrecoverable fault, or to INIT state to power-up again.

3.6.3.8 DEEP-SLEEP state - Unrecoverable faults

SPSB100 enters in DEEP-SLEEP state from ACTIVE-FULL-POWER mode or REC-1 states in case of:

DO_POWER_DOWN SPI command (only after SPI_PROTECT_ACCESS has been set).
Power ground lost. SPSB100 enters in DEEP-SLEEP state from RECOVERY-1 state in case of:
DO_POWER_DOWN SPI command (only after SPI_PROTECT_ACCESS has been set).
Power ground lost.
15 consecutive WD trigger faults. SPSB100 enters in DEEP-SLEEP state from RECOVERY-2 state in case of:
The temperature of one sensor overpassed the TSD threshold and the TSD counter (TSD_CNT_FAIL) reached 3.
The counter of regulator (REG_FAIL_CNT) fail events reached 3. When entering the DEEP-SLEEP state from ACTIVE or RECOVERY-1 states:
The NFSO1 output is asserted low.
FCCU monitoring is turned OFF.
NRST is asserted low and regulators are turned off according to the programmed power-down sequence. SPSB100 remains in a DEEP-SLEEP state until a wake-up event occurs. The design of SPSB100 has been optimized to offer a very-low power consumption while being wake-able by external events. DEEP-SLEEP state is also entered:
In case of hardware low-level error, refer to the Section 4.8: HW low-level monitors for details.
From INIT state in case of safety check error, refer to the Section 4.17: Safety checks for details.
In case of repetitive power-up fault, refer to the Section 3.6.2.3: Power-up fault management. SPSB100 Functional description DS14640 - Rev 2 page 34/213

3.7 Power-up and power-down sequence

are fully programmable through the USER-NVM space to cover a broad range of applications. The sequences control BUCK1, 2, 3 and LDO1, 2 regulators, together with NRST pin.

3.7.1 Power-up sequence

Power-up sequence is made of 7 steps as described below. Figure 22. Power-up sequence from 1 to 7. None, or more than one regulator can be turned ON at a step. independently of regulators setting. Note that the watchdog time-out starts at the step where NRST is deasserted.

If this option is selected, then the device waits for the PG signal of all turned ON regulators at step N. A time-out is used to detect a fault: if the time-out expires a power-down sequence is executed and a retry procedure is started as described in the Section 3.6.2.3: Power-up fault management.
If not, or when PG level is reached, the sequence is paused for a programmable delay with USER-NVM bits PU_WAIT_DEL_ENA_X (X equal to steps from 1 to 7) before proceeding to the next step. While the sequence executes, any regulator fault is managed as per its REGFAIL_GO_REC setting as described in the Section 3.6.2.5: Regulator faults management.

3.7.2 Power-down sequence

Power-down sequence is made of 7 steps as described below. Figure 23. Power-down sequence from 1 to 7. None, or more than one regulator can be turned OFF at a step. independently of regulators setting. Note that the watchdog is stopped before step 1. delay with USER-NVM bits PD_WAIT_DEL_OFF_X (X equal to steps from 1 to 7). with USER-NVM bits PD_WAIT_VREG_DEL_OFF.

3.8 User's NVM modification procedure

SPSB100 integrates nonvolatile memory (NVM) to store ST factory trim data and customer’s personalization data. Trim data are stored in ST-NVM space while customer’s data are stored in USER-NVM space. default power-up and power-down settings can be found in the Section 3.1.1: System supply configuration 1. The customer has the possibility to reprogram USER-NVM space only once; or use default values stored by ST. release. The default value is 0d.

Green: SPSB100 starts up with valid data stored in ST-NVM and USER-NVM (USER-NVM previously programmed by ST or by the customer).
Blue: SPSB100 enters in the USER-NVM programming procedure.
Orange: USER-NVM emulation feature is used.

Figure 24. Procedure to program the NVM

3.8.1 Starts-up with valid NVM data and NVM faults management

The ST-NVM data are read in ST-NVM-DL state, then USER-NVM data are read in U-NVM_DL state. state where further safety check will be performed.

3.8.2 USER-NVM emulation

It is possible to emulate the USER-NVM content using the data stored in RAM image. This can only be done when the USER-NVM has not been programmed by user. have been read and their CRC checked. At this stage, the SWDBG pin can be released and do not have to be maintained higher than VNVM_EMU_H. It is forbidden to enable regulators in the USER-NVM-PROG-1 state.

The USER-NVM emulated values are lost if power supply at VS pin is below VPORVS_R. During emulation mode the value of U_NVM_CRC0 and U_NVM_CRC1 bits in DCR17 and DCR25 is not considered by the device. In USER-NVM emulation mode the runtime check of USER-NVM is disabled. For this reason, the USER-NVM emulation mode shall be used for debug purpose only.

3.8.3 USER-NVM programming procedure

The user can emulate the USER-NVM as many times as he wants as far as the USER-NVM is not programmed by the user. Once programmed by user, the USER-NVM cannot be emulated and the device proceeds with valid data stored in USER-NVM. To program USER-NVM, it is necessary to first emulate the USER-NVM with desired configuration. During this emulation for programming, the user must perform at least write to DCR17 and DCR25 with any value corresponding to its need. This is needed to initiate some bits that will be used to allow proper programming. USER-NVM uses NVM CRC to check that NVM content is correct but during programming, the user does not have to care of this because the correct CRC will be calculated by SPSB100 from emulated data and will be programmed with emulated data. Then, instead of GO_INIT bit set through SPI access, the user must set the U-NVM_PROG bit (only after SPI_PROTECT_ACCESS has been set). This starts the USER-NVM programming and sets the device in USER- NVM-PROG-2 state. When the USER-NVM programming is completed, the status bit NVM_PROG_DONE is set. The user can read this status bit through SPI access. When this bit is set, the user can read the NVM_PROG_OK status bit to verify that the USER-NVM programming has completed correctly because the USER-NVM programming is followed by the USER-NVM verification. If the USER-NVM programming has failed and the NVM_PROG_OK status bit is low when the NVM_PROG_DONE status bit is set, the user may request a new programming by resetting the U-NVM_PROG control bit (only after SPI_PROTECT_ACCESS has been set) then setting again this bit. This operation can be done 2 times, so there is a maximum programming of 3 times. If at the end of 3 USER_NVM programming request, NVM_PROG_OK is still low when NVM_PROG_DONE is high, the chip cannot anymore be programmed and cannot start correctly. In this case, any new programming request is ignored. After valid USER-NVM programming procedure the U_NVM SPI registers from DCR10 to DRC28 can be only readable.

3.8.4 Loading USER-NVM data in RAM image

To program the USER-NVM it is necessary to load the data (CRC included) in a dedicated portion of the RAM. It is automatically done by state machine.

3.9 Wake-up inputs: IGN and WU

Both inputs can be configured as wake-up sources (through IGN_ENA and WU_ENA control bits). In particular, the input IGN can be used as a wake-up source connected to ignition (KL15) via a resistor. The voltage can be also read back via SPI through a 10-bit ADC monitoring (IGN[9..0] bits, in addition to WU[9..0] ones). This can be achieved only if WU_CONFIG bit and IGN_CONFIG bit are set to ”1”. Each wake-up input is sensitive to any level transition (positive and negative edge) and can be configured for static or cyclic monitoring of the input voltage level by suitable setting of bits WU_FILT and IGN_FILT which allows to choose the monitoring among static or cyclic with timer. When the configuration of a timer is changed, the timer is automatically restarted using the new configuration. For static contact monitoring, a filter time of tWU_stat, tIGN_stat is implemented. The filter is started when the input voltage crosses the specified threshold Vwuthp, VIGNthp (both thresholds are linked to VFBB level). Wake-up status bit (WU_WAKE and IGN_WAKE bits) is set only if this threshold is passed for more than tWU_stat, tIGN_stat. Cyclic contact monitoring allows instead periodical (not threshold dependent) activation of the wake-up input to read the status of the external contact. The periodical activation is driven by timer whose settings (on-time and The input signal is filtered with a filter time of tWU_cyc (tIGN_cyc ) after a delay (80% of the configured timer on- time). A wake-up will be processed if the status has changed versus the previous cycle, therefore wake-up status WU_WAKE and IGN_WAKE bits are set only if the status during consecutive on-time is different, after configured delay and tWU_cyc. (tIGN_cyc). This can be done only if WU_CONFIG and IGN_CONFIG are configured as wake- up inputs. SPSB100 Functional description DS14640 - Rev 2 page 38/213

In active low power or DEEP-SLEEP modes the inputs WU and IGN are configurable with an internal pull-up or pull-down current source according to the setup WU_PU and IGN_PU SPI bits. In active full power mode the inputs have an internal pull-down resistor (RWU_act) and the inputs status can be read by WU_STATE and IGN_STATE. This can be done only if WU_CONFIG and IGN_CONFIG are configured as wake-up inputs and if WU_ENA and IGN_ENA are set high. The output OUT_HS can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up input. If WU_ENA = 1 and WU_CONFIG = 1, the wake up capability and the voltage measurement through ADC are both activated on WU pin. If IGN_ENA = 1 and IGN_CONFIG = 1, the wake up capability and the voltage measurement through ADC are both activated on IGN pin.

3.10 Configurable time-out window watchdog

During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle. After the power-up sequence, the watchdog starts with a long open window tLW. The watchdog allows the microcontroller to run its own setup and then to start the window watchdog by setting WD_TRIG=1. Long open window tLW is configurable by USER-NVM through the bits LOW_SET [3..0]. Subsequently, the microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area Tswx.. The trigger time is configurable by SPI. A correct watchdog trigger signal will immediately start the next cycle. A watchdog trig will not take into account if NRST pin is low. If LOW_SET [3..0] is set at “1111”, the long open window is set in infinite duration. In this case, if the application does not require a watchdog, the microcontroller must not trig the watchdog. So, the device will transit from REC-1 to active full power after a read and clear of error flags. If the watchdog is triggered even with LOW_SET [3..0] set to “1111”, the watchdog starts with the default window and then has to be served. Note that in the case of LOW_SET = 1111, so in the case of the watchdog service is disabled, it must be considered in the safety analysis based on FIT calculation, as described in the safety manual. The watchdog trigger time can be configured by setting the WD_TIME [3..0] bits (only after SPI_PROTECT_ACCESS has been set) and the default value is 0001 (window 2). The change of watchdog window timing through WD_TIME in SPI registers cannot be done when the watchdog is in long open window counting. The microcontroller can read the LOW_STATUS bit to know if the watchdog is in long open window phase (when LOW_STATUS is high) or in normal window (when LOW_STATUS is low). When in long open window phase, the LOW_STATUS bit is high even if the watchdog is in infinite long open window. When not in infinite long open window, if FSM is in ACTIVE_HP or ACTIVE_LP state, the LOW_STATUS is low and watchdog counts in normal window. When LOW_STATUS is high, the current watchdog LOW is given by LOW_SET[3:0]. When LOW_STATUS is low, the current watchdog window is given by WD_TIME_STATUS[3:0]. During REC-1 FSM state, WD_TIME[3:0] cannot be written because the watchdog is counting in long open window. In the case of WD_FAIL or FCCU_FAIL occurs the watchdog starts in long open window when NRST rises. In this case, the watchdog trig bit is automatically cleared. So, the microcontroller can trig the watchdog with a WD_TRIG bit high. The new value of WD_TIME is loaded in the watchdog module on the next trig event after the SPI configuration. The following watchdog cycle uses the new programmed value. This means that when a watchdog is running on a current window, to change the window, the microcontroller must:

Write in WD_TIME(3-0) the new watchdog window.
Trig the watchdog in the current window. Doing this, the watchdog restarts using the new window. It is possible to disable the watchdog in ACTIVE - LOW-POWER mode only through the WD_LP_ENA bit set at “0” (only after SPI_PROTECT_ACCESS has been set). If WD_LP_ENA is set high during ACTIVE - LOW- POWER mode, the watchdog will stay disabled and will restart with a long open window after the transition Active- LP to Active-FP. Fault conditions can be detected through the following bits:
The status bit WD_ENA_ECHO indicates that the watchdog is running when high. SPSB100 Functional description DS14640 - Rev 2 page 39/213

The status bit WD_ENA_ECHO_ERROR indicates a watchdog echo error and generates an IRQ. This error can be masked by MASK_WD_ENA_ECHO_ERROR_IRQ.
In case of watchdog fail a flag WDFAIL is set and the watchdog fail counter WDFAIL_CNT is incremented up to 15 consecutive watchdog trig faults. After 15 consecutive watchdog trig faults, the bit FORCED_SLEEP_WDFAIL is set and the device will reach the DEEP-SLEEP state.
WDFAIL_CNT can be reset by CLR_WDFAIL_CNT bit.
The microcontroller can know the current state of watchdog by reading WD_TIMER_STATE(1-0) WD_TIMER_STATE = 00, WD trig is too early widow trig, WD_TIMER_STATE = 01, WD trig is in valid window trig.

3.11 FIN1 input

SPSB100 integrates an MCU fault monitoring called FCCU. FCCU block can be configured to detect error reported by the MCU through FIN1 input. Two error reporting protocols are available: static and dynamic protocols.

3.11.1 Static protocol

In this protocol MCU signals its own errors to SPSB100 by driving FIN1 input pin at low or high level. MCU shall configure the SPSB100 FCCU block as the following:

FCCU_PROTOCOL shall be reset to 0.
FCCU_STATIC_ERROR shall be reset to 0 if MCU signals error driving FIN1 low, or set to 1 if MCU signals error driving FIN1 high.
MCU shall drive FIN1.
FCCU_ENA shall be set at 1 to enable the monitoring feature (only after SPI_PROTECT_ACCESS has been set).

3.11.2 Dynamic protocol

In this protocol MCU signals its own error to SPSB100 by increasing the period, or half period, of the toggling signal sent to FIN1 input. The FCCU block shall be programmed to monitor half period of the toggling signal received on FIN1. The FCCU block is made of a counter clocked by a 400 kHz clock derived from the main oscillator. The counter is reset at each transition on FIN1 input, if the counter overflows then an error is signaled. The counter overflow threshold is programmed on FCCU_COUNTER<12:0> (only after SPI_PROTECT_ACCESS has been set). The oscillator accuracy shall be considered to calculate the value of this threshold, the following formula can be used: FCCU_COUNTER > FIN1_half_period * (400 kHz + main oscillator accuracy) Example: with an MCU toggling signal at 4 882.8 Hz (min) with 50% of duty cycle, and 20% accuracy of SPSB100 oscillator. FCCU_COUNTER > (204.8/2) µs * (400 kHz * 1.2) = 49.15 Gives FCCU_COUNTER = 50 at minimum. MCU shall configure the SPSB100 FCCU block as the following:

FCCU_PROTOCOL shall be set to 1.
FCCU_STATIC_ERROR can be used to configure an internal pull-up (set to 1) or an internal pull-down (reset to 0) on FIN1 input.
FCCU_COUNTER shall be loaded to the overflow threshold (only after SPI_PROTECT_ACCESS has been set).
MCU shall drive FIN1 with the proper toggling signal.
FCCU_ENA shall be set at 1 to enable the monitoring feature (only after SPI_PROTECT_ACCESS has been set). Each time a transition is detected on FIN1 input the register FCCU_LAST_STABLE<12:0> is loaded with the last value of the FCCU counter. MCU can read back this value through SPI. SPSB100 Functional description DS14640 - Rev 2 page 40/213

3.11.3 Reaction on error

When an error is detected by the MCU fault monitoring, the NRST pin is asserted low, the status bit FCCUFAIL is set, the state machine reacts as described in the Section 3.6.2.2: Watchdog trig and FCCU monitor faults management. The live status bit FIN1_STATE shows the current state of FIN1 input. To properly restart FCCU block after a FCCUFAIL detection, MCU has to write FCCU_ENA = 0, clear the FCCUFAIL flag and re-enable the monitoring by setting FCCU_ENA = 1. The live bit FCCU_ENA_STATUS reflects the state of the FCCU block.

3.12 High-side output OUT_HS

In active, FULL-POWER or LOW-POWER modes, and in DEEP_SLEEP states the high side driver output OUT_HS can be configured for supplying external loads or contacts. The high side output can be either controlled:

Permanently ON (OUTHS_[1..0] = 01)
Permanently OFF (OUTHS_[1..0] = 00)
Through an internal timer (OUTHS_[1..0] = 1x) In timer mode configuration (when TIMER_ENA = 1) the activation period can be configured through the bits T1_PER [2..0] in the following range {10, 20, 50,100, 200, 500, 1000, 2000 ms}. In case the wake-up inputs WU and IGN are configured in cyclic sense mode(WU_FILT = 1, IGN_FILT = 1)), the capture of their input state is synchronized with the high-side timer mode:
A switched ON delay time tDON_OUT_HS is applied after the high-side is turned ON.
A switched OFF delay time tDOFF_OUT_HS is applied after the high-side is turned OFF.
A fixed filter time of tWU_cyc is applied after blanking time has elapsed before refreshing the WU_WAKE or IGN_WAKE.
In case of status change detection between the previous and the new captured state, the status bits WU_WAKE and IGN_WAKE will be set in the status register. Depending on the dedicated settings applied on each wake-up input, wake-up detection could wake-up the SPSB100 and/or generate an interrupt signal on the IRQ pin. In case of overcurrent, detection is done by OUTHS_OC bit, OUTHS driver is switched off after filter time toc_out_hs and an IRQ is generated except if MASK_OUTHS_IRQ is set. After an OC detection, OUTHS can be re-enabled by clearing the status bit OUTHS_OC. In case of open load, detection is done by OUTHS_OL bit, an IRQ is generated except if MASK_OUTHS_IRQ is set. The live bit OUTHS_ENA_STATUS reflects the state of OUTHS output. Note: The high-side driver OUT_HS is intended to drive resistive loads only. Therefore, only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 100 μH) an external freewheeling diode connected between GND and the OUT_HS pin is required.

3.13 Fail-safe output - NFSO1

NFSO1 is asserted low when a fault event is detected. The objective of this pin is to drive an electrical safe circuitry independent from the MCU to deactivate the whole system and set the ECU in a protected and known state. The NFSO1 pin is an open drain output. An external pull-up circuitry must be connected to VIO or VBAT. The NFSO1 pin is controlled by an asynchronous OR of:

Asynchronous supervisor of internal voltage reference. When a difference between the main and monitoring voltage reference is detected the NFSO1 pin is asserted low.
Synchronous monitor of main oscillator. When an oscillator frequency drift or a stuck at is detected the NFSO1 pin is asserted low.
When a watchdog or FCCU fail occurs the NFSO1 pin is asserted low.
The SPI control bit NFSO_ASSERT_LOW (only after SPI_PROTECT_ACCESS has been set): – NFSO_ASSERT_LOW = 1: pin is asserted low. – NFSO_ASSERT_LOW = 0: pin is in high impedance. Its level is defined by external pull-up. SPSB100 Functional description DS14640 - Rev 2 page 41/213

asserted (level high) in DEEP-SLEEP. NFSO1 pin fully controllable by the MCU in ACTIVE state.

NFSO1_ECHO = 0: NFSO1 output pad is asserted low.
NFSO1_ECHO = 1: the NFSO1 output pad is pulled-up by external circuitry.

Figure 25. NFSO1 implementation details SPI when the application is ready to start.

Figure 26. NFSO1 output pin behavior at battery plug Figure 27. NFSO1 output pin behavior after a failure is detected

3.14 Interrupt - IRQ

Table 8. IRQ events

SPI status bit name IRQ generated IRQ SPI mask name BUCK1_PG_OK Y MASK_BUCK1_PG_IRQ BUCK1_PG_TIMEOUT Y MASK_BUCK1_PG_TIMEOUT_IRQ BUCK1_UV Y if BUCK1_REGFAIL_GO_REC = 0 MASK_BUCK1_IRQ BUCK2_OC Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_OC_IRQ BUCK2_OV Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK2_FB Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK2_PG_OK Y MASK_BUCK2_PG_IRQ BUCK2_PG_TIMEOUT Y MASK_BUCK2_PG_TIMEOUT_IRQ BUCK2_UV Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK3_OC Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_OC_IRQ BUCK3_OV Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_IRQ BUCK3_PG_OK Y MASK_BUCK3_PG_IRQ BUCK3_PG_TIMEOUT Y MASK_BUCK3_PG_TIMEOUT_IRQ BUCK3_UV Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_IRQ BUCK1_INT_FAIL Y if BUCK1_REGFAIL_GO_REC = 0 MASK_BUCK1_IRQ BUCK2_INT_FAIL Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK3_INT_FAIL Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_IRQ BYPASS_VDSMON_ERROR Y MASK_BYPASS_VDSMON_IRQ NFSO1_ECHO_ERROR Y MASK_NFSO1_ECHO_ERROR_IRQ FBB_OV Y MASK_FBB_OV_IRQ FBB_OV_EW Y MASK_FBB_OV_EW_IRQ FBB_UV Y MASK_FBB_UV_IRQ FBB_UV_EW Y MASK_FBB_UV_EW_IRQ FCCU_ENA_ECHO_ERROR Y MASK_FCCU_ENA_ECHO_ERROR_IRQ IRQ_REQUEST Y Not maskable LDO1_PG_OK Y MASK_LDO1_PG_IRQ LDO1_PG_TIMEOUT Y MASK_LDO1_PG_TIMEOUT_IRQ LDO1_UV Y MASK_LDO1_IRQ LDO2_OV Y if LDO2_REGFAIL_GO_REC = 0 MASK_LDO2_IRQ LDO2_PG_OK Y MASK_LDO2_PG_IRQ LDO2_PG_TIMEOUT Y MASK_LDO2_PG_TIMEOUT_IRQ LDO2_UV Y if LDO2_REGFAIL_GO_REC = 0 MASK_LDO2_IRQ NVM_PROG_DONE Y Not maskable OUTHS_OC Y MASK_OUTHS_IRQ OUTHS_OL Y MASK_OUTHS_IRQ SPI_ALL_WAKEUP_DISABLE Y MASK_SPI_ERROR_IRQ SPI_REG_COMP_ERROR Y MASK_SPI_ERROR_IRQ SPI_CLK_CNT Y MASK_SPI_ERROR_IRQ SPI_CRC_ERR Y MASK_SPI_ERROR_IRQ SPI_CSN_TIMEOUT Y MASK_SPI_ERROR_IRQ SPI_LBISTED Y MASK_SPI_ERROR_IRQ SPSB100 Functional description DS14640 - Rev 2 page 44/213

SPI status bit name IRQ generated IRQ SPI mask name SPI_SDI_STUCK_HIGH Y MASK_SPI_ERROR_IRQ SPI_SDI_STUCK_LOW Y MASK_SPI_ERROR_IRQ SPI_STATUS_WRT Y MASK_SPI_ERROR_IRQ SPI_UNDEF_ADD Y MASK_SPI_ERROR_IRQ VS_UV_EW Y MASK_VS_EW_IRQ TSD_CL1 Y if BUCK1_REGFAIL_GO_REC = 0 Not maskable TSD_CL2 Y if BUCK2_REGFAIL_GO_REC = 0 Not maskable TSD_CL3 Y if BUCK3_REGFAIL_GO_REC = 0 Not maskable TSD_CL4 Y if LDO2_REGFAIL_GO_REC = 0 Not maskable TW_CL0 Y MASK_CL0_TW_IRQ TW_CL1 Y MASK_CL1_TW_IRQ TW_CL2 Y MASK_CL2_TW_IRQ TW_CL3 Y MASK_CL3_TW_IRQ TW_CL4 Y MASK_CL4_TW_IRQ IGN_WAKE Y Not IGN_WAKEUP_ENA TIMER_WAKE Y Not TIMER_WAKE_ENA WU_WAKE Y Not WU_WAKEUP_ENA SWDBG_VIO Y MASK_SWDBG_VIO_IRQ ABIST_COMPLETE Y Not maskable BOOST_IN_LP Y MASK_BOOST_IN_LP_IRQ BOOST_VDSMON_ERROR Y MASK_BOOST_VDSMON_IRQ BUCK1_FB Y if BUCK1_REGFAIL_GO_REC = 0 MASK_BUCK1_IRQ BUCK1_INT_FAIL Y if BUCK1_REGFAIL_GO_REC = 0 MASK_BUCK1_IRQ BUCK1_OC Y if BUCK1_REGFAIL_GO_REC = 0 MASK_BUCK1_OC_IRQ BUCK1_OV Y if BUCK1_REGFAIL_GO_REC = 0 MASK_BUCK1_IRQ BUCK1_PG_OK Y MASK_BUCK1_PG_IRQ BUCK1_PG_TIMEOUT Y MASK_BUCK1_PG_TIMEOUT_IRQ BUCK1_UV Y if BUCK1_REGFAIL_GO_REC = 0 MASK_BUCK1_IRQ BUCK2_FB Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK2_INT_FAIL Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK2_OC Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_OC_IRQ BUCK2_OV Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK2_PG_OK Y MASK_BUCK2_PG_IRQ BUCK2_PG_TIMEOUT Y MASK_BUCK2_PG_TIMEOUT_IRQ BUCK2_UV Y if BUCK2_REGFAIL_GO_REC = 0 MASK_BUCK2_IRQ BUCK3_INT_FAIL Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_IRQ BUCK3_OC Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_OC_IRQ BUCK3_OV Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_IRQ BUCK3_PG_OK Y MASK_BUCK3_PG_IRQ BUCK3_PG_TIMEOUT Y MASK_BUCK3_PG_TIMEOUT_IRQ BUCK3_UV Y if BUCK3_REGFAIL_GO_REC = 0 MASK_BUCK3_IRQ SPSB100 Functional description DS14640 - Rev 2 page 45/213

SPI status bit name IRQ generated IRQ SPI mask name BYPASS_VDSMON_ERROR Y MASK_BYPASS_VDSMON_IRQ FBB_OV Y MASK_FBB_OV_IRQ FBB_OV_EW Y MASK_FBB_OV_EW_IRQ FBB_UV Y MASK_FBB_UV_IRQ FBB_UV_EW Y MASK_FBB_UV_EW_IRQ FCCU_ENA_ECHO_ERROR Y MASK_FCCU_ENA_ECHO_ERROR_IRQ IGN_WAKE Y Not IGN_ENA IRQ_REQUEST Y Not maskable LBIST_COMPLETE Y Not maskable LDO1_PG_OK Y MASK_LDO1_PG_IRQ LDO1_PG_TIMEOUT Y MASK_LDO1_PG_TIMEOUT_IRQ LDO1_UV Y MASK_LDO1_IRQ LDO2_OV Y MASK_LDO2_IRQ LDO2_PG_OK Y MASK_LDO2_PG_IRQ LDO2_PG_TIMEOUT Y MASK_LDO2_PG_TIMEOUT_IRQ LDO2_UV Y MASK_LDO2_IRQ NFSO1_ECHO_ERROR Y MASK_NFSO1_ECHO_ERROR_IRQ NVM_PROG_DONE Y Not maskable OUTHS_OC Y MASK_OUTHS_IRQ OUTHS_OL Y MASK_OUTHS_IRQ SPI_ALL_WAKEUP_DISABLE Y MASK_SPI_ERROR_IRQ SPI_CLK_CNT Y MASK_SPI_ERROR_IRQ SPI_CRC_ERR Y MASK_SPI_ERROR_IRQ SPI_CSN_TIMEOUT Y MASK_SPI_ERROR_IRQ SPI_LBISTED Y MASK_SPI_ERROR_IRQ SPI_REG_COMP_ERROR Y MASK_SPI_ERROR_IRQ SPI_SDI_STUCK_HIGH Y MASK_SPI_ERROR_IRQ SPI_SDI_STUCK_LOW Y MASK_SPI_ERROR_IRQ SPI_STATUS_WRT Y MASK_SPI_ERROR_IRQ SPI_UNDEF_ADD Y MASK_SPI_ERROR_IRQ SWDBG_VIO Y MASK_SWDBG_VIO_IRQ TIMER_WAKE Y Not TIMER_WAKE_ENA TSD_CL1 Y if BUCK1_REGFAIL_GO_REC = 0 Not maskable TSD_CL2 Y if BUCK2_REGFAIL_GO_REC = 0 Not maskable TSD_CL3 Y if BUCK3_REGFAIL_GO_REC = 0 Not maskable TSD_CL4 Y if LDO2_REGFAIL_GO_REC = 0 Not maskable TW_CL0 Y MASK_CL0_TW_IRQ TW_CL1 Y MASK_CL1_TW_IRQ TW_CL2 Y MASK_CL2_TW_IRQ TW_CL3 Y MASK_CL3_TW_IRQ TW_CL4 Y MASK_CL4_TW_IRQ SPSB100 Functional description DS14640 - Rev 2 page 46/213

SPI status bit name IRQ generated IRQ SPI mask name VS_UV_EW Y MASK_VS_EW_IRQ WD_ENA_ECHO_ERROR Y MASK_WD_ENA_ECHO_ERROR_IRQ WU_WAKE Y Not WU_ENA FP_READY Y Not maskable LBIST_STOPPED - Not maskable LP_READY Y MASK_LP_READY_IRQ Interrupt is a NOR of all information except if some masks are set. A read and clear of all setted flags is needed to allow the IRQ pin to be set high. Interrupt output pin indicates:

Warnings and errors which must be reported to the MCU.
Confirmation of a requested action from the MCU.

3.15 Reset output - NRST

The NRST pin is an open-drain with an internal pull-up for the echo-generation. An external pull-up to VIO level close to MCU is strongly recommended. The aim of NRST output is to drive the MCU NRST input pin. The NRST is released after a proper power-up sequence before reaching the RECOVERY-1 state, and is asserted low after tNRST_rt, in case of error as described in the Section 3.6.3: States and transitions description. 3.16 10-bit ADC In ACTIVE – FULL-POWER mode and RECOVERY-1 state the voltage signals VS, FBB, WU, IGN, TH_CL0, TH_CL1, TH_CL2, TH_CL3, and TH_CL4 are read out sequentially. Related bit names in the status register are and TEMP_CL4[0..9]. The voltage signals are multiplexed to an ADC. The ADC is realized as a 10-Bit SAR. Each channel is converted with a conversion time tcon, therefore an update of the ADC value is available every tcon * 13. The voltage measurement on VS, FBB, WU and IGN can be calculated from the binary coded register value using the following formula: Decimal code = (VIN/LSB_V ) – 1 The temperature measurement on TEMP_CL0-4 can be calculated from the binary coded register value using the following formula: Decimal code = ((355 – Tj)/LSB_T) – 1 In case of WU, or IGN, is directly connected to battery line, the input must be protected by a series resistance of typical 1 kΩ to sustain reverse battery condition.

3.17 SW-Debug mode

The SW-Debug mode is intended for software development. In SW-Debug mode SPSB100 is fully operational except that the watchdog is not started and consequently does not monitor proper watchdog trig. To set the device in SW-DEBUG mode, the SWDBG pin must be shorted to VIO before a power-up sequence (cold start or wake up from DEEP-SLEEP). With such setting the device executes the power-up sequence and, instead of reaching RECOVERY-1 state, the device transits to SWDBG state. In SWDBG state the timeout tSWDBG_TO is launched. The timeout is used to prevent the system from being stuck in SWDBG state: If the timeout expires, then SW-Debug mode entry is canceled. The device transits to RECOVERY-1 state and starts the watchdog with a long open window. Status register bit SWDBG_VIO is set, an IRQ (maskable by MASK_SWDBG_VIO_IRQ) is generated to indicate that SWDBG pin is shorted to VIO. If the short to VIO is removed before timeout expiration then the device transits to RECOVERY-1 state, the watchdog is disabled. To transit to ACTIVE-FULL-POWER mode the software must clear error flags and set WD_TRIG, this is the unique access to WD_TRIG that the software must handle in SW-Debug mode. SPSB100 Functional description DS14640 - Rev 2 page 47/213

Any further voltage attachment to SWDBG pin at VIO is ignored, until the next SPSB100 power-up sequence. This helps to protect unwanted SW-Debug mode entry and well enables possible share of this pin with other functions. Once the SW-Debug mode is established, it persists until terminated via SPI command SWDBG_EXIT or until the next power on reset (battery unplug and replug). If terminated by SPI command the watchdog starts immediately with a long open window. The SW-Debug mode status can be monitored by the SPI status register WD_ENA_ECHO = 0. The state of the SWDBG pin can be monitored by the live bit SWDBG_STATE. In final application, it is possible to detect the hardware fault “SWDBG shorted to VIO” using the following procedure. After the MCU boot-up, the software shall read the SPSB100 state. The expected state is REC-1. If the SWDBG pin is faulty shorted to VIO then the device reaches SWDBG state. In such a case it is possible to kill the timeout by setting the KILL_SWDBG_TIMEOUT control bit: the device transits to REC-1 state and the watchdog is enabled disregarding the SWDBG pin voltage. This feature is useful to prevent an increase of start-up time when the hardware fault “SWDBG shorted to VIO” is present.

3.18 VREG

The VREG is dedicated to generate the bootstrap voltage for the BUCKs in active and REC-1 states. It is supplied by FBB pin in active-full power and by FB1 in active-low power. VREG has a 3.3 V output and 150 mA current capability. VREG cannot be used to supply external blocks. The voltage regulator is protected against undervoltage: if the VREG output voltage is going below VVREG_UV for a delay higher than tVREG_UV, flag INT_REG_UV is set and the device will execute a power down sequence to enter in DEEP-SLEEP state. The voltage regulator is protected against overvoltage: if the VREG output voltage is going above VVREG_OV for a delay higher than tVREG_OV, flag INT_REG_OV is set and the device will execute a power down sequence to enter in DEEP-SLEEP state. The voltage regulator is protected against a short to ground during INIT state. If the VREG output voltage is not able to reach VVREG_UV after tVREG_stup, flag INT_REG_UV is set and the device will make a transition to DEEP- SLEEP state. Current limitation IVREG_CCmax of the regulator ensures fast charge of external decoupling capacitor. The output voltage is stable for ceramic load capacitors, see CVREG in the Section 7.22: VREG voltage regulator. Warning temperature detection is managed by a local thermal sensor (flag is TW_CL0). Warning temperature detection generates an IRQ except if MASK_CL0_TW_IRQ is set. In case the device temperature exceeds the TSD_CL0 threshold, the device executes a power down sequence before entering in REC-2 state. SPSB100 Functional description DS14640 - Rev 2 page 48/213

4 Protection, diagnosis and monitoring signals

4.1 Supply monitoring

4.1.1 VS pin

The battery line is monitored through a VS pin. The VS input voltage is monitored through analog comparators and the ADC:

VS input voltage can be read back by SPI access, by VS[9..0].
The ADC is used to detect under voltage early warnings (flagged by VS_UV_EW bit). The thresholds are programmable by SPI (VS_UV_EW_TH[4..0]) and an interrupt is issued when thresholds are crossed except if MASK_VS_EW_IRQ is set.

4.1.2 FBB pin

The FBB input voltage is monitored through analog comparators and the ADC:

Analog comparator is used to detect over and undervoltages. The reaction to a FBB voltage fault is described in the Section 3.6.2.6: FBB voltage drop management.
An analog comparator is used to detect over voltage. The flag is FBB_OV and generates an IRQ except if MASK_FBB_OV_IRQ is set. The state machine executes a power down sequence to enter in DEEP- SLEEP.
An analog comparator is used to detect undervoltage. The flag is FBB_UV and generates an IRQ except if MASK_FBB_UV_IRQ is set. The state machine executes a power down sequence to enter in DEEP- SLEEP.
The ADC is used to detect overvoltage early warnings (flagged by FBB_OV_EW bit).
The ADC is used to detect undervoltage early warnings (flagged by FBB_UV_EW bit).
The thresholds are programmable by SPI (FBB_OV_EW_TH[3..0]) and an interrupt is issued when thresholds are crossed except if MASK_FBB_OV_EW_IRQ is set.
The thresholds are programmable by SPI (FBB_UV_EW_TH[3..0]) and an interrupt is issued when thresholds are crossed, except if MASK_FBB_UV_EW_IRQ is set.
The result of ADC conversion is also readable back via SPI, by FBB[9..0].

4.1.3 VIO pin

VIO voltage is monitored through an analog comparator and digital communication is blocked if VIO voltage is below VVIO_UV threshold for a delay higher than TF_VIO_UV (flag is VIO_UV bit).

4.2 Regulators output voltage protection

The 3 BUCKs and LDO2 outputs are monitored through analog comparators to detect over and undervoltages. (through BUCKx_UV, BUCKx_OV, LDO2_UV and LDO2_OV bits). The reaction to a fault is described in the Section 3.6.2.5: Regulator faults management. In addition, LDO2 is also turned OFF when the tracked regulator is turned OFF in reaction to a fault. When a regulator is turned ON, by SPI or power-up sequence, a short to ground is detected if the output voltage does not reach the power-good threshold in the time-out period (BUCKx_PG_TIMEOUT bit), in such case the regulator is switched OFF. In addition, when turned ON through the SPI, an interrupt is generated as soon as their output voltage reaches the power-good threshold(BUCKx_PG and LDO2_PG bits). Latent fault detection of OV, UV, PG analog comparators is insured by Analog-BIST. Latent fault of regulator monitor handler is insured by Digital-BIST.

4.3 Boost and bypass Vds monitoring

The BOOST driver includes a comparator to monitor the voltage drop across the boost external transistor. The voltage is monitored between DLB and GND pins. SPSB100 Protection, diagnosis and monitoring signals DS14640 - Rev 2 page 49/213

above the programmed threshold for 5 consecutive periods of the BOOST PWM signal. it is masked by MASK_BOOST_VDSMON_IRQ) and the BOOST external transistor is permanently turned OFF. MCU shall read and clear the status flag to turn back ON the BOOST driver. is monitored between VS and FBB pins. (BYPASS_DSMON_TH[2..0] bits) for a delay higher than tF_BYPASS_VDSM time. is masked by MASK_BYPASS_VDSMON_IRQ), the BYPASS external transistor is switched off. Latent fault detection of comparators is insured by Analog-BIST. Figure 28. Boost and bypass Vds monitoring (extracted by application scheme)

4.4 Boost activity monitoring

SPI status bit BOOST_ENA_STATUS. (except if it is masked by MASK_BOOST_IN_LP_IRQ) when the BOOST starts to switch. In other states the BOOST is disabled.

4.5 WU and IGN monitoring

4.6 Ground pin monitoring

GND (both bonded on SGND pin). Section 4.8: HW low-level monitors. Latent fault detection of ground comparators is insured by Analog-BIST.

4.7 Temperature monitoring

thermal sensors. The sensors are suitably located on the device.

set and an interrupt is issued. outputs are shut down or not as described in the Section 3.6.2.5: Regulator faults management. Figure 29. Thermal cluster identification Table 9. Thermal cluster definition Note: • In the DEEP-SLEEP state all clusters are disabled.

In active low power all clusters are disabled except Th_CL0 to detect TSDC. Monitoring of central thermal cluster is insured by analog comparator, while other thermal clusters are monitored through the ADC. Latent fault detection of TSDC thermal comparator is covered by Analog-BIST. Latent fault detection of digital thermal monitor and ADC handler is covered by a Digital-BIST. SPSB100 Protection, diagnosis and monitoring signals DS14640 - Rev 2 page 51/213

4.8 HW low-level monitors

Voltage difference between main and monitoring digital and analog power supplies (INT_REG_UV, INT_REG_OV bits).
Current difference between main and monitoring current sources (CURRENT_MISMATCH bit). and synchronous monitors of:
Frequency difference between main and redundant oscillators (OSC_ERROR bit).
State machine’s state by comparison of main and redundant State machine(FSM_COMP_ERROR bit).
NVM data by: – Comparison of NVM data and redundant registers (NVM_COMP_ERROR bit). – CRC check at NVM download(NVM_CRC_ERROR bit).
Safety critical SPI registers by comparison of main and redundant registers (SPI_REG_COMP_ERROR bit generates an IRQ except if MASK_SPI_ERROR_IRQ is set).
Ground loss connection by cross-checking ground domains(GNDLOSS bit). A fault detected by low-level monitors trigs a power-down sequence and SPSB100 reaches the DEEP-SLEEP state. In such situation, after a wake-up event (except for OSC_ERROR where SPSB100 restarts automatically if oscillators recover their frequencies), all SPI registers are reset except HW low-level monitor flags and SPSB100 transit to START-SM state.

Figure 30. HW low level monitors

4.9 Communication interface

A 4-bit CRC SPI_CRC_ERR is set in case of error detected, and an IRQ is generated except if MASK_SPI_ERROR_IRQ is set.
Clock monitor: during communication (CSN low phase) a clock monitor counts the valid CLK edges. If the CLK edges do not correlate with the SPI data length then SPI_CLK_CNT is set, an IRQ is generated except if MASK_SPI_ERROR_IRQ is set, the actual communication is rejected. SPSB100 Protection, diagnosis and monitoring signals DS14640 - Rev 2 page 52/213

CLK phase check: To verify that the CLK phase of the SPI controller is set correctly a special device information register is implemented. By reading this register the data must be 55H. In case AAH is read the CPHA setting of the SPI controller is wrong and a proper communication cannot be guaranteed.
CSN timeout: if CSN is set low for t > tCSN fail then the frame is rejected and SDO is released to tri-state (SPI_CSN_TIMEOUT is set). An IRQ is generated except if MASK_SPI_ERROR_IRQ is set.
SDI stuck at high detection: an SPI frame consisting of all bits ‘1’ is detected as failure and will be rejected, SPI_SDI_STUCK_HIGH is set and an IRQ is generated except if MASK_SPI_ERROR_IRQ is set.
SDI stuck at low detection: an SPI frame consisting of all bits ‘0’ is detected as failure and will be rejected, SPI_SDI_STUCK_LOW is set and an IRQ is generated except if MASK_SPI_ERROR_IRQ is set.
SDO stuck: the global status byte (GSB) is transmitted within every SPI frame; the definition of the GSB guarantees that a content of all ‘1’ or all ‘0’ is not possible; therefore, the microcontroller can identify if the SDO signal is stuck at high or low level.
Functional safety relevant configuration registers are locked by a dedicated bit SPI_PROTECT_ACCESS. A first SPI command must be sent to unprotect the functional safety relevant registers, then a successive SPI command is sent to modify those configuration registers.
SPI undefined address access is detected by a dedicated bit SPI_UNDEF_ADD. An IRQ is generated except if MASK_SPI_ERROR_IRQ is set.
SPI unwanted write access on a status register is detected by a dedicated bit SPI_STATUS_WRT. An IRQ is generated except if MASK_SPI_ERROR_IRQ is set.
SPI unwanted access during LBIST test is detected and SPI_LBISTED is set. An IRQ is generated except if MASK_SPI_ERROR_IRQ is set. In this case, the SPI frame is rejected.
Functional safety relevant configuration registers are duplicated and a runtime comparison mechanism check the coherency of their data. In case of error the reaction is described in the Section 4.8: HW low- level monitors. Latent fault detection of SPI digital handler, functional safety redundant configuration register and comparison mechanism are covered by a Digital-BIST.

4.10 IRQ pin monitoring

To check that the IRQ line is properly connected to the MCU, an IRQ can be sent to the MCU through SPI request. When MCU sets the SPI bit IRQ_REQUEST, an interrupt is generated on IRQ pin. The MCU can verify that the IRQ has well been sent by checking the IRQ_SENT status bit. Pin IRQ shall be set high after read and clear of IRQ_SENT flag. To detect IRQ stuck high fault, the device embeds:

An echo signal of the IRQ pin: IRQ_ECHO live bit in the status register.
An echo error detection mechanism: IRQ_ECHO_ERROR status bit is set if the device detects an IRQ_ECHO high signal when IRQ pin is asserted low after a filter time TIRQ_ECHO_FILT.

4.11 NRST pin monitoring

To detect NRST stuck high fault, the device embeds:

An echo signal of the NRST pin: NRST_ECHO live bit in the status register.
An echo error detection mechanism: NRST_ECHO_ERROR status bit is set if the device detects an NRST_ECHO high signal when NRST pin is asserted low after a filter time TNRST_ECHO_FILT.

4.12 NFSO1 pin monitoring

To detect NFSO1 stuck high fault, the device embeds:

An echo signal of the NFSO1 pin: NFSO1_ECHO live bit in status register.
An echo error detection mechanism: NFSO1_ECHO_ERROR status bit is set if the device detects an NFSO1_ECHO high signal when NFSO1 pin is asserted low, after a filter time TNFSO_ECHO_FILT and an interrupt is sent to IRQ pin, except if MASK_NFSO1_ECHO_ERROR_IRQ is set.

4.13 Watchdog block monitoring

To detect an improper turn-OFF of the watchdog feature, the device embeds: SPSB100 Protection, diagnosis and monitoring signals DS14640 - Rev 2 page 53/213

An echo signal of the watchdog block enable signal: WD_ENA_ECHO live bit in the status register.
An echo error detection mechanism: WD_ENA_ECHO_ERROR status bit is set if the device detects that the watchdog block is turned OFF while the device is not in SW-DEBUG mode, and an interrupt is sent to IRQ pin, except if MASK_WD_ENA_ECHO_ERROR_IRQ is set.

4.14 FCCU block monitoring

An echo signal of the FCCU monitor block enable signal: FCCU_ENA_ECHO live bit in the status register.
An echo error detection mechanism: FCCU_ENA_ECHO_ERROR status bit is set if the device detects that the FCCU monitor block is turned OFF in ACTIVE state, when FCCU_ENA has been set and an interrupt is sent to IRQ pin, except if MASK_FCCU_ENA_ECHO_ERROR_IRQ is set.

4.15 Analog BIST

ABIST is performed on SPI request. ABIST is expected to be run.

OV, UV, PG analog comparators.
Internal voltage and current supplies monitor.
Central thermal monitor.
BOOST and BYPASS VDS monitors. ABIST must be run only in Active-Full power mode by MCU through the SPI. MCU shall write ABIST bit to request its execution (only after SPI_PROTECT_ACCESS has been set). After TABIST, ABIST is finished, the status bit ABIST_COMPLETE is set and an interrupt is sent to IRQ pin. ABIST_ERROR is set in case an error is detected. For boost VDSM monitoring, to avoid false ABIST error, a status bit ABIST_BOOST_IGNORED will be set at 1 if ABIST request is done during boost PWM activity.

4.16 Logic BIST

LBIST1 is performed at INIT state only.
LBIST2 is performed at INIT state and on SPI request.

Figure 31. Logic BIST

LBIST2 must be run only in Active-Full power mode by MCU through the SPI. MCU shall write LBIST bit to request its execution (only after SPI_PROTECT_ACCESS has been set). The LBIST2 execution is delayed until the NVM controller terminates its self-test After tLBIST, the LBIST2 is finished, the status bit LBIST_COMPLETE is set and an interrupt is sent to IRQ pin. LBIST_ERROR_1 is set in case a LBIST2 error is detected. SPSB100 does not take any action in case of an LBIST2 error is detected. It is the duty of the MCU to proper react on such a signaled error. LBIST error detected in INIT state is considered as a safety check error (see the Section 4.17: Safety checks). Fault management while LBIST is executed:

When LBIST1 and LBIST2 are executed in INIT state the internal faults processed by the blocks under LBIST are masked, their processing by SPSB100 is delayed until the end of LBIST1 & LBIST2.
When LBIST2 is executed on demand in active-full power mode the faults (UV, OV, TSD…) processed by the blocks under LBIST2 are not masked. If a fault occurs the LBIST2 is stopped, status bit LBIST_STOPPED is set and an IRQ is generated, the fault is processed by SPSB100 with appropriate reaction.
As a consequence the watchdog window must be properly set before requesting a LBIST2 execution to let the LBIST2 complete before the next watchdog trig through SPI.

4.17 Safety checks

Safety checks are executed in INIT state. They are made of:

Digital BIST LBIST1 and LBIST2.
Ground pin monitor.
NVM checks: CRC and U-PROG value. In case of error the state machine transits to DEEP-SLEEP where the device can be woken up to INIT state where safety checks are run again.

4.18 NVM integrity monitor

To detect an improper turn-OFF of NVM monitor feature, the device embeds an echo signal of the NVM monitor block enable signal: NVM_COMPARE_ENA_STATUS live bit in the status register. This status bit is set if a fault disables the comparison of NVM data with redundant registers, in such case an interrupt is sent to IRQ pin. The reaction of the NVM monitor features in case of error is described in the Section 4.8: HW low-level monitors. SPSB100 Protection, diagnosis and monitoring signals DS14640 - Rev 2 page 55/213

5 Serial peripheral interface (SPI)

A 32-bit SPI is used for bidirectional communication with the microcontroller. The microcontroller SPI peripheral shall be configured with CPOL = 0 and CPHA = 0: SDI input data is sampled by the rising CLK edge, and SDO output data is updated on the falling CLK edge. This device is not limited to microcontroller with a built-in SPI peripheral, instead three CMOS-compatible output pins and one input pin may be used to communicate with the device. A fault condition can be detected by setting CSN to low, in such condition the SDO pin reflects the global error flag GSBN of the device.

Chip select not (CSN) The CSN input pin is used to select the serial interface of this device. When CSN is high, the output pin SDO is in a high impedance state. CSN low activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame. If CSN is low for t > tCSNfail the SDO output will be switched back to high impedance not to block the signal line for other SPI nodes.
Serial data in (SDI) The SDI input pin is used to transfer data into the device. The data applied to SDI are sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register is transferred to the data input register. The writing to the selected data input register is enabled if exactly 32 bits are transmitted within one communication frame (that is, CSN low). If more or less clock pulses are counted within one frame the complete frame is ignored and a SPI error is signaled. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. Due to this safety functionality, a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.
Serial data out (SDO) The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag GSBN. The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out. As SDO is in high impedance when CSN is high, it is possible to link several SPI target devices that respect this rule with a dedicated CSN line for each SPI target.
Serial Clock (CLK) The CLK input is used to synchronize the input and output bit streams. The data input (SDI) is sampled at the rising edge of the CLK and the data output SDO is updated on the falling edge of the CLK signal.

5.1 ST-SPI

The ST-SPI is a standard used in ST automotive ASSP devices. This chapter describes the SPI protocol. It defines a common structure of the communication frames and defines specific addresses for product and status information. The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to adapt it to the individual functionality of a particular product. In addition, safety mechanisms are implemented to protect the communication from external influences and wrong or unwanted usage. SPSB100 Serial peripheral interface (SPI) DS14640 - Rev 2 page 56/213

5.1.1 Physical Layer

Figure 32. SPI pin description

5.2 Signal description

serial data out (SDO) is in high impedance when CSN is high or a communication timeout is detected. shifted out to serial data out (SDO).

5.2.1 Clock and data characteristics

CPOL = 0
CPHA = 0 SPSB100 Serial peripheral interface (SPI) DS14640 - Rev 2 page 57/213

Figure 33. SPI signal description The communication frame starts with the falling edge of the CSN (Communication Start). CLK has to be low. The SDI data is then latched at all following rising CLK edges into the internal shift registers. the SDO. At all following falling CLK edges data is shifted out through the internal shift registers to SDO. requested operation according to the operating code is performed.

5.2.2 Communication protocol

5.2.2.1 SDI frame

The devices data-in frame consists of 32 bits (OpCode (2 bits) + address (6 bits) + data (20 bits) + CRC (4 bits)). performed. The following 6 bits (MSB-2 to MSB-7) represent the address on which the operation is performed. The subsequent bytes contain the payload. Figure 34. SDI frame

5.2.2.2 Operation code

The operating code is used to distinguish among different access modes to the registers of the target device. Table 10. Operation codes of the same register is performed. SPI_CLK_CNT and a SPI_CRC_ERR will be set generating a SPIE. Communication start) of the same register is performed. communication (Selective bitwise clear).

5.2.2.3 Advanced operation code

A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address b’111111 is performed.

5.2.2.4 Data-in payload

follows the OpCode and the address bits. corresponding bit position the bit will be cleared.

5.2.2.5 SDO frame

The data-out frame consists of 32 bits (GSB + data bits + CRC). register at the time of the Communication start. These 8 bits are transmitted at every SPI transaction. into the shift register with the eighth positive CLK edge. a dedicated bit clear after.

Figure 35. SDO frame

5.2.2.6 Global status byte (GSB)

clear can be performed on these bits inside the GSB. Table 11. Global status byte

Global status bit not (GSBN) The GSBN is a logically NOR combination of bit 0 to bit 6. This bit can also be used as a global status flag without starting a complete communication frame as it is present directly after pulling CSN low. OUTHS open load can be masked in GSBN by setting bit MASK_OL_GSB. Global warning can be masked in GSBN by setting bit MASK_GW_GSB.
Reset bit (RSTB) The RSTB indicates a SPSB100 reset. In case this bit is set, all internal control and status registers are set to default. The RSTB bit is cleared after a read and clear of the VPOR bit in the status registers which caused the reset event.
SPI error (SPIE)
Functional error 1 (FE1) The FE1 is a logical OR combination of errors coming from functional blocks.
Device error (DE) The DE is a logical OR combination of errors related to device specific blocks.
Global warning (GW) The GW is a logical OR combination of warning flags (for example, thermal warning). Thermal warning can be masked in GW by setting bit MASK_TW_GW.
Fail-safe (FS) The FS bit indicates that the device was forced into a safe state due to mistreatment or critical internal errors (for example, watchdog failure, voltage regulator failure).

5.2.2.7 Data-out payload

communication to the controller device.

5.2.3 Address definition

Table 12. RAM and ROM address range Table 13. RAM address Table 14. ROM address

5.2.3.1 Device information registers

Table 15. Information registers map

5.2.3.1.1 Device identification registers

These registers represent a unique signature to identify the device and silicon version.

5.2.3.1.2 SPI modes

Table 16. SPI mode register

5.2.3.1.3 CRC

The CRC check is performed on the complete communication frame using the polynomial (X4 + X + 1). CRC is calculated on GSB + data -4 bit and the 4-bits result is saved in data LSB_3 to data LSB_0. Figure 36. CRC (cyclic redundancy check) calculation The CRC field is not inserted when device information is read in ROM registers.

5.2.3.2 Watchdog definition

For more details, refer to the Section 3.10: Configurable time-out window watchdog. The watchdog default settings can be read out via the device information registers. Table 17. WD Type/Timing

to LOW_SET(3-0) from user NVM. <WD Type 2> describes the default timing of the window watchdog. defines the typical open window time (tOW). See the Figure 37 with tCW = TEFW and tOW = TLFW - TEFW. Figure 37. Window watchdog operation The watchdog trigger bit location is defined by the <WD bit pos. X> registers. Table 18. WD bit position

5.2.3.3 Device application registers (RAM)

The device application registers are all registers accessible using OpCode ‘00’, ‘01’ and ‘10’.

6 Functional safety concept

IC’s capability to reach the required safety level, should be made at system level under the user's responsibility.

6.1 Safety requirements

operation as in the following tables based on MCU modes.

6.1.1 MCU in RUN mode

The following figure shows the MCU in RUN mode. Figure 38. PMIC + MCU in RUN mode Table 19. Safety requirement list while MCU is in RUN mode Output regulators are stopped, NRESET and NFSO pins are asserted. NFSO pins are asserted and SPSB100 reaches DEEP-SLEEP state. the MCU based on an error indication.

reset of the MCU in case of error. Output regulators are stopped, NRESET and NFSO pins are asserted. asserted and SPSB100 reaches DEEP-SLEEP state. destruction in case of runaway.

6.1.2 MCU in Smart-Power mode

The following figure shows MCU in Smart-Power mode. Figure 39. PMIC + MCU in Smart-Power mode

Table 20. Safety requirement list while MCU is in Smart-Power mode destruction in case of runaway.

6.1.3 MCU in Stand-by mode

The following figure shows MCU in Stand-by mode. Figure 40. PMIC + MCU in Stand-By mode

Table 21. Safety requirement list while MCU is in Stand-By mode destruction in case of runaway.

6.2 Safety mechanisms

7 Electrical characteristics

7.1 Supply monitoring

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 3 V < VS < 29 V, 6 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 22. Supply and supply monitoring

Electrical characteristics

DS14640 - Rev 2 page 69/213

Symbol Parameter Condition Min Typ Max Unit No load on regulator BUCK1,2_freq = 400 kHz IVS_LP1(1) Current consumption in active-low power mode VS = 13.5 V BUCK1 ON in LP BUCK1_REFRESH_FREQ = 1 BUCK2, 3 OFF LDO1, 2 OFF BUCK1 load = 5 mA VOUT_BUCK1 = 3.3 V BUCK1_freq = 400 kHz, IRQ and NFSO high - 2 3.2 mA IVS_LP2(1) Current consumption in active-low power mode VS = 13.5 V BUCK1 ON in LP BUCK1_REFRESH_FREQ = 1 BUCK2, 3 OFF LDO1, 2 OFF BUCK1 load = 50 µA VOUT_BUCK1 = 3.3 V WDC, OUT_HS, cyclic sense, cyclic wake up, no SPI communication BUCK2_freq = 400 kHz, IRQ and NFSO high - 300 600 µA IVS_DP(2)(3) Current consumption in DEEP-SLEEP mode VS = 13.5 V BUCK1, 2, 3 OFF LDO1, 2 OFF OUT_HS, cyclic sense, cyclic wake-up, NFSO high Ta = 0 °C to 85 °C - 20 40 µA IVS_DP_T(2)(3) Current consumption in DEEP-SLEEP mode VS = 13.5 V BUCK1, 2, 3 OFF LDO1, 2 OFF OUT_HS, cyclic sense, cyclic wake-up, NFSO high Full temperature range - - 55 µA IQCW Current consumption adder for cyclic wake-up VS = 13.5 V In active-low power mode or DEEP-SLEEP state - 60 90 µA IQCS Current consumption adder for cyclic sense VS = 13.5 V In active-low power mode or DEEP-SLEEP state Tperiod = 50 ms, tON = 100 µs - 60 90 µA IQOUT_HS(3) Additional bias quiescent current for switched ON OUT_HS VS = 13.5 V In active-low power mode or DEEP-SLEEP state No load - 140 220 µA IVS_BUCK2_LP(3) Additional bias quiescent current for BUCK2 in low power mode VS = 13.5 V BUCK2 ON in LP BUCK2_REFRESH_FREQ = 1 Vout = 5 V No load - 90 400 µA 1. Guaranteed by bench measurements. Performances verified in applicative conditions. 2. Current consumption in DEEP-SLEEP mode is calculated as IVS_DP + wake-up current consumption contributions. 3. Guaranteed by design.

7.2 Power ground loss monitoring

Table 23. Power ground loss monitoring

Digital implementation is guaranteed by scan test.

DS14640 - Rev 2 page 70/213

Ground loss protection parameter depends mainly on the implementation. This monitor measures a ground shift between GND and SGND pins.

7.3 Oscillator

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 24. Oscillator

7.4 Power-on reset

All outputs open; Tj = -40 °C to 150 °C, unless otherwise specified. Table 25. Power-on reset

This threshold is valid if VS had already reached VPORVS_R(max) previously.

7.5 LDO1 voltage regulator

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 26. LDO1

Digital implementation is guaranteed by scan test.
Nominal capacitor value required for stability of the regulator. Tested with 1 µF ceramic (± 20%). The capacitor must be

injection ) stress in the application. DS14640 - Rev 2 page 71/213

7.6 LDO2 voltage regulator

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. The same parameter values in both 5 V and 3.3 V conditions applies unless otherwise specified. Table 27. LDO2

Digital implementation is guaranteed by scan test.
Nominal capacitor value required for stability of the regulator. Tested with 1 µF ceramic (±20%). The capacitor must be

injection) stress in the application.

7.7 Boost controller

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 3 V ≤ VS ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 28. Boost controller DS14640 - Rev 2 page 72/213

Symbol Parameter Condition Min Typ Max Unit VFBB_REG2 VFBB regulation threshold If BUCK1 or BUCK2 voltage settings Fsw_BOOST Switching frequency Guaranteed by scan 320 400 480 kHz Boost_DC_Max(1) Boost duty cycle max

0 V < VS < VS_LOW

tON = 63 cycles of 33.6 MHz main clk 34 75 83 % Boost_DC_High(1) Boost duty cycle high VS_LOW < VS < VS_MID tON = 55 cycles of 33.6 MHz main clk 30 65.5 73 % Boost_DC_Low(1) Boost duty cycle low VS_MID < VS < VS_HIGH tON = 46 cycles of 33.6 MHz main clk 25 54.8 61 % Boost_DC_Min(1) Boost duty cycle min VS_HIGH < VS tON = 38 cycles of 33.6 MHz main clk 21 45.2 50 % Boost_DC_LP(1) Boost duty cycle in low power mode VS_HIGH < VS tON = 2 cycles of 800 kHz 27 50.0 66 % VS_Low_R VS comparator threshold VS_LOW Rising 4.25 4.5 4.75 V VS_Low_F VS comparator threshold VS_LOW Falling 3.75 4.0 4.25 V VS_Low_HYS VS comparator threshold VS_LOW Hysteresis 0.4 0.5 0.6 V VS_Mid_R VS comparator threshold VS_MID Rising 5.7 6.0 6.3 V VS_Mid_F VS comparator threshold VS_MID Falling 5.2 5.5 5.8 V VS_Mid_HYS VS comparator threshold VS_MID Hysteresis 0.4 0.5 0.6 V VS_High_R VS comparator threshold VS_HIGH Rising 7.1 7.5 7.9 V VS_High_F VS comparator threshold VS_HIGH Falling 6.6 7 7.4 V VS_High_HYS VS comparator threshold VS_HIGH Hysteresis 0.4 0.5 0.6 V VBoost_rip(2) Boost voltage_ripple Ripple at 20 kHz All characteristics of all blocks supplied by FBB are guaranteed with external components defined in the Table 50 - - 2.5 Vpp IBoost(2) Boost current capability Guaranteed with external components defined in the Table 50 0.05 - 4.2 A IBoost_LS_sink1 LS driver sink current VFBB = VGLB = 8.5 V 70 100 130 mA IBoost_HS_source1 HS driver source current VFBB = 8.5 V VGLB = 0 V 70 100 130 mA IBoost_LS_sink2 LS driver sink current VFBB = 8.5 V VGLB = 0.5 V 20 35 55 mA SPSB100 DS14640 - Rev 2 page 73/213

Symbol Parameter Condition Min Typ Max Unit IBoost_HS_source2 HS driver source current VFBB = 8.5 V VGLB = 8 V 10 25 45 mA RBoost_gate_pulldown Resistive gate pull-down BOOST_DIS = 1 3 5 8 kΩ IVS__stdby Current leakage on VS pin in stdby - - 2 μA IVS_Sense Sink current on VS active mode 120 180 250 μA VBOOST_VDSM1 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 000 220 250 280 mV VBOOST_VDSM2 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 001 420 450 480 mV VBOOST_VDSM3 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 010 610 650 680 mV VBOOST_VDSM4 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 011 800 850 900 mV VBOOST_VDSM5 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 100 1.04 1.1 1.16 V VBOOST_VDSM6 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 101 1.24 1.3 1.36 V VBOOST_VDSM7 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 110 1.35 1.5 1.65 V VBOOST_VDSM8 Boost drain-source rising threshold voltage BOOST_DSMON_TH = 111 1.53 1.7 1.87 V VBOOST_VDSM_HYS_H Boost drain-source threshold voltage hysteresis for high VDSM codes BOOST_DSMON_TH = 1xx 75 100 125 mV VBOOST_VDSM_HYS_L Boost drain-source threshold voltage hysteresis for low VDSM codes BOOST_DSMON_TH = 0xx 25 50 75 mV VTH_BYPASS_R1 Bypass external MOSFET enable comparator rising threshold, rising VVS If BUCK1 and BUCK2 voltage settings are = 3.3 V 8.65 9 9.35 V VTH_BYPASS_F1 Bypass external MOSFET disable comparator falling threshold, rising VVS If BUCK1 and BUCK2 voltage settings are = 3.3 V 8.4 8.75 9.1 V VTH_BYPASS_R2 Bypass external MOSFET enable comparator rising threshold, rising VVS If BUCK1 or BUCK2 voltage settings VTH_BYPASS_F2 Bypass external MOSFET disable comparator falling threshold, rising VVS If BUCK1 or BUCK2 voltage settings TF_BYPASS_EN(1) digital filter time on bypass external MOSFET enable comparator output 12 15 22 µs TF_BYPASS_DIS(1) digital filter time on bypass external MOSFET disable comparator output 0 0.24 0.4 µs VBYPASS_VDSM1 Bypass drain-source rising threshold voltage BYPASS_DSMON_TH = 000 75 125 175 mV VBYPASS_VDSM2 Bypass drain-source rising threshold voltage BYPASS _DSMON_TH = 001 125 165 225 mV VBYPASS_VDSM3 Bypass drain-source rising threshold voltage BYPASS _DSMON_TH = 010 175 225 275 mV SPSB100 DS14640 - Rev 2 page 74/213

Symbol Parameter Condition Min Typ Max Unit VBYPASS_VDSM4 Bypass drain-source rising threshold voltage BYPASS _DSMON_TH =011 225 275 325 mV VBYPASS_VDSM5 Bypass drain-source rising threshold voltage BYPASS _DSMON_TH = 100 275 325 375 mV VBYPASS_VDSM6 Bypass drain-source rising threshold voltage BYPASS _DSMON_TH =101 325 375 425 mV VBYPASS_VDSM7 Bypass drain-source rising threshold voltage BYPASS _DSMON_TH = 110 375 425 475 mV VBYPASS_VDSM8 Bypass drain-source rising threshold voltage BYPASS _DSMON_TH = 111 425 475 525 mV VBYPASS_VDSM_HYS Bypass drain-source threshold voltage hysteresis BYPASS_DSMON_TH = xxx 25 50 75 mV TF_BYPASS_VDSM(1) Digital filter time on bypass drain-source threshold 12 15 22 µs TB_BYPASS_VDSM(1) Blanking time on bypass drain- source comparator 90 110 142 µs Rbypass_gate_discharge Bypass gate discharge resistor FBB - GBY = 2 V FBB = 7 and GBY = 5 turn OFF 100 220 600 Ω Ibypass_gate_charge Bypass gate charge current GBY = 5 V FBB = 13.5 V 0.4 1.2 2 mA 1. Digital implementation is guaranteed by scan test. 2. Guaranteed by design.

7.8 BUCK1 converter

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 8.5 V ≤ VIN12 ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 29. BUCK1 converter DS14640 - Rev 2 page 75/213

Symbol Parameter Condition Min Typ Max Unit Vout_PG_buck1 Output power-good threshold monitor range 88 92 96 % Vout_OV_buck1_err Output overvoltage threshold monitor range 103 107 111 % tbuck1_PG_TO(2) Output power-good time-out 4.8 6 7.5 ms tbuck1_UV_TO(2) Vout undervoltage time-out filter 25 30 41 µs tbuck1_OV_TO (2) Vout overvoltage time-out filter 25 30 41 µs RDSON_HS_buck1_25(3) HS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 25 °C - 0.095 0.12 Ω RDSON_HS_buck1_130 HS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 130 °C - - 0.165 Ω RDSON_LS_buck1_25 LS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 25 °C - 0.095 0.12 Ω RDSON_LS_buck1_130 LS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 130 °C - - 0.165 Ω Ilimit_buck1_000 Peak switching current limit at VIN12 = 14 V BUCK1_IPEAK = 000 1.7 2 2.3 A Ilimit_buck1_001 Peak switching current limit at VIN12 = 14 V BUCK1_IPEAK = 001 2.125 2.5 2.875 A Ilimit_buck1_010 Peak switching current limit at VIN12 = 14 V BUCK1_IPEAK = 010 2.55 3 3.45 A Ilimit_buck1_011 Peak switching current limit at VIN12 = 14 V BUCK1_IPEAK = 011 2.975 3.5 4.025 A Ilimit_buck1_100 Peak switching current limit at VIN12 = 14 V BUCK1_IPEAK = 100 3.2 4 4.6 A Ilimit_buck1_101 Peak switching current limit at VIN12 = 14 V BUCK1_IPEAK = 101 3.5 4.5 5.175 A Ilimit_buck1_11X Peak switching current limit at VIN12 = 14 V BUCK1_IPEAK = 11X 3.75 5 5.75 A tbuck1_OC_TO(2) Over current filter time 125 150 200 µs Tsoftstart_buck1_00(3) Soft start time slope when start-up BUCK1_SS_VALUE = 00 9.9 16.5 23.1 V/ms Tsoftstart_buck1_01(3) Soft start time slope when start-up BUCK1_SS_VALUE = 01 4.95 8.25 11.9 V/ms Tsoftstart_buck1_10(3) Soft start time slope when start-up BUCK1_SS_VALUE = 10 1.98 3.3 4.62 V/ms Tsoftstart_buck1_11(3) Soft start time slope when start-up BUCK1_SS_VALUE = 11 0.99 1.65 2.31 V/ms Fsw_buck1_0 Switching frequency BUCK1_FREQ = 0 2.0 2.4 2.8 MHz Fsw_buck1_1 Switching frequency BUCK1_FREQ = 1 333 400 470 kHz Fspread_buck1_24(3) Spread spectrum range (Enable/ disable by BUCK1_SPREAD_ENA) Fsw_buck1 = 2.4 MHz -8 - +8 % Fspread_buck1_04(3) Spread spectrum range (enable/ disable by BUCK1_SPREAD_ENA) Fsw_buck1 = 400 kHz -20 - +20 % RPD_OFF_buck1 Pull-down resistor in off Vout = 3.3 V 60 75 90 Ω Ibuck1_LP Output current in low power mode VIN12 = 14 V - - 100 mA Vbuck1_LP_00 Output voltage in low power mode BUCK1_PU_VALUE = 00 Line/load transients not included 3.08 3.3 3.51 V SPSB100 DS14640 - Rev 2 page 76/213

Symbol Parameter Condition Min Typ Max Unit Ripple included VIN12 = 8.5 V to 16 V Iload = 50 μA to IBuck1_LP Vbuck1_LP_01 Output voltage in low power mode BUCK1_PU_VALUE = 01 Line/load transients not included Ripple included VIN12 = 8.5 V to 16 V Iload = 50 μA to IBuck1_LP 4.75 5 5.25 V Vbuck1_LP_1X Output voltage in low power mode BUCK1_PU_VALUE = 1x Line/load transients not included Ripple included VIN12 = 8.5 V to 16 V Iload = 50 μA to IBuck1_LP 6.22 6.5 6.78 V Isw_limit_buck1_LP Peak current limit in LP mode 750 1000 1250 mA Vout_UV_buck1_LP_33 Output undervoltage threshold monitor in LP mode Vout = 3.3 V 2.8 2.9 3.05 V Vout_UV_buck1_LP_5 Output undervoltage threshold monitor in LP mode Vout = 5 V 4.15 4.35 4.65 V Vout_UV_buck1_LP_65 Output undervoltage threshold monitor in LP mode Vout = 6.5 V 5.45 5.65 5.85 V Vout_OV_ buck1_LP_33 Output overvoltage threshold monitor in LP mode Vout = 3.3 V 3.55 3.7 3.8 V Vout_OV_buck1_LP_5 Output overvoltage threshold monitor in LP mode Vout = 5 V 5.4 5.65 5.85 V Vout_OV_buck1_LP_65 Output overvoltage threshold monitor in LP mode Vout = 6.5 V 6.9 7.2 7.5 V RDSON_HS_buck1_LP_25 HS switch ON resistance at 0.1 A VIN12 = 14 V Tj = 25 °C - 0.72 0.9 Ω RDSON_HS_buck1_LP_130 HS switch ON resistance at 0.1 A VIN12 = 14 V Tj = 130 °C - - 1.3 Ω RDSON_LS_buck1_LP_25 LS switch ON resistance at 0.1 A VIN12 = 14 V Tj = 25 °C - 0.2 0.3 Ω RDSON_LS_buck1_LP_130 LS switch ON resistance at 0.1 A VIN12 = 14 V Tj = 130 °C - - 0.4 Ω 1. Guaranteed by bench measurements. Performances verified in applicative conditions. Tested in static load conditions (Iload = 150 mA at 400 kHz and 2.4 MHz). 2. Digital implementation is guaranteed by scan test. 3. Guaranteed by design.

7.9 BUCK2 converter

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 8.5 V ≤ VIN12 ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. BUCK2 shares the same input as BUCK1. Table 30. BUCK2 converter DS14640 - Rev 2 page 77/213

Symbol Parameter Condition Min Typ Max Unit VIN12_L Input voltage range Vout_buck2 = 3.3 V 6 14 29 V Vout_buck2_33(1) Output voltage BUCK2_PU_VALUE = 00 Transients and ripple not included VIN12 = 8.5 V to 16 V Iload = 50 mA to 1.5 A Freq. = 400 kHz 3.23 3.3 3.399 V Vout_buck2_5(1) Output voltage BUCK2_PU_VALUE = 01 Transients and ripple not included VIN12 = 8.5 V to 16 V Iload = 50 mA to 1.5 A Freq. = 400 kHz 4.9 5 5.15 V Vout_buck2_65(1) Output voltage BUCK2_PU_VALUE = 1x Transients and ripple not included VIN12 = 8.5 V to 16 V Iload = 50 mA to 1.5 A Freq. = 400 kHz 6.37 6.5 6.695 V Vout_UV_buck2_err Output undervoltage threshold monitor range 86 90 94 % Vout_PG_buck2 Output power-good threshold monitor range 88 92 96 % Vout_OV_ buck2_err Output overvoltage threshold monitor range 103 107 111 % tbuck2_PG_TO(2) Output power-good time-out 4.8 6 7.5 ms tbuck2_UV_TO(2) Vout undervoltage time-out filter 25 30 41 µs tbuck2_OV_TO(2) Vout overvoltage time-out filter 25 30 41 µs RDSON_HS_buck2_25 HS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 25 °C - 0.095 0.12 Ω RDSON_HS_buck2_130 HS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 130 °C - - 0.165 Ω RDSON_LS_buck2_25 LS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 25 °C - 0.095 0.12 Ω RDSON_LS_buck2_130 LS switch ON resistance at 1.5 A VIN12 = 14 V Tj = 130 °C - - 0.165 Ω Ilimit_buck2_000 Peak switching current limit at VIN12 = 14 V BUCK2_IPEAK = 000 1.7 2 2.3 A Ilimit_buck2_001 Peak switching current limit at VIN12 = 14 V BUCK2_IPEAK = 001 2.125 2.5 2.875 A Ilimit_buck2_010 Peak switching current limit at VIN12 = 14 V BUCK2_IPEAK = 010 2.55 3 3.45 A Ilimit_buck2_011 Peak switching current limit at VIN12 = 14 V BUCK2_IPEAK = 011 2.975 3.5 4.025 A Ilimit_buck2_100 Peak switching current limit at VIN12 = 14 V BUCK2_IPEAK = 100 3.2 4 4.6 A Ilimit_buck2_101 Peak switching current limit at VIN12 = 14 V BUCK2_IPEAK = 101 3.5 4.5 5.175 A Ilimit_buck2_11x Peak switching current limit at VIN12 = 14 V BUCK2_IPEAK = 11x 3.75 5 5.75 A tbuck2_OC_TO(2) Over current filter time 125 150 200 µs SPSB100 DS14640 - Rev 2 page 78/213

Symbol Parameter Condition Min Typ Max Unit Tsoftstart_buck2_00(3) Soft start time slope when start-up BUCK2_SS_VALUE = 00 9.9 16.5 23.1 V/ms Tsoftstart_buck2_01(3) Soft start time slope when start-up BUCK2_SS_VALUE = 01 4.95 8.25 11.9 V/ms Tsoftstart_buck2_10(3) Soft start time slope when start-up BUCK2_SS_VALUE = 10 1.98 3.3 4.62 V/ms Tsoftstart_buck2_11(3) Soft start time slope when start-up BUCK2_SS_VALUE = 11 0.99 1.65 2.31 V/ms Fsw_buck2_0 Switching frequency BUCK2_FREQ = 0 2.0 2.4 2.8 MHz Fsw_buck2_1 Switching frequency BUCK2_FREQ = 1 333 400 470 kHz Fspread_buck2_24(3) Spread spectrum range (enable/ disable by BUCK2_SPREAD_ENA) Fsw_buck2 = 2.4 MHz -8 - +8 % Fspread_buck2_04(3) Spread spectrum range (enable/ disable by BUCK2_SPREAD_ENA) Fsw_buck2 = 400 kHz -20 - +20 % PHI_buck2(3)(2) Phase shift to BUCK1 - 225 - deg RPD_OFF_buck2 Pull-down resistor in off Vout = 3.3 V 60 75 90 Ω Ibuck2_LP Output current in low power mode VIN12 = 14 V - - 100 mA Vbuck2_LP_00 Output voltage in low power mode BUCK2_PU_VALUE = 00 Line/load transients not included Ripple included VIN12 = 8.5 V to 16 V Iload = 50 μA to IBuck2_LP 3.08 3.3 3.51 V Vbuck2_LP_01 Output voltage in low power mode BUCK2_PU_VALUE = 01 Line/load transients not included Ripple included VIN12 = 8.5 V to 16 V Iload = 50 μA to IBuck2_LP 4.75 5 5.25 V Vbuck2_LP_1X Output voltage in low power mode BUCK2_PU_VALUE = 1x Line/load transients not included Ripple included VIN12 = 8.5 V to 16 V Iload = 50 μA to IBuck2_LP 6.22 6.5 6.78 V Isw_limit_buck2_LP Peak current limit in LP mode 750 1000 1250 mA Vout_UV_buck2_LP_33 Output undervoltage threshold monitor in LP mode Vout = 3.3 V 2.8 2.9 3.05 V Vout_UV_buck2_LP_5 Output undervoltage threshold monitor in LP mode Vout = 5 V 4.15 4.35 4.65 V Vout_UV_buck2_LP_65 Output undervoltage threshold monitor in LP mode Vout = 6.5 V 5.45 5.65 5.85 V Vout_OV_buck2_LP_33 Output overvoltage threshold monitor in LP mode Vout = 3.3 V 3.55 3.7 3.8 V Vout_OV_buck2_LP_5 Output overvoltage threshold monitor in LP mode Vout = 5 V 5.4 5.65 5.85 V Vout_OV_buck2_LP_65 Output overvoltage threshold monitor in LP mode Vout = 6.5 V 6.9 7.2 7.5 V RDSON_HS_buck2_LP_25 HS switch ON resistance at 0.1 A VIN12 = 14 V Tj = 25 °C - 0.72 0.9 Ω RDSON_HS_buck2_LP_130 HS switch ON resistance at 0.1 A VIN12 = 14 V Tj = 130 °C - - 1.3 Ω RDSON_LS_buck2_LP_25 LS switch ON resistance at 0.1 A VIN12 = 14 V Tj = 25 °C - 0.25 0.3 Ω SPSB100 DS14640 - Rev 2 page 79/213

Figure 54. Current limitation curves of BUCK1, 2 for Vout 6.5 V

7.10 BUCK3 converter

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 3 V ≤ VIN13 ≤ 7 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 31. BUCK3 converter DS14640 - Rev 2 page 86/213

Symbol Parameter Condition Min Typ Max Unit Iload = 50 mA to 3 A Vout_buck3_011(1)(2) Output voltage BUCK3_PU_VALUE = 001 BUCK3_FTUNE = 011 VIN3 = 3 V to 5.5 V Iload = 50 mA to 3 A 0.9797 1.01 1.0403 V Vout_buck3_1V1(1)(2) Output voltage BUCK3_PU_VALUE = 010 VIN3 = 3 V to 5.5 V Iload = 50 mA to 3 A 1.056 1.1 1.144 V Vout_buck3_1V2(1)(2) Output voltage BUCK3_PU_VALUE = 011 VIN3 = 3 V to 5.5 V Iload = 50 mA to 3 A 1.152 1.2 1.248 V Vout_buck3_1V25(1)(2) Output voltage BUCK3_PU_VALUE = 100 VIN3 = 3 V to 5.5 V Iload = 50 mA to 3 A 1.2 1.25 1.3 V Vout_buck3_3V3(1)(2) Output voltage BUCK3_PU_VALUE = 101 or 11x VIN3 = 4.8 V to 7.0 V Iload = 50 mA to 3 A 3.168 3.3 3.432 V Vout_UV_buck3 Output undervoltage threshold monitor range For all BUCK3_PU_VALUE except 001 85 90 95 % Vout_PG_buck3 Output power-good threshold monitor range 87 92 96 % Vout_OV_buck3 Output overvoltage threshold monitor range For all BUCK3_PU_VALUE except 001 104 107.5 111 % Vout_UV_buck3 Output undervoltage threshold monitor range for fine-tune BUCK3_PU_VALUE = 001 0.8 - 0.9 V Vout_PG_buck3_FT Output power-good threshold monitor range for fine-tune BUCK3_PU_VALUE = 001 0.82 - 0.92 V Vout_OV_buck3_FT Output overvoltage threshold monitor range for fine-tune BUCK3_PU_VALUE = 001 1.04 - 1.125 V tbuck3_PG_TO(3) Output power-good timeout 4.8 6 7.5 ms tbuck3_UV_TO(3) Vout undervoltage time-out filter 25 30 41 µs tbuck3_OV_TO(3) Vout overvoltage time-out filter 25 30 41 µs RDSON_HS_buck3_25 HS switch ON resistance at 3 A VIN3 = 5 V TJ = 25 °C - 0.04 0.08 Ω RDSON_HS_buck3_130 HS switch ON resistance at 3 A VIN3 = 5 V TJ = 130 °C - - 0.1 Ω RDSON_LS_buck3_25 LS switch ON resistance at 3 A VIN3 = 5 V TJ = 25 °C - 0.04 0.08 Ω RDSON_LS_buck3_130 VIN3 = 5 V TJ = 130 °C - - 0.1 Ω Ilimit_buck3_00 Peak switching current limit BUCK3_IPEAK = 00 3.4 4 4.6 A Ilimit_buck3_01 Peak switching current limit BUCK3_IPEAK = 01 4.25 5 5.75 A Ilimit_buck3_10 Peak switching current limit BUCK3_IPEAK = 10 5.1 6 6.9 A Ilimit_buck3_11 Peak switching current limit BUCK3_IPEAK = 11 5.95 7 8.05 A tbuck3_OC_TO(3) Over current filter time 125 150 200 µs SPSB100 DS14640 - Rev 2 page 87/213

Figure 63. Line transient BUCK3 at 3.3 V Note: Iload = 3 A, line voltage: 4.75 V to 7 V at 30 V/ms.

7.11 Watchdog

6.0 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. All watchdog timings are covered by scan. Table 32. Watchdog DS14640 - Rev 2 page 91/213

Symbol Parameter Condition Min Typ Max Unit TEFW4 Early failure window 4 WD_TIME = 0011 - - 31.5 ms TLFW4 Late failure window 4 WD_TIME = 0011 90 - - ms TSW4 Safe window 4 WD_TIME = 0011 50.4 - 56.8 ms TEFW5 Early failure window 5 WD_TIME = 0100 - - 96.2 ms TLFW5 Late failure window 5 WD_TIME = 0100 250 - - ms TSW5 Safe window 5 WD_TIME = 0100 151.1 - 159.3 ms TEFW6 Early failure window 6 WD_TIME = 0101 - - 197.1 ms TLFW6 Late failure window 6 WD_TIME = 0101 500 - - ms TSW6 Safe window 6 WD_TIME = 0101 308.4 - 319.3 ms TEFW7 Early failure window 7 WD_TIME = 0110 - - 299.6 ms TLFW7 Late failure window 7 WD_TIME = 0110 750 - - ms TSW7 Safe window 7 WD_TIME = 0110 468.1 - 479.4 ms TEFW8 Early failure window 8 WD_TIME = 0111 - - 402.1 ms TLFW8 Late failure window 8 WD_TIME = 0111 1000 - - ms TSW8 Safe window 8 WD_TIME = 0111 627.8 - 638.7 ms TEFW9 Early failure window 9 WD_TIME = 1000 - - 630.8 ms TLFW9 Late failure window 9 WD_TIME = 1000 1600 - - ms TSW9 Safe window 9 WD_TIME = 1000 984 - 1025.1 ms TEFW10 Early failure window 10 WD_TIME = 1001-1111 - - 3.2 ms TLFW10 Late failure window 10 WD_TIME = 1001-1111 78 - - ms TSW10 Safe window 10 WD_TIME = 1001-1111 5 - 50 ms SPSB100 DS14640 - Rev 2 page 92/213

Figure 64. Watchdog early, late and safe windows DS14640 - Rev 2 page 93/213

Figure 65. Watchdog timing

7.12 High side output OUT_HS

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6.0 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 33. High side output OUT_HS DS14640 - Rev 2 page 94/213

Symbol Parameter Condition Min Typ Max Unit IOC_OUT_HS Overcurrent threshold VFBB = 13.5 V 25 33 40 mA tOC_OUT_HS(1) Overcurrent filter time 16 28 40 µs tBLK_OC_OUT_HS(1) Blanking time of overcurrent In case of short at enable (to be added to filter time for the minimum tON) 32 46 60 µs IOLD_OUT_HS Open load detection current VFBB = 13.5 V 0.25 0.7 1.2 mA tOLD_OUT_HS(1) Open load detection time 45 70 95 µs dVOUT_HS/dt Slew rate VFBB = 13.5 V Rload = 620 Ω Cload = 47 nF from 20% to 80% 0.05 0.8 2 V/µs tDON_OUT_HS Switch ON delay time VFBB = 13.5 V (from CSN rising 50% to OUT 80%) Rload = 620 Ω Cload = 47 nF 5 20 40 µs tDOFF_OUT_HS Switch OFF delay time VFBB = 13.5 V (from CSN rising 50% to OUT 20%) Rload = 620 Ω Cload = 47 nF 10 60 100 µs IQLH_OUT_HS_LP Switched-off output Current in low power VOUT_HS = 0 V Active low power or DEEP-SLEEP modes -5 - - µA IQLH_OUT_HS_FP Switched-off output Current in full power VOUT_HS = 0 V Active full power mode -10 - - µA 1. Digital implementation is guaranteed by scan test.

7.13 NFSO1 fail safe output

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6.0 V ≤ VFBB ≤ 40 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 34. Low side outputs

7.14 Wake up inputs (WU, IGN)

Symbol Parameter Condition Min Typ Max Unit Vthp max = VFBB * 0.5 Value for VFBB = 14 V VIGNthp Wake-up negative edge threshold voltage Vthp min = VFBB * 0.4 Vthp typ = VFBB * 0.45 Vthp max = VFBB * 0.5 Value for VFBB = 14 V 5.6 6.3 7 V VWUthn Wake-up positive edge threshold voltage Vthp min = VFBB * 0.5 Vthp typ = VFBB * 0.55 Vthp max = VFBB * 0.6 Value for VFBB = 14 V 7 7.7 8.4 V VIGNthn Wake-up positive edge threshold voltage Vthp min = VFBB * 0.5 Vthp typ = VFBB * 0.55 Vthp max = VFBB * 0.6 Value for VFBB = 14 V 7 7.7 8.4 V VHYST_WU Hysteresis Vthp min = VFBB * 0.05 Vthp typ = VFBB * 0.1 Vthp max = VFBB * 0.15 Value for VFBB = 14 V 0.7 1.4 2.1 V VHYST_IGN Hysteresis Vthp min = VFBB * 0.05 Vthp typ = VFBB * 0.1 Vthp max = VFBB * 0.15 Value for VFBB = 14 V 0.7 1.4 2.1 V tWU_stat(1) Static wake filter time 50 64 85 µs tIGN_stat(1) Static wake filter time 50 64 85 µs IWU_stdby Input current in DEEP-SLEEP or active low power mode VWU < 1 V or VWU > (VFBB - 1.5 V) WU_ENA = 0 - - 3 μA IIGN_stdby Input current in DEEP-SLEEP or active low power mode VIGN < 1 V or VIGN > (VFBB - 1.5 V) IGN_ENA = 0 - - 3 μA IWU_stdby_PD Pull-down current in DEEP-SLEEP or active low power modes VWU < 1 V or VWU > (VS - 1.5 V) WU_ENA = 1 5 20 60 μA IWU_stdby_PU Pull-up current in DEEP-SLEEP or active low power modes VWU < 1 V or VWU > (VS - 1.5 V) WU_ENA = 1 -60 -20 -5 μA IIGN_stdby_PD Pull-down current in DEEP-SLEEP or active low power modes VIGN < 1 V or VIGN > (VS - 1.5 V) IGN_ENA = 1 5 20 60 μA IIGN_stdby_PU Pull-up current in DEEP-SLEEP or active low power modes VWU < 1 V or VWU > (VS - 1.5 V) WU_ENA = 1 -60 -20 -5 μA RWU_act Input resistor to GND in active mode and in DEEP-SLEEP or active low power mode during wake-up input sensing 80 180 300 kΩ RIGN_act Input resistor to GND in active mode and in DEEP-SLEEP or active low power mode during wake-up input sensing 80 180 300 kΩ tWU_cyc(1) Cyclic wake filter time 12 16 29 µs tIGN_cyc(1) Cyclic wake filter time 12 16 29 µs SPSB100 DS14640 - Rev 2 page 96/213

Digital implementation is guaranteed by scan test.

7.15 SPI

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 3 V ≤ VIO ≤ 5.4 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 36. Input: CSN

The value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 37. Inputs: CLK, SDI

The value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 38. SDI, CLK and CSN timing DS14640 - Rev 2 page 97/213

Symbol Parameter Condition Min Typ Max Unit tf_in(1) Fall time of input signal SDI, CLK, CSN - 25 ns 1. Guaranteed by design. Table 39. Output: SDO

0 V < VSDO < VIO

Table 40. SDO timing Table 41. CSN timing DS14640 - Rev 2 page 98/213

Figure 68. SPI - Output timing DS14640 - Rev 2 page 100/213

Figure 69. SPI CSN - Output timing Figure 70. SPI - CSN low to high transition and global status bit access

7.16 SWDBG input

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 3 V ≤ VFBB ≤ 20 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 42. SWDBG input DS14640 - Rev 2 page 101/213

Symbol Parameter Condition Min Typ Max Unit VSWDBG_L Input voltage low threshold 1.0 - - V VSWDBG_H Input voltage high threshold for WDC disable - - 2.3 V VSWDBG_HYS Input hysteresis 0.2 - - V tSWDBG_TO(1) Software-debug timeout 8.3 10 12.6 s RSWDBG_PD Pull-down resistor VSWDBG = 6 to 20 V 13 29 55 kΩ VNVM_EMU_L Input low threshold for NVM emulation exit 6.1 - - V VNVM_EMU_H Input voltage high threshold for transition to NVM emulation - - 9.4 V VNVM_EMU_HYS Input hysteresis for NVM emulation 0.3 - - V CSWDBG(2) SWDBG input capacitance - - 15 pF 1. Digital implementation is guaranteed by scan test. 2. Guaranteed by design.

7.17 ADC characteristics

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6.0 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 43. ADC characteristics

7.18 IRQ interrupt

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 3.0 V ≤ VIO ≤ 5.5 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 44. Interrupt output DS14640 - Rev 2 page 102/213

Symbol Parameter Condition Min Typ Max Unit IIRQ_LK Leakage current VIRQ = 20 V VIO = 3.3 V - - 100 μA IIRQ_LK_5V Leakage current when IRQ is disabled VIRQ = 5.0 V VIO = 5.0 V - - 1 μA RIRQ_PU IRQ internal pull-up resistor for echo VIRQ = 1 V 13 29 55 kΩ tIRQ_react(1) Interrupt reaction time - - 40 µs tIRQ_ECHO_FILT IRQ echo error filter time 91 100 150 µs 1. Guaranteed by scan.

7.19 FIN1 input

7.20 Timer

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6.0 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. All timer timings are covered by scan. Table 46. Timer values DS14640 - Rev 2 page 103/213

Symbol Parameter Condition Min Typ Max Unit T3 Timer period T1_PER = 010 41.6 50 62.5 ms T4 Timer period T1_PER = 011 83 100 125 ms T5 Timer period T1_PER = 100 166 200 250 ms T6 Timer period T1_PER = 101 416 500 625 ms T7 Timer period T1_PER = 110 830 1000 1250 ms T8 Timer period T1_PER = 110 1660 2000 2500 ms

7.21 Reset output (NRST)

7.22 VREG voltage regulator

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 7.5 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 48. VREG DS14640 - Rev 2 page 104/213

Symbol Parameter Condition Min Typ Max Unit tVREG_UV(1) VREG undervoltage filter time 12 15 22 μs tVREG_stup(1) VREG max start-up delay time for power-good 1.6 2 2.51 ms IVREG_CCmax Short circuit output current (to GND) Current limitation in active-full power 125 260 380 mA CVREG(2) Load capacitor Ceramic 3 4.7 10 µF 1. Digital implementation guaranteed by scan test. 2. Nominal capacitor value required for stability of the regulator. Tested with 4.7 µF ceramic (±20%). The capacitor must be located close to the regulator output pin.

7.23 BIST timing

8 Application circuit

Figure 71. Typical application circuit

8.1 External components

Table 50. External components (referred to pictures in the related sections)

Component Block/Usage Min Typ Max Unit Note X7S SMD Choice: GCJ32EC71H106KA01 C_Boost_ALU(1) Option ALU capacitance at FBB 0 100 150 μF ESR: < 30 mΩ Capacitance change or temperature coefficient: < | 32%| Rated voltage: > 40 VDC AL ELEC CAP SMD Choice: GYC1H101MCQ1GS Q1_Boost - - - - - RDS(ON): < 10 mΩ V(BR)DSS: > 40 V VGS: ±20 V ID (continuous): > 20 A ID (pulse): > 40 A VGS_TH: < 3 V Choice: STL105N4LF7AG D1_Boost D2_Boost - - - - - Schottky IF(AV): > 25 A VRRM: > 40 V VF(max): < 0.7 V Choice: STPS3045DJF L_Boost BOOST inductance 0.8 1 1.2 μH DCR: < 10 mΩ Isat: > 20 A Derating < 40% Choice: IHLP-4040DZ-11 Rpr Resistor for VS pin protection 0.95 1 1.05 K Ω - Rg Serial gate resistor of Q1_BOOST 2.09 2.2 2.31 Ω - Rg_pd Pull-down resistor of Q1_BOOST gate 142.5 150 157.5 kΩ - Q2_Bypass - - - - –- RDS(ON): < 10 mΩ V(BR)DSS: > 40 V VGS: ±20 V ID (continuous): > 20 A ID (pulse): > 40 A VGS_TH: < 3 V Choice: STD45P4LLF6AG DZby Zener diode to clamp VGS of Q2 bypass - - - - Voltage clamp = 18 V Choice: SM4T18AY Rcl Discharge resistor to short VGS of Q2 bypass in OFF STATE 20.9 22 23.1 KΩ - C_Buck1_24(1) C_Buck2_24(1) C_Buck3(1) Output capacitor at 2.4 MHz T = 27 °C Vout_buck1 = 3.3 V 17 22 27 µF ESR: < 15 mΩ Rated voltage: > 10 VDC X7R [±15% temperature characteristics] SMD Choice: CGA6P1X7R1C226M250AC L_Buck1_24 L_Buck2_24 Output inductor at 2.4 MHz Iout = 3 A 2.2 3.3 4 µH Rdc: < 25 mΩ Isat > 8 A SRF > 15 MHz SMD Choice: XAL6030-332ME SPSB100 Application circuit DS14640 - Rev 2 page 107/213

Component Block/Usage Min Typ Max Unit Note Cbst_Buck1(1) Cbst_Buck2(1) Bootstrap capacitor 37.6 47 56.4 nF - Cbst_Buck3(1) Bootstrap capacitor 80 100 120 nF - L_Buck3 Output inductor Iout = 6 A 2.2 3.3 4 µH Rdc: < 15 mΩ Isat > 10 A SRF > 15 MHz SMD Choice: SPM10040T-3R3M-HZ Cc_Buck1_24(1) Cc_Buck2_24(1) F = 2.4 MHz 1.2 1.5 1.8 nF - Cc_Buck3(1) - 3.76 4.7 5.64 nF - Rc_Buck1_24 Rc_Buck2_24 F = 2.4 MHz 14.25 15 15.75 kΩ - Rc_Buck3 - 0.95 1 1.05 kΩ - C_Buck1_04(1) C_Buck2_04(1) Output capacitor at 400 kHz T = 27 °C Vout_buck1 = 3.3 V 33 47 56 µF ESR: < 15 mΩ Rated voltage: > 10 VDC X7R [±15% temperature characteristics] Choice: CGA6P1X7R1A476M250AC L_Buck1_04 L_Buck2_04 Output inductor at 400 kHz Iout = 3 A 11 15 18 µH Rdc : < 40mΩ Isat > 8 A SRF > 4 MHz SMD Choice: SPM12565VT-150M-D Cc_Buck1_04(1) Cc_Buck2_04(1) F = 400 kHz 8 10 12 nF - Rc_Buck1_04 Rc_Buck2_04 F = 400 kHz 4.84 5.1 5.35 kΩ - CVREG(1) - 3 4.7 10 µF max ESR < 0.1 Ω Rated voltage > 5 V X7R Choice: CGA4J3X7R1A475K125AB CLDO1(1) - - 2.2 - µF - CLDO2(1) - - 2.2 - µF - RNFSO1_PU Pull-up resistor to Vbat 28.5 30 31.5 KΩ - RIRQ_PU Pull-up resistor to VIO 28.5 30 31.5 KΩ - RNRST_PU Pull-up resistor to VIO 28.5 30 31.5 KΩ - CVIN12(1) BUCK1, 2 input capacitor - 22 - µF - CVIN3(1) BUCK3 input capacitor - 47 - µF - 1. Capacitance to be dimensioned, for example, according to voltage drop out requirements.

8.2 External components calculation

8.2.1 BUCK1 and BUCK2 inductor

ΔI L = IRipp le = 0.3 I O U T M A X (1) Where IOUT(MAX) is the maximum output current. Then, the inductor value can be estimated by the following equation: L > 1 f SW X ΔI L XV OU T X 1 − V OU T V I N M A X Where fSW is the switching frequency and VIN(max) is the maximum input voltage. The peak current flowing in the inductor is: I L PE AK = I O U T M A X + ΔI L If the inductor value decreases, the peak current increases. The peak current has to be lower than the current limit of the device. The inductor should have a saturation current higher than the device current limit. Note: To meet slope compensation, L needs to meet the following equation: L > 1

2 X V OU T

With Islope = 650 mA × fSW.

8.2.2 BUC3 inductor

The value of the output inductor is usually calculated to satisfy the peak-to-peak ripple current requirement. For the best compromise of cost, size and performance, it is suggested to keep the inductor current ripple between 20% and 40% of maximum load current. For example, if: ΔI L = IRipp le = 0.3 I O U T M A X (2) Where IOUT(MAX) is the maximum output current. Then, the inductor value can be estimated by the following equation: L > 1 f SW X ΔI L XV OU T X 1 − V OU T V I N M A X (3) Where fSW is the switching frequency and VIN(max) is the maximum input voltage. The peak current flowing in the inductor is: I L PE AK = I O U T M A X + ΔI L 2 (4) If the inductor value decreases, the peak current increases. The peak current has to be lower than the current limit of the device. The inductor should have a saturation current higher than the device current limit. Note: To meet slope compensation, L needs to meet the following equation: L > 1 (5) With Islope = 325 mA × fSW. SPSB100 Application circuit DS14640 - Rev 2 page 109/213

9 SPI registers

9.1 Global status byte GSB

Table 51. Global status byte GSB Table 52. Global status byte GSB description

31 GSBN

The GSBN is a logically NOR combination of GSB bits 0 to bit 6(1). at SDO directly after pulling CSN low. Section 5.2.2: Communication protocol for masks).

30 RSTB

Power-down sequence
WDFAIL (SR3 - 0x23)
FCCU fail (SR3 - 0x23) 0: No reset signal has been generated (default) 1: Reset signal has been generated RSTB is cleared by a read and Clear command to all bits in status register 1 causing the reset event.

29 SPIE

The SPIE indicates errors related to a wrong SPI communication.

SPI_SDI_STUCK_HIGH (SR4 - 0x24)
SPI_SDI_STUCK_LOW (SR4 - 0x24)
SPI_CSN_TIMEOUT (SR4 - 0x24)
SPI_CRC_ERR (SR4 - 0x24)
SPI_UNDEF_ADD (SR4 - 0x24)
SPI_STATUS_WRT (SR4 - 0x24)
SPI_CLK_CNT (SR4 - 0x24)
SPI_LBISTED (SR4 - 0x24) 0: No error (default) 1: Error detected

28 RES Reserved

27 FE1

The FE1 is a logical OR combination of errors coming from functional blocks.

OUTHS_OC (SR2 - 0x22)
OUTHS_OL (SR2 - 0x22)
BUCK1_UV (SR1 - 0x21)
BUCK2_UV (SR1 - 0x21) SPSB100 SPI registers DS14640 - Rev 2 page 110/213

BUCK3_UV (SR1 - 0x21)
BUCK1_OV (SR1 - 0x21)
BUCK2_OV (SR1 - 0x21)
BUCK3_OV (SR1 - 0x21)
BUCK1_OC (SR1 - 0x21)
BUCK2_OC (SR1 - 0x21)
BUCK3_OC (SR1 - 0x21)
LDO2_UV (SR1 - 0x21)
LDO2_OV (SR1 - 0x21)
BUCKX_PG_TIMEOUT from SPI request (SR1 - 0x21)
LDO2_PG_TIMEOUT from SPI request (SR1 - 0x21) 0: No error (default) 1: Error detected FE1 is cleared by a read and clear command to all related bits in status registers 3, 5 and 6 26 DE Device error bit DE is a logical OR combination of global errors related to the device.
FBB_OV (SR2 - 0x22)
FBB_UV (SR2 - 0x22)
VIO_UV (SR2 - 0x22)
TSD_CLx (SR2 - 0x22)
WD_ENA_ECHO_ERROR (SR2 - 0x22)
FCCU_ENA_ECHO_ERROR (SR2 - 0x22)
NFSO1_ECHO_ERROR (SR2 - 0x22)
IRQ_ECHO_ERROR (SR2 - 0x22)
NRST_ECHO_ERROR (SR2 - 0x22) 0: No error (default) 1: Error detected DE is cleared by a read and clear command to all related bits in status registers 2, 4 and 7 25 GW Global warning bit GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch off of functions.
FBB_UV_EW (SR4 - 0x24)
FBB_OV_EW (SR4 - 0x24)
VS_UV_EW (SR4 - 0x24)
TW_CLx (SR4 - 0x24) 0: No error (default) 1: Error detected GW is cleared by a read and clear command to all related bits in status register 2 and 4 24 FS Fail-safe The FS bit indicates that the device was forced into DEEP-SLEEP, RECOVERY-1 or -2 state due to the following fault conditions:
FCCUFAIL (SR3 - 0x23)
WDFAIL (SR3 - 0x23)
FORCED_SLEEP_TSD (SR3 - 0x23)
FORCED_SLEEP_POWUP (SR5 - 0x25)
GNDLOSS (SR3 - 0x23)
INT_REG_UV (SR3 - 0x23)
INT_REG_OV (SR3 - 0x23)
CURRENT_MISMATCH (SR3 - 0x23)
OSC_ERROR (SR3 - 0x23)
ABIST_ERROR (SR3 - 0x23)
LBIST_ERROR (SR3 - 0x23)
NVM_COMP_ERROR (SR3 - 0x23)
NVM_CRC_ERROR (SR3 - 0x23)
SPI_REG_COMP_ERROR (SR3 - 0x23) SPSB100 SPI registers DS14640 - Rev 2 page 111/213

FSM_COMP_ERROR (SR3 - 0x23) All control registers are set to default Control registers are blocked for WRITE access except the following bits:
Error flags
Wake-up settings
Timer setting 1: Fail-safe active FS is cleared by a read and clear command to all related bits in status register SR3 and SR5

9.2 Control register overview

Table 53. Control register overview (bit 31...28) upper nibbles Table 54. Control register overview (bit 27...24) lower nibbles

9.3 U_NVM register overview

Table 55. U_NVM register overview (bit 31...28) upper nibbles

Table 56. U_NVM register overview (bit 27...24) lower nibbles

0x0C DCR12 LSB R/WCRC 3 CRC 2 CRC 1 CRC 0 0x0D DCR13 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x0E DCR14 MSB PU_LOOP_FOR_EVER LDO2_REGFAIL_GO_REC LDO2_TRK_1 LDO2_TRK_0 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x0F DCR15 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x!0 DCR16 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x11 DCR17 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x12 DCR18 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x13 DCR19 MSB U_NVM_RELEASE_15 U_NVM_RELEASE_14 U_NVM_RELEASE_13 U_NVM_RELEASE_12 R/WU_NVM_RELEASE_7 U_NVM_RELEASE_6 U_NVM_RELEASE_5 U_NVM_RELEASE_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x14 DCR20 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x15 DCR21 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x16 DCR22 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x17 DCR23 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x18 DCR24 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x19 DCR25 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x1C DCR28 MSB RES RES RES RES R/WRES RES RES RES LSB CRC 3 CRC 2 CRC 1 CRC 0 SPSB100 SPI registers DS14640 - Rev 2 page 115/213

9.4 Status register overview

Table 57. Status register overview (bit 31...28) upper nibbles

Table 58. Status register overview (bit 27...24) lower nibbles

RTEMP_CL4_7 TEMP_CL4_6 TEMP_CL4_5 TEMP_CL4_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x2E DSR14 MSB RES RES RES RES RVS_7 VS_6 VS_5 VS_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x2F DSR15 MSB RES RES RES RES RWU_7 WU_6 WU_5 WU_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x30 DSR16 MSB RES RES RES RES RIGN_7 IGN_6 IGN_5 IGN_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x31 DSR17 MSB RES RES RES RES RFBB_7 FBB_6 FBB_5 FBB_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x32 DSR18 MSB BUCK1_FBLOSS NVM_COMPARE_ENA_STATUS WD_TIME_STATUS_3 WD_TIME_STATUS_2 RVBUCK1_ENA_STATUS LDO1_ENA_STATUS OUTHS_ENA_STATUS LOW_STATUS LSB CRC 3 CRC 2 CRC 1 CRC 0 SPSB100 SPI registers DS14640 - Rev 2 page 118/213

9.5 Control registers

Table 59. DCR1 (0x01) MSB Table 60. DCR1 (0x01) MSB description

23 RES Reserved

22 RES Reserved

21 RES Reserved

20 RES Reserved

19 RES Reserved

18 RES Reserved

17 WD_TIME_3

16 WD_TIME_2

Table 61. DCR1 (0x01) Table 62. DCR1 (0x01) description

15 WD_TIME_1

14 WD_TIME_0

13 VBUCK3_ENA BUCK3 enable bit (default value link to start up sequence setting)

12 VBUCK2_ENA

11 VBUCK1_ENA

10 LDO1_ENA

9 LDO2_ENA

8 LOW_POWER_SET

Table 63. DCR1 (0x01) LSB Table 64. DCR1 (0x01) LSB description

7 WD_LP_ENA 1: Watchdog is enabled in low power mode (default)

6 DO_POWER_DOWN

5 U-NVM_PROG

4 DO_POWER_CYCLE

3 CRC 3

2 CRC 2

1 CRC 1

0 CRC 0

Table 65. DCR2 (0x02) MSB Table 66. DCR2 (0x02) MSB description

21 NFSO_ASSERT_LOW

20 LBIST

19 ABIST

17 FCCU_COUNTER_12

16 FCCU_COUNTER_11

Table 67. DCR2 (0x02) Table 68. DCR2 (0x02) description

15 FCCU_COUNTER_10

14 FCCU_COUNTER_9

13 FCCU_COUNTER_8

12 FCCU_COUNTER_7

11 FCCU_COUNTER_6

10 FCCU_COUNTER_5

9 FCCU_COUNTER_4

8 FCCU_COUNTER_3

Table 69. DCR2 (0x02) LSB Table 70. DCR2 (0x02) LSB description

7 FCCU_COUNTER_2

6 FCCU_COUNTER_1

5 FCCU_COUNTER_0

4 FCCU_ENA

Table 71. DCR3 (0x03) MSB Table 72. DCR3 (0x03) MSB description

21 BUCK3_SPREAD_ENA

20 BUCK2_SPREAD_ENA

19 BUCK1_SPREAD_ENA

18 CLR_WDFAIL_CNT

17 RES Reserved

16 BUCK3_FTUNE_2

Table 73. DCR3 (0x03) Table 74. DCR3 (0x03) description

15 BUCK3_FTUNE_1

14 BUCK3_FTUNE_0

13 BOOST_OFF

12 FBB_OV_EW_TH_3

11 FBB_OV_EW_TH_2

10 FBB_OV_EW_TH_1

9 FBB_OV_EW_TH_0

8 FBB_UV_EW_TH_3

FBB undervoltage early warning threshold. Table 75. DCR3 (0x03) LSB Table 76. DCR3 (0x03) LSB description

7 FBB_UV_EW_TH_2

6 FBB_UV_EW_TH_1

5 FBB_UV_EW_TH_0

4 SPI_PROTECT_ACCESS

Table 77. DCR4 (0x04) MSB

Table 78. DCR4 (0x04) MSB description

22 BOOST_DSMON_TH_2

21 BOOST_DSMON_TH_1

20 BOOST_DSMON_TH_0

19 SWDBG_EXIT

18 VS_UV_EW_TH_4

17 VS_UV_EW_TH_3

16 VS_UV_EW_TH_2

Table 79. DCR4 (0x04) Table 80. DCR4 (0x04) description

15 VS_UV_EW_TH_1

14 VS_UV_EW_TH_0

13 FCCU_PROTOCOL

12 FCCU_STATIC_ERROR

11 OUTHS_1

10 OUTHS_0

9 BYPASS_DSMON_TH_2

8 BYPASS_DSMON_TH_1

Table 81. DCR4 (0x04) LSB Table 82. DCR4 (0x04) LSB description

7 BYPASS_DSMON_TH_0

6 CLR_REG_FAIL_CNT

5 KILL_SWDBG_TIMEOUT

4 WD_TRIG

Table 83. DCR5 (0x05) MSB Table 84. DCR5 (0x05) MSB description

22 CLR_REC2_FROM_DO_POWER_CYCLE Clear REC2_FROM_DO_POWER_CYCLE to 0

21 CLR_DEEP_SLEEP_FROM_DO_POWER_DOWN

20 CLR_POWUP_RETRY_COUNT

19 T1_ENA_2

18 T1_ENA_1

17 T1_ENA_0

16 T1_PER_2

Table 85. DCR5 (0x05) Table 86. DCR5 (0x05) description

15 T1_PER_1

14 T1_PER_0

13 TIMER_WAKE_ENA

12 IGN_CONFIG

11 IGN_FILT IGN filter configuration bits

10 IGN_ENA

9 IGN_PU

8 WU_CONFIG

Table 87. DCR5 (0x05) LSB Table 88. DCR5 (0x05) LSB description

7 WU_ENA

6 WU_PU

5 WU_FILT

4 TIMER_ENA

Table 89. DCR6 (0x06) MSB

Table 90. DCR6 (0x06) MSB description

22 MASK_BUCK3_PG_TIMEOUT_IRQ

21 MASK_BUCK3_OC_IRQ

20 MASK_BUCK3_PG_IRQ

19 MASK_BUCK3_IRQ

18 MASK_BUCK2_PG_TIMEOUT_IRQ

17 MASK_BUCK2_OC_IRQ

16 MASK_BUCK2_PG_IRQ reserved

Table 91. DCR6 (0x06) Table 92. DCR6 (0x06) description

15 MASK_BUCK2_IRQ

14 MASK_BUCK1_PG_TIMEOUT_IRQ

13 MASK_BUCK1_OC_IRQ

12 MASK_BUCK1_PG_IRQ

11 MASK_BUCK1_IRQ

10 MASK_FBB_OV_IRQ

9 MASK_FBB_UV_IRQ

8 MASK_FBB_OV_EW_IRQ

Table 93. DCR6 (0x06) LSB Table 94. DCR6 (0x06) LSB description

7 MASK_FBB_UV_EW_IRQ

6 MASK_LDO2_PG_IRQ

5 MASK_LDO2_PG_TIMEOUT_IRQ

4 MASK_LDO2_IRQ

3 CRC3

2 CRC2

1 CRC1

0 CRC0

Table 95. DCR7 (0x07) MSB Table 96. DCR7 (0x07) MSB description

22 MASK_LDO1_PG_IRQ

21 MASK_LDO1_PG_TIMEOUT_IRQ

20 MASK_LDO1_IRQ

19 MASK_BOOST_IN_LP_IRQ

18 MASK_BYPASS_VDSMON_IRQ

17 MASK_BOOST_VDSMON_IRQ

16 IRQ_REQUEST

Table 97. DCR7 (0x07) Table 98. DCR7 (0x07) description

15 MASK_VS_EW_IRQ

14 RES Reserved

13 MASK_CL4_TW_IRQ

12 MASK_CL3_TW_IRQ

11 MASK_CL2_TW_IRQ

10 MASK_CL1_TW_IRQ

9 MASK_CL0_TW_IRQ

8 MASK_OUTHS_IRQ

Table 99. DCR7 (0x07) LSB Table 100. DCR7 (0x07) LSB description

7 MASK_SPI_ERROR_IRQ

6 MASK_NFSO1_ECHO_ERROR_IRQ

5 MASK_WD_ENA_ECHO_ERROR_IRQ

4 MASK_FCCU_ENA_ECHO_ERROR_IRQ

Table 101. DCR8 (0x08) MSB

Table 102. DCR8 (0x08) MSB description

22 MASK_SWDBG_VIO_IRQ

watchdog is restarted with a long open window and SWDBG is ignored.

21 MASK_LP_READY_IRQ

Mask IRQ when FSM goes to low power state.

20 CLR_TSD_CNT_FAIL

19 MASK_BUCK3_OC_POWER_OFF

18 MASK_BUCK2_OC_POWER_OFF

17 MASK_BUCK1_OC_POWER_OFF

16 MASK_BUCK3_UV_POWER_OFF

Table 103. DCR8 (0x08) Table 104. DCR8 (0x08) description

15 MASK_BUCK2_UV_POWER_OFF

14 MASK_BUCK1_UV_POWER_OFF

13 MASK_TW_GW

12 MASK_OL_GSB

11 RES Reserved

10 MASK_GW_GSB

9 RES Reserved

8 RES Reserved

Table 105. DCR8 (0x08) LSB Table 106. DCR8 (0x08) LSB description

7 RES Reserved

6 RES Reserved

5 RES Reserved

4 GO_INIT

9.6 U_NVM registers

from DCR10 to DRC28 can be only readable as showed below. Table 107. DCR10 (0x0A) MSB Table 108. DCR10 (0x0A) MSB description

19 BUCK1_FREQ

18 BUCK1_PU_VALUE_1

17 BUCK1_PU_VALUE_0

16 BUCK1_PU_STEP_ENA_2

Table 109. DCR10 (0x0A) Table 110. DCR10 (0x0A) description

15 BUCK1_PU_STEP_ENA_1

14 BUCK1_PU_STEP_ENA_0

13 BUCK1_PD_STEP_OFF_2

12 BUCK1_PD_STEP_OFF_1

11 BUCK1_PD_STEP_OFF_0

10 BUCK1_IPEAK_2

9 BUCK1_IPEAK_1

8 BUCK1_IPEAK_0

Table 111. DCR10 (0x0A) LSB Table 112. DCR10 (0x0A) LSB description

7 BUCK1_REGFAIL_GO_REC

6 BUCK1_SS_VALUE_1

5 BUCK1_SS_VALUE_0

4 BUCK1_REFRESH_FREQ

Table 113. DCR11 (0x0B) MSB Table 114. DCR11 (0x0B) MSB description

19 BUCK2_FREQ

18 BUCK2_PU_VALUE_1

17 BUCK2_PU_VALUE_0

16 BUCK2_PU_STEP_ENA_2

Table 115. DCR11 (0x0B) Table 116. DCR11 (0x0B) description

15 BUCK2_PU_STEP_ENA_1

14 BUCK2_PU_STEP_ENA_0

13 BUCK2_PD_STEP_OFF_2

12 BUCK2_PD_STEP_OFF_1

11 BUCK2_PD_STEP_OFF_0

10 BUCK2_IPEAK_2

9 BUCK2_IPEAK_1

8 BUCK2_IPEAK_0

Table 117. DCR11 (0x0B) LSB Table 118. DCR11 (0x0B) LSB description

7 BUCK2_REGFAIL_GO_REC

6 BUCK2_SS_VALUE_1

5 BUCK2_SS_VALUE_0

4 BUCK2_REFRESH_FREQ

Table 119. DCR12 (0x0C) MSB Table 120. DCR12 (0x0C) MSB description

19 BYPASS_DIS

18 BUCK3_PU_VALUE_2

17 BUCK3_PU_VALUE_1

16 BUCK3_PU_VALUE_0

Table 121. DCR12 (0x0C) Table 122. DCR12 (0x0C) description

15 BUCK3_PU_STEP_ENA_2

14 BUCK3_PU_STEP_ENA_1

13 BUCK3_PU_STEP_ENA_0

12 BUCK3_PD_STEP_OFF_2

11 BUCK3_PD_STEP_OFF_1

10 BUCK3_PD_STEP_OFF_0

9 BUCK3_IPEAK_1

8 BUCK3_IPEAK_0

Table 123. DCR12 (0x0C) LSB Table 124. DCR12 (0x0C) LSB description

7 BUCK3_REGFAIL_GO_REC

6 BUCK3_SS_VALUE_1

5 BUCK3_SS_VALUE_0

4 BUCK3_REFRESH_FREQ

Table 125. DCR13 (0x0D) MSB Table 126. DCR13 (0x0D) MSB description

19 U_NVM_D_15

18 U_NVM_D_14

17 U_NVM_D_13

16 U_NVM_D_12

Table 127. DCR13 (0x0D) Table 128. DCR13 (0x0D) description

15 U_NVM_D_11

14 U_NVM_D_10

13 U_NVM_D_9

12 U_NVM_D_8

11 U_NVM_D_7

10 U_NVM_D_6

9 U_NVM_D_5

8 U_NVM_D_4

Table 129. DCR13 (0x0D) LSB Table 130. DCR13 (0x0D) LSB description

7 U_NVM_D_3

6 U_NVM_D_2

5 U_NVM_D_1

4 U_NVM_D_0

Table 131. DCR14 (0x0E) MSB Table 132. DCR14 (0x0E) MSB description

19 PU_LOOP_FOR_EVER

18 LDO2_REGFAIL_GO_REC

17 LDO2_TRK_1

16 LDO2_TRK_0

Table 133. DCR14 (0x0E) Table 134. DCR14 (0x0E) description

15 LDO2_PD_STEP_OFF_2

14 LDO2_PD_STEP_OFF_1

13 LDO2_PD_STEP_OFF_0

12 LDO2_PU_STEP_ENA_2

11 LDO2_PU_STEP_ENA_1

10 LDO2_PU_STEP_ENA_0

9 LDO1_PD_STEP_OFF_2

8 LDO1_PD_STEP_OFF_1

Table 135. DCR14 (0x0E) LSB

Table 136. DCR14 (0x0E) LSB description

7 LDO1_PD_STEP_OFF_0

6 LDO1_PU_STEP_ENA_2

5 LDO1_PU_STEP_ENA_1

4 LDO1_PU_STEP_ENA_0

Table 137. DCR15 (0x0F) MSB Table 138. DCR15 (0x0F) MSB description

19 U_NVM_F_15

18 U_NVM_F_14

Table 139. DCR15 (0x0F) Table 140. DCR15 (0x0F) description Table 141. DCR15 (0x0F) LSB Table 142. DCR15 (0x0F) LSB description

Table 143. DCR16 (0x10) MSB Table 144. DCR16 (0x10) MSB description

19 U_NVM_G_15

18 U_NVM_G_14

17 U_NVM_G_13

16 NRESET_PD_STEP_ASSERT_2

Table 145. DCR16 (0x10)

Table 146. DCR16 (0x10) description

15 NRESET_PD_STEP_ASSERT_1

14 NRESET_PD_STEP_ASSERT_0

13 NRESET_PU_STEP_DEASSERT_2

12 NRESET_PU_STEP_DEASSERT_1

11 NRESET_PU_STEP_DEASSERT_0

10 PU_WAIT_PG_ENA_7

9 PU_WAIT_PG_ENA_6

8 PU_WAIT_PG_ENA_5

Table 147. DCR16 (0x10) LSB Table 148. DCR16 (0x10) LSB description

7 PU_WAIT_PG_ENA_4

6 PU_WAIT_PG_ENA_3

5 PU_WAIT_PG_ENA_2

4 PU_WAIT_PG_ENA_1

Table 149. DCR17 (0x11) MSB Table 150. DCR17 (0x11) MSB description

19 U_NVM_CRC0_7

18 U_NVM_CRC0_6

17 U_NVM_CRC0_5

16 U_NVM_CRC0_4

Table 151. DCR17 (0x11) Table 152. DCR17 (0x11) description

15 U_NVM_CRC0_3

14 U_NVM_CRC0_2

13 U_NVM_CRC0_1

12 U_NVM_CRC0_0

11 U_PROG0_1 Not accessible by user but programmed by NVM controller during user programming

10 U_PROG0_0 Not accessible by user but programmed by NVM controller during user programming

9 U_NVM_H_5

8 U_NVM_H_4

Table 153. DCR17 (0x11) LSB Table 154. DCR17 (0x11) LSB description

7 NFSO_STATE_IN_DEEP_SLEEP

6 U_NVM_H_2

5 U_NVM_H_1

4 BOOST_DIS

Table 155. DCR18 (0x12) MSB Table 156. DCR18 (0x12) MSB description

19 PD_WAIT_VREG_DEL_OFF_1

18 PD_WAIT_VREG_DEL_OFF_0

Table 157. DCR18 (0x12) Table 158. DCR18 (0x12) description Table 159. DCR18 (0x12) LSB

Table 160. DCR18 (0x12) LSB description Table 161. DCR19 (0x13) MSB Table 162. DCR19 (0x13) MSB description

19 U_NVM_RELEASE_15

18 U_NVM_RELEASE_14

17 U_NVM_RELEASE_13

16 U_NVM_RELEASE_12

Table 163. DCR19 (0x13)

Table 164. DCR19 (0x13) description

15 U_NVM_RELEASE_11

14 U_NVM_RELEASE_10

13 U_NVM_RELEASE_9

12 U_NVM_RELEASE_8

11 U_NVM_RELEASE_7

10 U_NVM_RELEASE_6

9 U_NVM_RELEASE_5

8 U_NVM_RELEASE_4

Table 165. DCR19 (0x13) LSB Table 166. DCR19 (0x13) LSB description

7 U_NVM_RELEASE_3

6 U_NVM_RELEASE_2

5 U_NVM_RELEASE_1

4 U_NVM_RELEASE_0

Table 167. DCR20 (0x14) MSB Table 168. DCR20 (0x14) MSB description

19 U_NVM_K_15 User NVM regs

18 U_NVM_K_14

17 U_NVM_K_13

16 U_NVM_K_12

Table 169. DCR20 (0x14) Table 170. DCR20 (0x14) description

15 U_NVM_K_11

14 U_NVM_K_10

13 U_NVM_K_9

12 U_NVM_K_8

11 U_NVM_K_7

10 U_NVM_K_6

9 U_NVM_K_5

8 U_NVM_K_4

Table 171. DCR20 (0x14) LSB Table 172. DCR20 (0x14) LSB description

7 LOW_SET_3

6 LOW_SET_2

5 LOW_SET_1

4 LOW_SET_0

Table 173. DCR21 (0x15) MSB Table 174. DCR21 (0x15) MSB description

19 U_NVM_L_15

18 U_NVM_L_14

17 U_NVM_L_13

16 U_NVM_L_12

Table 175. DCR21 (0x15) Table 176. DCR21 (0x15) description

15 U_NVM_L_11

14 U_NVM_L_10

13 U_NVM_L_9

12 U_NVM_L_8

11 U_NVM_L_7

10 U_NVM_L_6

9 U_NVM_L_5

8 U_NVM_L_4

Table 177. DCR21 (0x15) LSB Table 178. DCR21 (0x15) LSB description

7 U_NVM_L_3

6 U_NVM_L_2

5 U_NVM_L_1

4 U_NVM_L_0

Table 179. DCR22 (0x16) MSB Table 180. DCR22 (0x16) MSB description

19 U_NVM_M_15

18 U_NVM_M_14

17 U_NVM_M_13

16 U_NVM_M_12

Table 181. DCR22 (0x16) Table 182. DCR22 (0x16) description

15 U_NVM_M_11

14 U_NVM_M_10

13 U_NVM_M_9

12 U_NVM_M_8

11 U_NVM_M_7

10 U_NVM_M_6

9 U_NVM_M_5

8 U_NVM_M_4

Table 183. DCR22 (0x16) LSB Table 184. DCR22 (0x16) LSB description

7 U_NVM_M_3

6 U_NVM_M_2

5 U_NVM_M_1

4 U_NVM_M_0

Table 185. DCR23 (0x17) MSB Table 186. DCR23 (0x17) MSB description

19 U_NVM_N_15

18 U_NVM_N_14

17 U_NVM_N_13

16 U_NVM_N_12

Table 187. DCR23 (0x17) Table 188. DCR23 (0x17) description

15 U_NVM_N_11

14 U_NVM_N_10

13 U_NVM_N_9

12 U_NVM_N_8

11 U_NVM_N_7

10 U_NVM_N_6

9 U_NVM_N_5

8 U_NVM_N_4

Table 189. DCR23 (0x17) LSB

Table 190. DCR23 (0x17) LSB

7 U_NVM_N_3

6 U_NVM_N_2

5 U_NVM_N_1

4 U_NVM_N_0

Table 191. DCR24 (0x18) MSB Table 192. DCR24 (0x18) MSB description

19 U_NVM_O_15

18 U_NVM_O_14

17 U_NVM_O_13

16 U_NVM_O_12

Table 193. DCR24 (0x18)

Table 194. DCR24 (0x18) description

15 U_NVM_O_11

14 U_NVM_O_10

13 U_NVM_O_9

12 U_NVM_O_8

11 U_NVM_O_7

10 U_NVM_O_6

9 U_NVM_O_5

8 U_NVM_O_4

Table 195. DCR24 (0x18) LSB Table 196. DCR24 (0x18) LSB description

7 U_NVM_O_3

6 U_NVM_O_2

5 U_NVM_O_1

4 U_NVM_O_0

Table 197. DCR25 (0x19) MSB Table 198. DCR25 (0x19) MSB description

19 U_NVM_CRC1_7

18 U_NVM_CRC1_6

17 U_NVM_CRC1_5

16 U_NVM_CRC1_4

Table 199. DCR25 (0x19) Table 200. DCR25 (0x19)

15 U_NVM_CRC1_3

14 U_NVM_CRC1_2

13 U_NVM_CRC1_1

12 U_NVM_CRC1_0

11 U_PROG1_1 Not accessible by user but programmed by NVM controller during user programming

10 U_PROG1_0 Not accessible by user but programmed by NVM controller during user programming

9 U_NVM_P_5

8 U_NVM_P_4

Table 201. DCR25 (0x19) LSB Table 202. DCR25 (0x19) LSB description

7 U_NVM_P_3

6 U_NVM_P_2

5 U_NVM_P_1

4 U_NVM_P_0

Table 203. DCR28 (0x1C) MSB Table 204. DCR28 (0x1C) MSB description

16 RES Reserved

Table 205. DCR28 (0x1C) Table 206. DCR28 (0x1C) description

15 RES Reserved

13 RES Reserved

12 RES Reserved

10 RES Reserved

Table 207. DCR28 (0x1C) LSB

Table 208. DCR28 (0x1C) LSB description

4 RES Reserved

9.7 Status registers

Table 209. DSR1 (0x21) MSB Table 210. DSR1 (0x21) MSB description

21 FORCED_SLEEP_WDFAIL

20 BUCK3_OC

19 BUCK3_OV

18 BUCK3_UV

17 BUCK3_PG_TIMEOUT

16 BUCK2_OC

Table 211. DSR1 (0x21) Table 212. DSR1 (0x21) description

15 BUCK2_OV

14 BUCK2_UV

13 BUCK2_PG_TIMEOUT

12 BUCK1_OC 1: BUCK1 overcurrent detected

11 BUCK1_OV

10 BUCK1_UV

9 BUCK1_PG_TIMEOUT

8 LDO2_PG_TIMEOUT 1: PG timeout occurs following a SPI request to tun on LDO2

Table 213. DSR1 (0x21) LSB Table 214. DSR1 (0x21) LSB description

7 LDO2_UV

6 LDO2_OV

5 LDO1_PG_TIMEOUT 1: PG timeout occurs following a SPI request to tun on LDO1

4 LDO1_UV

Table 215. DSR2 (0x22) MSB

Table 216. DSR2 (0x22) MSB description

22 OUTHS_OL

21 OUTHS_OC

20 BOOST_IN_LP

19 BYPASS_VDSMON_ERROR

18 BOOST_VDSMON_ERROR

17 FBB_OV

16 FBB_UV

Table 217. DSR2 (0x22) Table 218. DSR2 (0x22) description

15 IRQ_ECHO_ERROR

14 FCCU_ENA_ECHO_ERROR

13 NFSO1_ECHO_ERROR

12 WD_ENA_ECHO_ERROR

11 NRST_ECHO_ERROR

10 VIO_UV

9 TSD_CL4

8 TSD_CL3

Table 219. DSR2 (0x22) LSB Table 220. DSR2 (0x22) LSB description

7 TSD_CL2

6 TSD_CL1

5 TSD_CL0 Central thermal shutdown

4 TSD

Table 221. DSR3 (0x23) MSB Table 222. DSR3 (0x23) MSB description

22 LBIST_STOPPED 1: Indicates that LBIST has been stopped due to fault events

21 BUCK3_INT_FAIL

20 BUCK2_INT_FAIL BUCK2 internal fail that may be caused by LDO_BUCK2_OV or LDO_BUCK2_UV

19 BUCK1_INT_FAIL

18 LBIST_ERROR_1 1: The logic BIST2 reported an error

17 LBIST_ERROR_0 1: The logic BIST1 reported an error

16 ABIST_ERROR 1: The analog BIST reported an error

Table 223. DSR3 (0x23) Table 224. DSR3 (0x23) description

15 CURRENT_MISMATCH 1: A current mismatch occurs between main and monitoring currents

14 FORCED_SLEEP_TSD 1: state machine reaches DEEP-SLEEP after 3 TSD events

13 FCCUFAIL

12 WDFAIL

11 INT_REG_UV

10 INT_REG_OV

9 NVM_COMP_ERROR Indicates an error between NVM and mirror register

8 NVM_CRC_ERROR Indicates a NVM CRC error at NVM download

Table 225. DSR3 (0x33) LSB

Table 226. DSR3 (0x33) LSB description

7 GNDLOSS

6 OSC_ERROR

5 SPI_REG_COMP_ERROR

4 FSM_COMP_ERROR

Table 227. DSR4 (0x24) MSB Table 228. DSR4 (0x24) MSB description

22 SPI_ALL_WAKEUP_DISABLE

SPI tentative occurs to disable all wake up sources.

21 SPI_CLK_CNT

20 SPI_CSN_TIMEOUT 1: SPI CSN time-out error detected

19 SPI_CRC_ERR 1: SPI CRC error detected

18 SPI_SDI_STUCK_HIGH 1: SPI SDI stuck at high level

17 SPI_SDI_STUCK_LOW 1: SPI SDI stuck at low level

16 SPI_UNDEF_ADD 1: SPI access to undefined address

Table 229. DSR4 (0x24)

Table 230. DSR4 (0x24) description

15 SPI_STATUS_WRT 1: SPI writes access to status register

14 SPI_LBISTED 1: SPI access while SPI is under LBIST test

13 FBB_OV_EW

In ACTIVE and REC-1 modes, an interrupt pulse is generated at IRQ.

12 FBB_UV_EW

11 VS_UV_EW

9 TW_CL4

8 TW_CL3

Table 231. DSR4 (0x24) LSB Table 232. DSR4 (0x24) LSB description

7 TW_CL2

6 TW_CL1

5 TW_CL0 Central thermal warning

Table 233. DSR5 (0x25) MSB Table 234. DSR5 (0x25) MSB description

22 FP_READY

1: Transition from Low power to full power occurred.

21 BOOST_LEVEL_SET

20 BOOST_ENA_STATUS

19 BYPASS_STATUS

18 BUCK3_PG_OK

17 BUCK2_PG_OK

16 BUCK1_PG_OK

Table 235. DSR5 (0x25) Table 236. DSR5 (0x25) description

15 DEV_STATE_5

14 DEV_STATE_4

13 DEV_STATE_3

12 DEV_STATE_2

11 DEV_STATE_1

10 DEV_STATE_0

9 DEEP-SLEEP_FROM_DO_POWER_DOWN_1

8 DEEP-SLEEP_FROM_DO_POWER_DOWN_0

Table 237. DEV_STATE binary code for state machine states/modes

Table 238. DSR5 (0x25) LSB Table 239. DSR5 (0x25) LSB description

7 FORCED_SLEEP_POWUP 1: state machine reaches DEEP-SLEEP after 3 attend to power-up

6 FSM_TO_REC2

5 REC2_FROM_DO_POWER_CYCLE_1

4 REC2_FROM_DO_POWER_CYCLE_0

Table 240. DSR6 (0x26) MSB Table 241. DSR6 (0x26) MSB description

21 SWDBG_VIO

SWDBG is linked to VIO up to the end of the timeout following the power-up sequence. If not masked, IRQ is generated and the watchdog starts with L.O.W.

20 SWDBG_STATE state of SWDBG input pin with VIO thresholds

Table 242. DSR6 (0x26) Table 243. DSR6 (0x26) description

14 FIN1_STATE

13 IGN_STATE

Note that the status is only valid if IGN is configured as wake-up input in configuration register (0x05).

12 WU_STATE

Note that the status is only valid if WU is configured as wake-up input in configuration register (0x05).

11 IGN_WAKE

10 WU_WAKE

8 TIMER_WAKE

Table 244. DSR6 (0x26) LSB Table 245. DSR6 (0x26) LSB description

7 IRQ_ECHO

Indicates current status of IRQ pin.

6 NRST_ECHO

Indicates current status of NRST pin.

5 IRQ_SENT

4 NFSO1_ECHO

Indicates current status of NFSO1 pin. Table 246. DSR7 (0x27) MSB Table 247. DSR7 (0x27) MSB description

22 VPOR VS power-on reset threshold (VPOR) reached bit is latched until a "Read and clear" command

21 LDO1_PG_OK Indicates power-good LDO1 bit is latched until a “read and clear” command

20 LDO2_ENA_STATUS

19 LDO2_PG_OK

18 FCCU_ENA_ECHO

17 WD_ENA_ECHO

16 WD_TIMER_STATE_1

Table 248. DSR7 (0x27) Table 249. DSR7 (0x27) description

15 WD_TIMER_STATE_0

14 WDFAIL_CNT_3

13 WDFAIL_CNT_2

12 WDFAIL_CNT_1

11 WDFAIL_CNT_0

10 TSD_CNT_FAIL_1 Thermal shut down sequence retry counter

9 TSD_CNT_FAIL_0

8 POWUP_RETRY_CNT_1

Table 250. DSR7 (0x27) LSB

Table 251. DSR7 (0x27) LSB description

7 POWUP_RETRY_CNT_0

6 RES

5 NVM_PROG_OK U-NVM programming is completed without error

4 NVM_PROG_DONE U-NVM programming is completed

Table 252. DSR8 (0x28) MSB Table 253. DSR8 (0x28) MSB description

22 FCCU_LAST_STABLE_12

21 FCCU_LAST_STABLE_11

20 FCCU_LAST_STABLE_10

19 FCCU_LAST_STABLE_9

18 FCCU_LAST_STABLE_8

17 FCCU_LAST_STABLE_7

16 FCCU_LAST_STABLE_6

Table 254. DSR8 (0x28) Table 255. DSR8 (0x28) description

15 FCCU_LAST_STABLE_5

14 FCCU_LAST_STABLE_4

13 FCCU_LAST_STABLE_3

12 FCCU_LAST_STABLE_2

11 FCCU_LAST_STABLE_1

10 FCCU_LAST_STABLE_0 FCCU monitor last stable value duration

9 FORCED_SLEEP_REGFAIL 1: When REG_FAIL_CNT = 3 then FSM transit from REC_2 to DEEP-SLEEP (similar to

8 REG_FAIL_CNT_1

Table 256. DSR8 (0x28) LSB

0 ABIST boost ignored bit

Table 257. DSR8 (0x28) LSB description

7 REG_FAIL_CNT_0

6 ABIST_BOOST_IGNORED

5 LBIST_COMPLETE

4 ABIST_COMPLETE

Table 258. DSR9 (0x29) MSB Table 259. DSR9 (0x29) MSB description

Table 260. DSR9 (0x29) Table 261. DSR9 (0x29) description

13 TEMP_CL0_9

12 TEMP_CL0_8

11 TEMP_CL0_7

10 TEMP_CL0_6

9 TEMP_CL0_5

8 TEMP_CL0_4

Table 262. DSR9 (0x29) LSB Table 263. DSR9 (0x29) LSB description

7 TEMP_CL0_3

6 TEMP_CL0_2

5 TEMP_CL0_1

4 TEMP_CL0_0

Table 264. DSR10 (0x2A) MSB Table 265. DSR10 (0x2A) MSB description Table 266. DSR10 (0x2A) Table 267. DSR10 (0x2A) description

13 TEMP_CL1_9

12 TEMP_CL1_8

11 TEMP_CL1_7

10 TEMP_CL1_6

9 TEMP_CL1_5

8 TEMP_CL1_4

Table 268. DSR10 (0x2A) LSB Table 269. DSR10 (0x2A) LSB description

7 TEMP_CL1_3

6 TEMP_CL1_2

5 TEMP_CL1_1

4 TEMP_CL1_0

Table 270. DSR11 (0x2B) MSB Table 271. DSR11 (0x2B) MSB description Table 272. DSR11 (0x2B)

Table 273. DSR11 (0x2B) description

13 TEMP_CL2_9

12 TEMP_CL2_8

11 TEMP_CL2_7

10 TEMP_CL2_6

9 TEMP_CL2_5

8 TEMP_CL2_4

Table 274. DSR11 (0x2B) LSB Table 275. DSR11 (0x2B) LSB description

7 TEMP_CL2_3

6 TEMP_CL2_2

5 TEMP_CL2_1

4 TEMP_CL2_0

Table 276. DSR12 (0x2C) MSB Table 277. DSR12 (0x2C) MSB description

Table 278. DSR12 (0x2C) Table 279. DSR12 (0x2C) description

13 TEMP_CL3_9

12 TEMP_CL3_8

11 TEMP_CL3_7

10 TEMP_CL3_6

9 TEMP_CL3_5

8 TEMP_CL3_4

Table 280. DSR12 (0x2C) LSB Table 281. DSR12 (0x2C) LSB description

7 TEMP_CL3_3

6 TEMP_CL3_2

5 TEMP_CL3_1

4 TEMP_CL3_0

Table 282. DSR13 (0x2D) MSB Table 283. DSR13 (0x2D) MSB description Table 284. DSR13 (0x2D) Table 285. DSR13 (0x2D) description

13 TEMP_CL4_9

12 TEMP_CL4_8

11 TEMP_CL4_7

10 TEMP_CL4_6

9 TEMP_CL4_5

8 TEMP_CL4_4

Table 286. DSR13 (0x2D) LSB Table 287. DSR13 (0x2D) LSB description

7 TEMP_CL4_3

6 TEMP_CL4_2

5 TEMP_CL4_1

4 TEMP_CL4_0

Table 288. DSR14 (0x2E) MSB Table 289. DSR14 (0x2E) MSB description Table 290. DSR14 (0x2E)

Table 291. DSR14 (0x2E)

13 VS_9

12 VS_8

11 VS_7

10 VS_6

9 VS_5

8 VS_4

Table 292. DSR14 (0x2E) LSB Table 293. DSR14 (0x2E) LSB description

7 VS_3

6 VS_2

5 VS_1

4 VS_0

Table 294. DSR15 (0x2F) MSB Table 295. DSR15 (0x2F) MSB

Table 296. DSR15 (0x2F) Table 297. DSR15 (0x2F) description

13 WU_9

12 WU_8

11 WU_7

10 WU_6

9 WU_5

8 WU_4

Table 298. DSR15 (0x2F) LSB Table 299. DSR15 (0x2F) LSB description

7 WU_3

6 WU_2

5 WU_1

4 WU_0

Table 300. DSR16 (0x30) MSB Table 301. DSR16 (0x30) MSB description Table 302. DSR16 (0x30) Table 303. DSR16 (0x30) description

13 IGN_9

12 IGN_8

11 IGN_7

10 IGN_6

9 IGN_5

8 IGN_4

Table 304. DSR16 (0x30) LSB Table 305. DSR16 (0x30) LSB description

7 IGN_3

6 IGN_2

5 IGN_1

4 IGN_0

Table 306. DSR17 (0x31) MSB Table 307. DSR17 (0x31) MSB description Table 308. DSR17 (0x31)

Table 309. DSR17 (0x31) description

13 FBB_9

12 FBB_8

11 FBB_7

10 FBB_6

9 FBB_5

8 FBB_4

Table 310. DSR17 (0x31) LSB Table 311. DSR17 (0x31) LSB description

7 FBB_3

6 FBB_2

5 FBB_1

4 FBB_0

Table 312. DSR18 (0x32) MSB Table 313. DSR18 (0x32) MSB description

20 BUCK2_FBLOSS

19 BUCK1_FBLOSS

18 NVM_COMPARE_ENA_STATUS 1: Status bit from ST_NVM to NVM_COMPARE_DISABLE inverted bit for user read

17 WD_TIME_STATUS_3 Live bit

16 WD_TIME_STATUS_2 Live bit

Table 314. DSR18 (0x32) Table 315. DSR18 (0x32) description

15 WD_TIME_STATUS_1 Live bit

14 WD_TIME_STATUS_0 Live bit

13 VBUCK3_ENA_STATUS Live bit

12 VBUCK2_ENA_STATUS Live bit

11 VBUCK1_ENA_STATUS Live bit

10 LDO1_ENA_STATUS Live bit

9 OUTHS_ENA_STATUS Live bit

8 LOW_STATUS

Table 316. DSR18 (0x32) LSB Table 317. DSR18 (0x32) LSB description

7 BOOST_ENA_STATUS Live bit

6 FCCU_ENA_STATUS Live bit

DS14640 - Rev 2 page 191/213

9.8 Status register that must be cleared to enter into active FP mode

Table 318. Status register list to be cleared for active FP mode

lbist_complete lbist_stopped ldo1_pg_ok ldo1_pg_timeout ldo1_uv ldo2_ov ldo2_pg_ok ldo2_pg_timeout ldo2_uv lp_ready nvm_comp_error nvm_crc_error osc_error ouths_oc ouths_ol nrst_echo_error spi_all_wakeup_disable spi_clk_cnt spi_crc_error spi_csn_timeout spi_reg_comp_error spi_sdi_stuck_high spi_sdi_stuck_low spi_lbisted spi_status_wrt spi_undef_add timer_wake tsd_cl0 tsd_cl1 tsd_cl2 tsd_cl3 tsd_cl4 vio_uv vpor wdfail wu_wake forced_sleep_regfail SPSB100 SPI registers DS14640 - Rev 2 page 193/213

10 PCB layout recommendation

affects noise pickup and can cause a good design to perform with results that are under the expectations. any other additional components necessary to put in place a suitable filtering action. should be kept away from the inductors and other noise sources.

Allow enough copper for VIN, GND and PHx
All bypass capacitors are placed as close as possible to their connecting pins
Components for loop compensation are placed as close as possible to the COMP pin
SGND as well as GND are connected to the inner PGND plane through via holes
PHx nodes copper should only be routed on the top layer to minimize switching noises
FBx trace routing is kept away from the software node
Thermal via holes are placed on VINx and PGND pads to improve thermal dissipation

Figure 72. Assembly top

Figure 75. Assembly bottom

10.1 PCB metal and component placement

10.2 Solder mask

than the openings in the solder mask. This allows for layers to be misaligned by up to 0.1 mm on both axes. x/y aspect ratio of the solder mask strip.

Figure 76. Solder mask defined (SMD)

10.3 Stencil design

(0.005”). The reduction should be adjusted for stencils of other thicknesses.

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark. 11.1 VFQFN56+4L (8x8x0.9 mm exp. pad down) package information Figure 77. VFQFN56+4L (8x8x0.9 mm exp. pad down) package outline

Package information

DS14640 - Rev 2 page 198/213

Table 319. VFQFN56+4L (8x8x0.9 mm exp. pad down) package mechanical data DS14640 - Rev 2 page 199/213

Revision history

Table 320. Document revision history 04-Jun-2024 1 Initial release. converter and Section 7.10: BUCK3 converter. Table 78. DCR4 (0x04) MSB description and Table 86. DCR5 (0x05)

DS14640 - Rev 2 page 202/213

DS14640 - Rev 2 page 203/213

DS14640 - Rev 2 page 204/213

IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2024 STMicroelectronics – All rights reserved SPSB100 DS14640 - Rev 2 page 213/213

Product Information

SPSB100 specifications and overview.

Summary

Automotive power management IC for highly integrated processors 07-Oct-2024

Description

Automotive power management IC for highly integrated processors 07-Oct-2024

Source title SPSB100_V01 Datasheet(PDF) - STMicroelectronics

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