SPF-3043 SIRENZA | Alldatasheet

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Technical content

1 EDS-101772 Rev D

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for i naccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at t he user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved. 02468 1 0 3V,20mA 5V,40mA lobmyS scitsiretcarahCeciveD snoitidnoCtseT V SD I,V5= QD Cº52,Am04= )detonesiwrehtosselnu( tseT ycneuqerF stinU .niM .pyT .xaM G XAM niaGelbaliavAmumixaMZ S Z= S Z,* L Z= L* zHG9.0 zHG9.1 Bd 5.62 4.32 FN NIM erugiFesioNmuminiMZ S=Γ TPO Z, L Z= L* zHG9.0 zHG9.1 Bd 23.0 45.0 S 12 niaGnoitresnI ]1[ ZS Z= L 05= Ω zHG9.0B d5 .810 .025 .12 FNe rugiFesioN ]2[ draoBtiucriCnoitacilppAANLz HG9.1B d5 0.10 4.1 niaGn iaG ]2[ draoBtiucriCnoitacilppAANLz HG9.1B d0 .413 .51 PIO 3 tnioPtpecretnIredrOdrihTtuptuO ]2[ draoBtiucriCnoitacilppAANLz HG9.1m Bd0 .625 .82 P Bd1 tnioPnoisserpmoCBd1tuptuO ]2[ draoBtiucriCnoitacilppAANLz HG9.1m Bd0 .510 .71 VP egatloVffohcniP ]1[ V SD I,V2= SD Am1.0=V 1 .1-8 .0-5 .0- I SSD tnerruCniarDdetarutaS ]1[ V SD V,V2= SG V0=A m0 30 60 21 gm ecnatcudnocsnarT ]1[ V SD V,V2= SG V0=S m0 90 51 VB OSG egatloVnwodkaerBecruoS-etaG ]1[ I SG neponiard,Am30.0=V 0 1-8 - VB ODG egatloVnwodkaerBniarD-etaG ]1[ I DG nepoecruos,Am30.0=V 0 1-8 - htRe cnatsiseRlamrehTd ael-ot-noitcnujW /Cº0 51 V SD egatloVgnitarepOe cruos-niardV 5 .5 I SD tnerruCgnitarepOe cruos-niardA m5 5 SPF-3043 Low Noise pHEMT GaAs FET Product Features

  • DC-10 GHz Operation
  • 0.5 dB NF MIN @ 2 GHz
  • 22 dB G MAX @ 2 GHz
  • +32 dBm OIP3 (5V,40mA)
  • +20 dBm P1dB (5V,40mA)
  • Low Current, Low Cost
  • Apps circuits available for key bands

Applications

  • Analog and Digital Wireless Systems
  • 3G, Cellular, PCS
  • Fixed Wireless, Pager Systems
  • Driver Stage for Low Power Applications Sirenza Microdevices’ SPF-3043 is a high performance 0.25µm pHEMT Gallium Arsenide FET. This 300µm device is ideally biased at 3V,20mA for lowest noise performance and battery powered requirements. At 5V,40mA the device can deliver OIP3 of 32dBm. It provides ideal performance as a driver stage in many commercial and industrial LNA applications. Typical Gain Performance Frequency (GHz) Gain, Gmax (dB) Gmax Gain [1] 100% tested - DC parameters tested on-wafer, insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from 500 devices across 5 wafers, 3 wafer lots. The test fixture is an engineering application circuit board (parts are pressed down on the circuit board). The application circuit represents a trade-off between the optimal noise match and input return loss. Pending Obsolescence Last Time Buy Date: Dec. 19, 2003

SPF-3043 Low Noise pHEMT GaAs FET

2 EDS-101772 Rev D

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com PreliminaryPending Obsolescence Absolute Maximum Ratings Typical Performance - Engineering Application Circuits (See App Note AN-043) Refer to the application note for additional RF data, PCB layouts, BOMs, biasing instructions, and other key issues to be considered. For the latest application note please visit our site at www.sirenza.com. [3] POUT= 0 dBm per tone, 1MHz tone spacing qerF )zHG( V SD )V( I QD )Am( FN NIM ]4[ )Bd( xamG )Bd( Bd1P ]5[ )mBd( 3PIO ]6[ )mBd( 09.0 30 25 2.05 .525 .519 2 50 42 3.05 .620 .022 3 09.1 30 20 5.04 .225 .519 2 50 44 5.03 .320 .022 3 [4] ZS=ΓOPT, ZL=ZL*, The input matching circuit losses have been de-emebedded. [5] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max P1dB [6] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max OIP3 Note: Optimum NF, P1dB, and OIP3 performance cannot be achieved simultaneously. Peak RF Performance Under Optimum Matching Conditions S G D ZSOPT Z LOPT qerF )zHG( V SD )V( I QD )Am( FN )Bd( niaG )Bd( Bd1P )mBd( 3PIO ]3[ )mBd( 11S )Bd( 22S )Bd( noitarugifnoC stnemmoC Biasing Details The SPF-3043 is a depletion mode FET and requires a negative gate voltage to achieve pinchoff. As such, power supply sequencing circuitry is strongly recommended to prevent damaging bias transients during turn-on. Active bias circuitry is also recommended to maintain a constant drain current from part-to-part. Junction Temperature Calculation MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF consid- erations the device operating conditions should also satisfy the following expression: P DC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (C) TL = Lead Temperature (pin 2) (C) RTH = Thermal Resistance (C/W) retemaraPl obmySe ulaVt inU tnerruCniarDI SD 06A m tnerruCetaGdrawroFI FSG 03A µ tnerruCetaGesreveRI RSG 03A µ egatloVecruoS-ot-niarDV SD 7V egatloVecruoS-ot-etaGV SG 0>RO3-<V rewoPtupnIFRP NI 51m Bd egnaRerutarepmeTegarotST rots 051+OT04-C noitapissiDrewoPP SSID 024W m erutarepmeTnoitcnuJT J 051+C esuacyamstimilesehtfoenoynadnoyebecivedsihtfonoitarepO egatlovecivedeht,noitareposuounitnocelbailerroF.egamadtnenamrep ehtnideificepsseulavgnitarepomumixamehtdeecxetontsumtnerrucdna .1egapnoelbat

SPF-3043 Low Noise pHEMT GaAs FET

3 EDS-101772 Rev D

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com PreliminaryPending Obsolescence 02468 1 0 -60 -50 -40 -30 -20 -10 02468 1 0 -60 -50 -40 -30 -20 -10 Typical Performance - De-embedded S-Parameters Note: S-parameters are de-embedded to the device leads with ZS=ZL=50Ω . The device was mounted on a 0.010” PCB with plated-thru holes close to pins 2 and 4. De-embedded s-parameters can be downloaded from our website (www.sirenza.com). Gain, Gmax (dB) Gain vs Frequency (3V,20mA) Gain, Gmax (dB) Gain vs Frequency (5V,40mA) Gain Gmax Gain Gmax Frequency (GHz) Frequency (GHz) S11,S22 vs Frequency (3V,20mA) S11,S22 vs Frequency (5V,40mA) Isolation (dB) Isolation (dB) 0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0

1 GHz

4 GHz

10 GHz

8 GHz

6 GHz

3 GHz

2 GHz

0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0 Typical Performance - Noise Parameters qerF )zHG( V SD )V( I SD )Am( FN NIM ]7[ )Bd( ΓΓΓΓΓ TPO xamG )Bd( [7] ZS=ΓOPT, ZL=ZL*, NFMIN is a noise parameter for which the input matching circuit losses have been de-emebedded. The noise parameters were measured using a Maury Microwave Automated Tuner System. The device was mounted on a 0.010” PCB with plated- thru holes close to pins 2 and 4.

SPF-3043 Low Noise pHEMT GaAs FET

4 EDS-101772 Rev D

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com PreliminaryPending Obsolescence Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. LC 5. DIE IS FACING UP FOR MOLD AND FACING DOWN 2.25 LC 6. PACKAGE SURFACE TO BE MIRROR FINISH. FOR TRIM/FORM. ie :REVERSE TRIM/FORM. SYMBOL 4. ALL SPECIFICATIONS COMPLY TO EIAJ SC70. 2. DIMENSIONS ARE INCLUSIVE OF PLATING. 3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH 1. ALL DIMENSIONS ARE IN MILLIMETERS. & METAL BURR. NOTE: 0.25 0.10 0.10 0.00 0.80 1.80 0.80 1.85 1.15 MIN b c e HE A D E

0.65 BSC

0.40 0.18 0.40 0.10 1.00 2.40 1.10 1.35 MAX L 0.10 0.30 b1 0.55 0.70 D e HE e E b b1 L C A Package Dimensions Use multiple plated-through vias holes located close to the package pins to ensure a good RF ground connection to a continuous groundplane on the backside of the board. Recommended PCB Layout SOT-343 Package Plated Thru Holes (0.020" DIA) Ground Plane Pin Designation #niPn oitcnuFn oitpircseD 1e taGs aiBetaG/tupnIFR 2e cruoSd aelecuderotselohaivesU.dnuorgotnoitcennoC .elbissopsasdaeldnuorgotesolcsasaivecalP.ecnatcudni 3n iarDs aiBniarD/tuptuOFR 4e cruoS2 niPsaemaS Pin Description rebmuNtraPe ziSleeRl eeR/seciveD 3403-FPS" 70 003 Part Number Ordering Information The part will be symbolized with the “F3” designator and a dot signifying pin 1 on the top surface of the package. Part Symbolization