SPDC12L00010 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Description
  • 2 Pin settings
  • 2.1 Pin connection and mechanical data (dimensions in mm)
  • 2.2 Pin description
  • 3 Maximum ratings
  • 3.1 Absolute maximum ratings
  • 3.2 Thermal data
  • 3.3 Thermal de-rating
  • 4 Electrical characteristi cs
  • 5 Application information
  • 5.1 Input voltage
  • 5.2 Auxiliary voltage
  • 5.3 Inhibit function
  • 5.4 Soft-start
  • 5.5 Multiple units synchroni zation
  • 5.6 Power good signal and power good delay
  • 5.7 Oscillator setting
  • 5.8 Current sink-mode
  • 5.9 Under voltage lock out
  • 5.10 Program setting
  • 5.11 Voltage sensing
  • 5.12 Output voltage programming
  • 5.13 Additional loop compensation
  • 5.14 Output over voltage protection
  • 5.15 Current limitation
  • 5.16 Thermal shutdown
  • 5.17 Signal ground and power ground
  • 5.18 Input capacitors

Features

■ MTBF 1 000 000 (TA = 25 °C) ■ 10 A max output current ■ Input voltage range from 1.8 V to 14 V ■ Supply voltage range from 4.5 V to 14 V ■ Fixed or adjustable output voltage down to 0.6 V ■ Fixed frequency voltage mode control ■ Adjustable switching frequency ■ Soft-start and inhibit ■ Selectable UVLO threshold (5 V or 12 V bus) ■ Master/slave synchronization with 180° phase shift ■ Pre-bias start-up capability ■ Selectable source/sink or source only capability after soft-start ■ Power Good output with programmable delay ■ Over voltage protection with selectable latched/not-latched mode ■ Thermal shut-down ■ Operating temperature range -40 °C ÷ 85 °C

Applications

■ Laptop ■ Blade servers ■ RAID systems ■ Network routers ■ Cellular base stations ■ Industrial equipment ■ Test instrumentation ■ Medical diagnostic equipment ■ Points of load regulation Table 1. Device summary

1 Description

The ST SPDC12L00010 high density 10 A DC-DC converter is a complete step-down power supply. A single LGA package includes ST switching controller, power FETs, inductor and all the support components. SPDC12L00010 operates over a wide input voltage range of 1.8 V to 14 V, supporting an output range of 0.6 V to 5 V. High level of integration and synchronous rectification allows the SPDC12l00010 to deliver up to 10 A continuous current at up to 93% efficiency, without external heat sink or airflow. The device is a complete stand alone surface mount power supply, that can be handled and assembled like a standard integrated circuit. Moreover its low profile design permits the SPDC12L00010 to be soldered onto the back side of a printed circuit board, freeing up valuable board space. SPDC12L00010 is self protected against over voltage and short circuit conditions. A built in adjustable soft-start and inhibit guarantee correct functionality whatever the load is. Pre-bias start up capability is in place as well Power Good output with programmable delay to avoid false signals. The device is packaged in a thermally enhanced, compact (15 x 15 mm) and low profile (3 mm) over molded land grid array (LGA) package, suitable for automated assembly by standard surface mount equipment. The SPDC12L00010 is Pb-Free and RoHS compliant.

2 Pin settings

2.1 Pin connection and mechan ical data (dimensions in mm)

Figure 1. Pin connection

2.2 Pin description

Table 2. Pin description can be increased or decreased. In OVP status the pin is pulled to 4.5 V (latched mode only). Using this pin it is possible to recover the voltage drop on Vout track.

introduced on the falling edge of PG signal. connecting the SYNC pins together.

  • Setting UVLO threshold for 5 V or 12 V bus.

All references are referred to these pins, internally connected to PGND. This pin is connected to the error amplifier inverting input. This pin is connected to the error amplifier output. This pin can be used to inhibit the module. Bank 1 VIN DC input voltage. See Section 5.18 on page 18 for mandatory condition. Bank 2 PGND Return for input/output voltage source. Bank 3 VOUT Regulated power output. See Section 5.19 on page 18 for mandatory condition. see Section 5.20 on page 19 for details. Table 2. Pin description (continued)

3 Maximum ratings

3.1 Absolute maximum ratings

3.2 Thermal data

Table 3. Absolute maximum ratings Table 4. Table 3. Thermal data

3.3 Thermal de-rating

temperature to the maximum allowable value. thermal de-rating is to measure the module temperature in the final application condition. the maximum temperature allowable value at T1 is 125 °C. Figure 2. Measurement points for thermal de-rating (top side) 25 cm2, 4 layers, 1.6 mm FR4 printed circuit board. Table 5. Thermal de-rating for Vout = 5.0 V

Table 6. Thermal de-rating for Vout = 3.3 V Table 5. Thermal de-rating for Vout = 5.0 V (continued)

Table 7. Thermal de-rating for Vout = 2.5 V Table 8. Thermal de-rating for Vout = 1.8 V Table 9. Thermal de-rating for Vout = 1.2 V

4 Electrical characteristics

Table 10. Electrical characteristics

5 Application information

5.1 Input voltage

VIN (bank 1), for power circuit voltage supply. if VIN is lower than 4.5 V, VCC must be supplied separately. The recommended maximum operating DC input voltage is 14 V.

5.2 Auxiliary voltage

VAUX (pin J11) pin must be used to supply PRG and OS setting resistors.

5.3 Inhibit function

SS_INL (pin L11) allows putting the device in stand-by mode. reduced to 5 mA, for VIN = 12 V. With SS_INL higher than 0.5 V the device is enabled. Figure 3. Inhibit function

5.4 Soft-start

The soft-start phase begins when both VCC and VIN raise above their turn-on thresholds, otherwise the SS_INL pin is internally shorted to SGND. A ramp is generated at SS_INL pin during start-up, charging the external capacitor CSS with an internal current generator. The initial value for this current is 30 μA and it charges the capacitor up to 0.5 V, after that, it is reduced to 10 μA until the final charge value approximately 4 V. In the meanwhile, the controller internal voltage reference raises to its final value, following the SS_INL pin voltage slope. During soft-start, the module provides a constant current protection, limiting the output current at the maximum value, without entering in HICCUP mode. If there is not current limitation, the output voltage slope follows the SS_INL pin slope. The output voltage rise time, can be set choosing proper CSS value. The soft-start phase ends when the SS_INL pin voltage reaches 3.5 V. A capacitor CSS = 3 3 nF is present on the module, to perform a minimum soft-start time, suitable for Co = 10000 μF max. output capacitor; in this condition and with 10 A output current resistor load, the output voltage rise time is around 5ms, but the complete soft-start time is around 10ms. Using the minimum output capacitor Co = 660 μF and with 10 A resistor load, the output voltage rise time is around 2 ms.

5.5 Multiple units synchronization

Using more than one unit on the same circuit, it is possible to synchronize the switching frequency oscillators, connecting all SYNC (pin L6) together. The device with the higher switching frequency will be the Master, while the other will be the Slaves. The best way to synchronize two or more devices is to set same switching frequency, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. Using and external clock signal, to synchronize one or more devices working at a different switching frequency, it is recommended to follow the below formula: f sw ≤ fext ≤ 1.3fsw The phase shift between master and slaves is approximately 180°.

5.6 Power Good signal and Power Good delay

The output voltage is monitored by FB (pin L9), if it is not within ± 10% (typ.) of the programmed value, the PG (pin L4) output is forced low. The PG signal can be delayed by adding an external capacitor on PGDL Y (pin L5), the delay can be calculated with the following formula: PGdelay = 0.5 x CPGDL Y(pF) [μs]

5.7 Oscillator setting

The switching frequency is internally fixed to 729 kHz, this value can be slightly varied using an external resistor ROS connected between OS (pin K11) and SGND (L8) or VAUX (pin J11). Since the OS pin is maintained at fixed voltage (typ. 1.2), the frequency is increased/decreased proportionally to the current sunk/sourced from/into the pin. In particular, connecting ROS to SGND the frequency is increased according the following formula: fSW = 729 + (9.88x106/ROS) [kHz] Connecting ROS to VAUX the frequency is reduced according to the following formula: fSW = 729 - (30.1x106/ROS) [kHz]

5.8 Current sink-mode

Connecting a proper resistor (see par. Section 5.10 on page 15) from PRG (pin L7) to VAUX (pin J11), it is possible to select the sink-mode operation, that means to allow the output current to reverse its polarity into the converter output inductor. If the sink-mode is enabled, the converter can sink current from the load after soft-start; If the sink-mode is disabled, the converter never sinks current. Note: When output low current operation is required (Iout < 2 A), sink-mode operation is recommended, this condition improves output voltage transient response and reduces output voltage ripple.

5.9 Under voltage lock out

8.6 V/7.7 V for 12 V input range.

5.10 Program setting

5.11 Voltage sensing

Using VSENSE (pin L2) it is possible to recover the voltage drop on VOUT PCB track. Connect VSENSE in a point closed to the load (see Figure 4). Using VSENSE connection, it will not recover the voltage drop on PGND PCB track. Leaving VSENSE floating, the output voltage will be sensed at VOUT (bank 3). Figure 4. Voltage sensing Table 11. Program setting

5 V range

12 V range

5.12 Output voltage programming

L2), it is possible to change the output voltage. Connecting the resistor to VSENSE the output voltage decrease (see Figure 5 b). The module output voltage is 1.2 V with Rx = n.c. Figure 5. Output voltage programming

5.13 Additional loop compensation

VSENSE (pin L2) (see Figure 6 b). Figure 6. Additional loop compensation

5.14 Output over voltage protection

The device provides OVP: when the voltage sensed on FB (pin L9) reaches a value greater than 20% of reference, the on module low side driver is turned ON and the converter stop switching operation. If the OVP not latched mode has been set, the on module low side MOSFET is kept ON, as long as the over voltage condition is detected. If OVP latched mode has been set, the low side MOSFET is turned ON and the OS (pin K11) is forced high (4.5 V typ.), until VCC is toggled. It must be taken in account that there is an electrical network between the output terminal and FB, therefore the voltage at this pin is not a perfect replica of output voltage. If the converter is set to sink current, the low side MOSFET could be turned ON before the output voltage exceeds the over voltage threshold (109% typ.), because the error amplifier will change its balance in advance. If the sink-mode is disabled, the low side MOSFET will be turned ON only when the OVP operate, in this case a delay between the output voltage rising and the FB rising can appear and the OVP can operate late (126% typ.).

5.15 Current limitation

The device realizes the over current protection sensing the current on board high side MOSFET and on board low side MOSFET, therefore two current limits are set: peak current limit and valley current limit. The peak current protection is active when the high side MOSFET is turned ON, the valley current protection is enabled when the low side MOSFET is turned ON. After soft-start is completed, if an over current occurs, the device enters in HICCUP mode: both high side and low MOSFETs are turned OFF; the soft-start capacitor is discharged with a 10 μA constant current; when the voltage on SS_INL (pin L11) reaches 0.5 V the soft-start phase restart. During the soft-start phase the OCP provides a constant current protection.

5.16 Thermal shutdown

When the controller junction temperature reaches 150 ± 10 °C, the device shutdown. Both MOSFET are turned OFF and the soft-start capacitor is discharged. The device does not restart until the junction temperature goes down to 120 °C and until the voltage on the soft-start capacitor reaches 0.5 V.

5.17 Signal ground and power ground

SGND (L8) and PGND (bank 2) are connected together on the module. Connect to SGND the capacitor for PGDL Y and SS_INL, the resistor for FB and OS. Connect to PGND the return for SS_INL. the application circuit (see Figure 7). Figure 7. Signal ground and power ground

5.18 Input capacitors

The input capacitor present on the module is not able to sustain the input RMS current. PGND (bank 1 and bank 2), to satisfy minimum functional requirement. the application requirement.

5.19 Output capacitors

The output capacitors present on the module are able to sustain output RMS current.

5.20 Phase connection

On the module bottom, there is an area relative to PH (bank 4) connection: this area is internally connected to the high side MOSFET source and to the low side MOSFET drain; this electrical point is used to dissipate heat generated by the two MOSFETs. Connect PH (bank 4), to an insulated copper area on the mother board, to ensure proper heat sink. Since the PH signal contains very fast voltage transients, it is recommended to take in account possible inducted noise on mother board, i.e.: it is advised against to lead under the module printed circuit board tracks with susceptible signals.

6 Package mechanical data

conditions are also marked on the inner box label. ECOPACK is an ST trademark. Figure 8. Package mechanical data

6.1 Soldering

phenomenon, particular attention has to be take on the set up of the peak temperature. IPC/JEDEC J-STD-020C, July 2004 recommendations. Figure 9. Soldering Table 12. Soldering

6.2 PCB footprint

Use Figure 10 as suggested PCB footprint. Figure 10. PCB footprint for SPDC12L00010 (dimensions in mm)

7 Revision history

Table 13. Document revision history